JPH09259030A - Multi-cpu device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-CPU device where plural CPU can easily access the storage circuit (S-RAM circuit and D-RAM circuit, for example) of a single port through a bus line of one system with a simple constitution. SOLUTION: A control preferential selection circuit A monitors a chip selection signal outputted from CPU 1 and CPU 2, decides control priority right, outputs a master 1-n signal or a master 2-n signal, gives the master 1-n signal to a generation circuit B, a generation circuit C and a generation circuit D and gives the master 2-n signal to a generation circuit E and a generation circuit G. A CPU 1 READY response timing generation part B decides timing for terminating the access cycle of CPU 1, generates a READY signal (b) and gives it to CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-CPU device, for example, a plurality of CPUs having one S (Static).
c) -Applicable to devices that access RAM circuits.

[0002]

2. Description of the Related Art In recent years, memory devices have been actively developed, and S-RAM, D (Dynamic) -RAM and D-RAM have been developed.
PM (Dual Port MEMORY) and the like are widely used.

For example, the S-RAM has one port for writing and reading, and it is relatively easy to increase the capacity.
It is cheap. On the other hand, the DPM has two ports for writing and reading, can be simultaneously accessed by two types of microprocessor (MPU) masters, and has a small capacity and is expensive.

[0004]

As described above, the dual port memory can be accessed by the masters of two types of microprocessors, but it has a small capacity and is expensive. Therefore, when a large amount of information is handled by the dual port memory, it can be realized by using a plurality of dual port memories, but there is a problem that it becomes considerably expensive.

Therefore, a large-capacity and inexpensive S-RAM is used to provide a multi-CPU device which can be accessed from a plurality of CPUs (or microprocessors) as if they were accessing a dual-port memory. Was wanted.

For this reason, a plurality of CPUs are connected to a single-port memory circuit (for example, an S-RAM circuit or a D-RAM circuit) through a bus line of one system.
There is a demand for realization of a multi-CPU device that can be easily accessed from a simple configuration.

[0007]

Therefore, the present invention provides a multi-CPU device in which a plurality of CPUs access a single-port memory circuit through a bus line of one system.
The above-mentioned problems are solved by the following characteristic configurations.

That is, the present invention (1) monitors the active / inactive state of the chip select signals output from the CPUs, and when the chip select signals from two or more CPUs compete at the same time, , "Arbitration means" which gives a control right instead of the control request for these plurality of chip select signals and outputs a control right signal, and waits for the control request during the period when the control right is not given. And (2) generate a control permission response signal for giving control permission to the CPU corresponding to the control right signal, give it to the CPU, and control the CPU outputting the chip select signal waiting for control. “Control permission / permission waiting response signal generating means” for giving a waiting response signal, and (3)
An address from the CPU to which control permission is given is given to the memory circuit through the bus line, and a chip select signal for the memory circuit is generated based on the control right signal so as to correspond to the access time of the memory circuit and given to the memory circuit. "Memory circuit chip select signal generating means".

With such a structure, the "arbitration means" of (1)
However, when a control request is issued by a chip select signal generated from a plurality of CPUs at the same time, a control right for the plurality of CPUs is given instead by giving an alternative control right to the CPU requesting the control. Can be given evenly and a plurality of processes can be easily performed at the same time.

Then, the "control permission / permission waiting response signal generating means" of (2) generates a control permission response signal in response to the control authority signal for each CPU instead of each CPU,
Give to PU. The control permission response signal is, for example, a ready signal or an enable signal.
Signals etc. are preferred. On the other hand, each CPU requesting control
In place of the control permission response signal, the CPU waits for control by giving the control permission wait response signal during the period when the control permission is not given.

Furthermore, by (3) "memory circuit chip select signal generating means", the CPU which receives the control permission response signal generates an address and a chip select signal and gives them to the memory circuit through the bus line. Multiple CPs
The memory circuit can be accessed in an orderly manner without collision of the address and the chip select signal from U.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. Therefore, in this embodiment, a control priority selection unit A that monitors chip select signals from a master, which is a plurality of microprocessors, and gives control right to the master, and READY response timing generation units B and E. , S- is the address of the master to which control is given.
A bus arbitration device including address buffer control timing generation units C and F that are significant for RAM and chip select input timing generation units D and G that generate a chip select signal considering the access time of S-RAM is configured. .

FIG. 1 is a functional block diagram of a multi-CPU device. In FIG. 1, the multi-CPU device is mainly C
PU1, CPU2, bus arbitration circuit 10, CPU1
Address buffer circuit H, AND circuit 9, CPU 2
Address buffer circuit I, S-RAM circuit 8, CP
It is composed of a U1 data buffer circuit J and a CPU2 data buffer circuit K.

The bus arbitration circuit 10 includes a control priority selection circuit A.
And CPU1READY response timing generator B and C
PU1 address buffer control timing generation circuit C,
A CPU1 chip select input timing generation circuit D,
CPU2READY response timing generation circuit E and CP
U2 address buffer control timing generation circuit F and C
It comprises a PU2 chip select input timing generation circuit G.

The configuration of FIG. 1 is mainly provided with two types of bus masters, CPU1 and CPU2,
When accessing the S-RAM circuit 8, which is a common memory, means for selecting the priority of each CPU, address bus driver control timing means when the priority is acquired, and timing generation of the READY response And means for performing bus arbitration.

CPU1 address buffer circuit H and CP
An address bus is formed between the U2 address buffer circuit I and the S-RAM circuit 8. Also, CPU
A data bus is also formed between the 1-data buffer circuit J, the CPU 2 data buffer circuit K, and the S-RAM circuit 8. CPU1 and CPU for these buses
The bus arbitration circuit 10 arbitrates the access from the access point 2.

The CPU 1 is an internal microprocessor, for example, an NEC MPU V.I. 53, this MPU sets the system clock to 10MHz, WAI
One cycle without T is set as two system clocks, an address is given to the CPU1 address buffer circuit H, and data is C
It is supplied to the PU1 data buffer circuit J, the chip select signal master1cs-n is supplied to the control priority selection circuit A, and the READY signal is received from the CPU1READY response timing generation circuit B.

The CPU 2 is an internal microprocessor, for example, an Intel MPU 80186XL.
This MPU uses 16M as the system clock.
1 Hz is used as 4 system clocks, an address is supplied to the CPU2 address buffer circuit I, data is supplied to the CPU2 data buffer circuit K, and a chip select signal master2cs-n is supplied to the control priority selection circuit A. The READY signal is received from the CPU2READY response timing generation circuit E.

The control priority selection circuit A includes a CPU 1, a CPU
2 outputs the chip select signal master1c
s-n, master2cs-n are monitored, control priority is determined, master1-n signal or master2
-N signal is output, and master1-n signal is output to CPU1.
It is given to the READY response timing generation unit B, the CPU1 address buffer control timing generation circuit C, and the CPU1 chip select input timing generation circuit D.
The ter2-n signal is given to the CPU2READY response timing generation circuit E, the CPU2 address buffer control timing generation circuit F, and the CPU2 chip select input timing generation circuit G.

The CPU1 READY response timing generation circuit B determines the timing for ending the access time of the CPU 1, generates the READY signal b, and outputs the C signal.
Give to PU1.

The CPU 1 address buffer control timing generation circuit C has an address input to the S-RAM circuit 8,
The timing for enabling other necessary signals is determined, and the timing signal c is given to the CPU1 address buffer circuit H and the CPU1 data buffer circuit J.

The CPU 1 chip select input timing generation circuit D determines the chip select input timing in consideration of the access timing to the S-RAM circuit 8 and supplies the timing signal d to the AND circuit 9.

The CPU2 READY response timing generation circuit E determines a timing for ending the access cyclo of the CPU 2 and gives a READY signal e to the CPU 2.

The CPU 2 address buffer control timing generation circuit F has an address input to the S-RAM circuit 8,
The timing for enabling other necessary signals is determined and the timing signal f is given to the CPU2 address buffer circuit I and the CPU2 data buffer circuit K.

The CPU2 chip select input timing generation circuit G determines the chip select input timing in consideration of the access time of the S-RAM8 circuit and supplies the timing signal g to the AND circuit 9.

The CPU1 address buffer circuit H has a CP
It is controlled by the timing signal c generated by the U1 address buffer control timing generation circuit C and gives an address to the common S-RAM circuit 8 through the address bus.

The CPU2 address buffer circuit I has a CP
It is controlled by the timing signal f generated by the U2 address buffer control timing generation circuit F and gives an address to the common S-RAM circuit 8 through the address bus.

The AND circuit 9 receives the timing signal d from the CPU1 chip select input timing generation circuit D and
A logical product is performed with the timing signal g from the CPU2 chip select input timing generation circuit G, and this logical product signal ramcs-n is given as a chip select signal to the S-RAM circuit 8.

The S-RAM circuit 8 includes one or more S-RAM circuits.
It is composed of RAMIC and C by address bus
The address is received from the PU1 address buffer circuit H or the CPU2 address buffer circuit I, and the chip select signal is sent from the AND circuit 9 as the logical product signal ramcs-n.
And receives and stores the data from the CPU1 data buffer circuit J or the CPU2 data buffer circuit K through the data bus and reads the data.

CPU1 data buffer circuit J and CPU
The data bus is controlled by the timing signal c from the 1 address buffer control timing generation circuit C, and the data from the CPU 1 is stored in the S-RAM.
The data is supplied to the circuit 8 and the data from the S-RAM circuit 8 is supplied to the CPU 1.

The CPU2 data buffer circuit K is a CPU
Controlled by the timing signal f from the 2-address buffer control timing generation circuit F, the data bus is controlled, and the data from the CPU 2 is stored in the S-RAM.
The data is supplied to the circuit 8 and the data from the S-RAM circuit 8 is supplied to the CPU 2.

FIG. 3 is a detailed circuit configuration of an example of the control priority selection circuit A. In FIG. 3, the control priority selection circuit A includes a logic circuit R1 and register circuits REG1 to RE.
It is composed of G4 and a decoder circuit A1.

The logic circuit R1 receives the chip select signal master1cs-n from the CPU1 and further receives CP.
It receives the chip select signal master2cs-n from U2, arbitrates the control priority, and registers REG1 to REG1.
Control data is set for REG4 using a clock of 10 MHz. The decoder circuit A1 includes a register RE
The control data of G1 to REG4 is decoded to decode the decode signal master1-n or the decode signal master2.
-N is generated and output.

Each constituent circuit of the bus arbitration circuit 10 described above is
The decode signals master1-n and the decode signal ma, which are control signals, are controlled by an arbitrary clock applied.
Synchronous control is performed corresponding to star2-n. That is, CP
Chip select signal master1cs from U1 and U2
-N and master2cs-n conflict with each other, a control right is given instead of a control request for these chip select signals to give a control right signal master1-.
n and master2-n are output, and the control request is waited for during the period when the control right is not given.

(Operation): Next, the multi CPU of FIG.
The operation of the device will be described. First, the chip select signal master1cs- for the common S-RAM circuit 8 output from the CPUs 1 and 2 which are two types of bus masters.
The control priority selection circuit A monitors n and master2cs-n. The two types of bus masters, CPU1 and CPU2, simultaneously perform chip select signals master1cs-n, m.
When the aster2cs-n is output, the control right is given to the CPU1, and when it is not simultaneous, the CPU that has output
To the two CPUs 1 and 2 when both chip select signals are fixed to the significant state.

The control priority selection circuit A selects the control right grant. When the master CPU is determined by the provision of the control priority selection circuit A, the CPU 1 address buffer control timing corresponding to the access time of the common S-RAM circuit 8 and the data sampling position in the access time of the CPU is considered. Timing signal c of generation circuit C
And CPU1 chip select input timing generation circuit D
Or the timing signal of the CPU2 address buffer control timing generation circuit F and the timing signal of the CPU2 chip select input timing generation circuit G are generated, and the CPU1READY response timing generation circuit is generated at the access time end time of the master CPU. The READY signal b of B or the READY signal e of the CPU2READY response timing generation circuit E is generated.

As described above, the multi-CPU of this embodiment
In the configuration of the device, “for the CPU 1 or 2 waiting for control, by delaying the response of the READY signal b of the CPU1READY response timing generation circuit B or the READY signal e of the CPU2READY response timing generation circuit E, the data bus and It is configured to arbitrate address bus contention. ”

FIG. 2 is a detailed transition diagram of an operation state of an example of the control priority selection circuit A. In FIG. 2, as the operating state of the control priority selection circuit A, operating states ST1 to ST
There are eight. The operating state ST1 is a state without access, where (0.0.0.0) is the register REG1.
~ Indicates the state of REG4 control data. That is, CPU
When reset by 1 or 2, this no access state (ST1) is set. In FIG. 2, in the no access state (ST1), what is described as (1.1) indicates (the state of the chip select of the CPU2 and the state of the chip select of the CPU1). ) Is CP
Both U1 and U2 represent a state in which the chip select is not issued. Incidentally, (1.1) is represented by negative logic.

The operating state ST2 represents the CPU1 access state, the states of the registers REG1 to REG4 are (1.0.0.0), and the no access state (ST
The chip select signal from (1) to (1.0) or (0.
0), the CPU 1 access state (ST2) is set. Further, when the chip select signal becomes (1.1) from the CPU1 access state (ST2), the state transitions again to the no access state (ST1). Also, this CP
When the chip select signal becomes (0.0) or (0.1) from the U1 access state (ST2), the state transitions to the CPU1 access / CPU2 access wait state (ST4). In this CPU1 access state (ST2), if the chip select signal is (1.0), this state is maintained.

The operating state ST3 represents the CPU2 access state, and the states of the registers REG1 to REG4 are:
(0.0.0.1), no access state (ST
When the chip select signal becomes (0.1) from 1), the CPU2 access state (ST3) is set. When the chip select signal becomes (1.1) from the CPU2 access state (ST3), the no access state (ST) is restored again.
State transition to 1). When the chip select signal becomes (1.0) or (0.0) from the CPU2 access state (ST3), the CPU2 empty access state (ST
State transition to 8).

The operating state ST4 is the CPU1 access C
It shows the state of waiting for PU2 access,
The states of 1 to REG4 are (1.0.1.0), and C
When the chip select signal becomes (0.1) from the PU1 access state (ST2), the CPU1 access / CPU
2 Access wait state (ST4) is entered. Also, this CP
When the chip select signal becomes (1.0) from the U1 access / CPU2 access wait state (ST4), C
The state transitions to the PU1 access state (ST2). Also,
This CPU1 access / CPU2 access waiting state (S
When the chip select signal becomes (1.1) from T4,
The state transits to the no access state (ST1) again. When the chip select signal becomes (0.1) or (0.0) from the CPU1 access / CPU2 access wait state (ST4), the CPU2 access wait state (ST
The state transitions to 7).

The operating state ST5 is CPU2 access C
It indicates the PU1 access wait state and
The states of 1 to REG4 are (0.1.0.1), and C
When the chip select signal becomes (0.0) or (1.0) from the PU2 empty access state (ST8), this CPU
2 access / CPU 1 access wait state (ST5). In addition, the chip select signal is (1.1) from the CPU2 access / CPU1 access wait state (ST5).
Then, the state transits to the no access state (ST1) again. Further, the chip select signal (0.
When it becomes 1), the state transits to the CPU2 access state (ST3) again. Also, this CPU2 access / CPU1
When the chip select signal becomes (1.0) or (0.0) from the access wait state (ST5), the state transitions to the CPU1 access wait state (ST6).

The operating state ST6 represents the CPU1 access wait state, the states of the registers REG1 to REG4 are (0.1.0.0), and the CPU2 access / CPU1 access wait state (ST5) changes from the chip to the chip. When the select signal becomes (1.0) or (0.0), this C
The PU1 access waiting state (ST6) is entered. This CPU
When the chip select signal becomes (1.0) or (0.0) from the one access waiting state (ST6), the state transitions to the CPU1 access state (ST2). Also, this CPU 1
When the chip select signal changes from the access wait state (ST6) to (1.1), no access state (ST1)
The state transitions to. Further, when the chip select signal changes from this CPU1 access waiting state (ST6) to (0.1), the state transitions to the CPU2 access state (ST3).

The operating state ST7 represents the CPU2 access wait state, the states of the registers REG1 to REG4 are (0.0.1.0), and the CPU1 access / CPU2 access wait state (ST4) changes from the chip to the chip. When the select signal changes to (0.1) or (0.0), the state transitions to the CPU2 access waiting state (ST7). When the chip select signal changes from this CPU2 access wait state (ST7) to (1.0), CP
The state transitions to the U1 access state (ST2). When the chip select signal changes from this CPU2 access wait state (ST7) to (1.1), the state transitions again to the no access state (ST1). Further, when the chip select signal changes from (0.1) or (0.0) from the CPU2 access wait state (ST7), the state transitions to the CPU2 access state (ST3).

The operating state ST8 represents the CPU2 idle access state, the states of the registers REG1 to REG4 are (0.1.1.1), and the chip select signal (from the CPU2 access state (ST3) is ( When it is changed to 0.0) or (1.0), the state transitions to this CPU2 idle access state (ST8). Further, the chip select signal (0.
When it changes to 0) or (1.0), CPU2 access
The state transits to the CPU1 access waiting state (ST5).
When the chip select signal changes from this CPU2 idle access state (ST8) to (1.1), the state transitions again to the no access state (ST1).

As the signal states of the registers REG1 to REG4, the states other than the operation states ST1 to ST8 of FIG.
(0.1.1.0), (1.0.0.1), (1.0.
1.1), (1.1.0.0), (1.1.0.1),
There are (1.1.1.0) and (1.1.1.1).

With such a configuration, the CPU 1 and CP
In controlling the U2, the above-mentioned operating states ST1 to ST8
If the control operation is performed only by the CPU1, the operation is performed between the state ST1 and the state ST2.
In the case of the control operation only by the operation, the operation is performed between the states ST1 and ST3.

Further, in the example of FIG. 2, when the S-RAM circuit having a long access time is used, the number of access wait states may be increased or the synchronous clock at the time of state transition may be slowed down. When using a short S-RAM circuit, the access wait state may be reduced, or the synchronous clock at the time of state transition may be increased in speed.

FIG. 4 is an operation timing chart when the chip select signals of both the CPU1 and the CPU2 continue to be fixed in the significant state. FIG. 5 is an operation timing chart when the chip select of only the CPU 1 is fixed to the significant state. FIG. 6 is an operation timing chart when the chip select of only the CPU 2 is fixed to the significant state.

In FIGS. 4 to 6, the signal (a)
~ Signal (zd) is a common signal. (A) is SY
NC-CLK2N, which represents the waveform of the 10 MHz synchronous clock of the bus arbitration circuit 10 corresponding to the CPU 2 side. (B) is CSCRAM-N (active when low level), and represents the signal of the chip select signal master1cs-n output by the CPU 1.
(C) is ALMCS-N (active when low level), and represents the signal of the chip select signal master2cs-n output by the CPU 2.

(D) is REG1OUT, which represents the waveform of the output signal of the register REG1. (E) is REG
2OUT, which represents the waveform of the output signal of the register REG2. (F) is REG3OUT, and register RE
The waveform of the output signal of G3 is shown. (G) is REG4OU
T, which represents the waveform of the output signal of the register REG4.
(H) is D0000, and represents a waveform in the state (0000) and the no access state (ST1 in FIG. 2).
(I) is a signal waveform when ALM0001-N (active at a low level) is given and the control right is given to the CPU 2.

(J) is a waveform when D0010 is the CPU 2 in the access waiting state (ST7 in FIG. 2). (K) is D0011, which is a waveform in the non-specified state of FIG. (L) is D0100 and CP
This is a waveform in the U1 access wait state (ST6 in FIG. 2). (M) is a waveform of D0101 in the CPU2 access / CPU1 access waiting state (ST5 in FIG. 2). (N) is D0110, which is the waveform in the non-specified state of FIG. (O) is a waveform when D0111 is in the CPU2 idle access state (ST8 in FIG. 2). (P) is CAP1000-N (active at low level), and represents a signal waveform when the control right is given to the CPU 1.

(Q) is D1001, and represents the waveform in the non-specified state of FIG. (R) is D1010 and represents a waveform in the CPU1 access / CPU2 access waiting state (ST4 in FIG. 2). (S) is D101
1 and represents the waveform in the non-specified state of FIG.
(T) is D1100 and represents the waveform in the non-specified state of FIG. (U) is D1101, and represents the waveform in the non-specified state of FIG.

(V) is D1110, which represents the waveform in the non-specified state of FIG. (W) is D1111 and represents the waveform in the non-specified state of FIG. (X) is
16M, which represents the signal waveform of the 16 MHz clock of the CPU 2. (Y) is SYNC-CLK1, which is 10 MH of the bus arbitration circuit 10 corresponding to the CPU 1 side.
It is a waveform of a synchronous clock of z. (Z) is CAPAC
CCS-N (active at low level),
The waveform of the CPU1 address buffer enable signal c is shown. (Za) is CAPCRAMRDY-N (active at low level), and CPU1 response READ
The waveform of the Y signal b is shown.

(Zb) is ALMACCCS-N (active at low level) and represents the waveform of the address buffer enable signal f of the CPU 2. (Zc)
Represents the waveform of the response READY signal e to the CPU 2, which is ALMRDY and is active when it is at a high level. (Zd) is CRAMCS-N (active when low level) and represents the waveform of the input chip select signal ramcs-n to the S-RAM circuit 8.

(Operation when the chip select of only the CPU1 is fixed to the significant state): In FIG. 5, the chip select signal master1 output from the CPU1 of FIG.
The CSCRAM-N signal, which is cs-n, outputs a low level (active) for the CPU 1 to acquire the control right. On the other hand, the chip select signal master2cs-n output from the CPU 2 in FIG.
The SN signal is at a high level (inactive) because it is not trying to acquire the control right. REG1 which is an output signal of the registers REG1 to REG4 in (d) to (g)
Regarding OUT to REG4OUT, only REG1OUT is at a high level (logic 1), and the rest of them maintain a low level (logic 0).

The D0000 signal, which represents the no access state (0000) in (h), maintains a high level.
It represents that the control right is given to the CPU 2 of (i),
Since the ALM0001-N signal is at high level (inactive), the control right is not given. (J)
The D0010 signal indicating that the CPU 2 is waiting for access is at a high level (inactive). It is the D0011 signal which is in the out-of-specification state of (k) and maintains a high level. The D0100 signal indicating the CPU1 access waiting state of (l) is at a high level (inactive).

The D0101 signal indicating the CPU2 access / CPU1 access waiting state of (m) is at a high level (inactive). The D0110 signal indicating the non-regulated state of (n) maintains the high level. The D0111 signal representing the CPU2 empty access state of (o) is at a high level (inactive). (P) CPU
The CAP1000-N signal, which indicates when the control right is given to 1, is at a low level (active). (Q)
The D1001 signal representing the non-regulated state of is maintained at the high level. The D1010 signal indicating the CPU1 access / CPU2 access waiting state of (r) is at a high level (inactive).

The D1011 signal indicating the out-of-specification state of (s) is maintained at a high level (inactive).
The D1100 signal indicating the out-of-specification state of (t) also maintains the high level (inactive). D1101 representing the non-regulated state of (u) also maintains a high level (inactive). D1110, which represents the non-regulated state of (v), also maintains a high level (inactive). D1111, which represents the non-regulated state in (w), is also high level (inactive)
Has been maintained. The CAPACCCS-N signal representing the CPU1 address buffer enable signal c of (z) is
High level (inactive) and low level (active) are repeated. The low-level period is long and the high-level period is 3 to 4 clock cycles.

(Za) CPU1 response READY signal b
The CAPCRAMRDY-N signal that represents is repeatedly high level (inactive) and low level (active). The high-level period is long and the low-level period has a width of about two clock cycles. C of (zb)
A, which is the address buffer enable signal f of PU2,
The LMACCCS-N signal is at high level (inactive). Response R of (zc) to CPU2
The ALMRDY signal, which represents the EADY signal e, is at a low level (inactive). (Zd) S-RA
The CRAMCS-N signal, which is the input chip select signal ramcs-n to the M circuit 8, repeats high level (inactive) and low level (active). The high level period and the low level period are almost the same and have a width of about two clock cycles.

As described above, the CPU 2 waits and the C
When the chip select of only PU1 is fixed to the significant state, the restricting right is granted to only CPU1.
It is a simple operation.

(Operation when the chip select of only the CPU2 is fixed to the significant state): In FIG. 6, the chip select signal master1 output from the CPU1 of (b).
The CSCRAM-N signal, which is cs-n, is high level (inactive) because the CPU 1 does not acquire the control right.
Is output. ALMCS, which is the chip select signal master2cs-n output by the CPU 2 in (c).
The -N signal is at a low level (active) to acquire the control right. Registers REG1 to (d) to (g)
REG1OUT to REG4O which are output signals of REG4
In UT, only REG4OUT is at high level (logic 1)
Then, all others are kept at the low level (logic 0).

The D0000 signal, which represents the no access state (0000) in (h), maintains a high level.
It represents that the control right is given to the CPU 2 of (i),
ALM0001-N signal is low level (active)
It has become. The D0010 signal indicating that the CPU 2 in (j) is in an access waiting state is at a high level (inactive). It is the D0011 signal which is in the out-of-specification state of (k) and maintains a high level. (L) CPU
The D0100 signal, which indicates a one-access waiting state, is at a high level (inactive). D0101 showing the CPU2 access / CPU1 access waiting state of (m)
The signal is high level (inactive).
The D0110 signal indicating the non-regulated state of (n) maintains the high level. The D0111 signal representing the CPU2 empty access state of (o) is at a high level (inactive).

The CAP1000-N signal, which indicates when the control right is given to the CPU 1 in (p), is at a high level (inactive). D1 representing the non-regulated state of (q)
The 001 signal maintains the high level. (R) C
D, which represents the state of waiting for PU1 access / CPU2 access
The 1010 signal is at high level (inactive). The D1011 signal indicating the non-regulated state of (s) is maintained at the high level (inactive). The D1100 signal indicating the out-of-specification state of (t) also maintains the high level (inactive). D1 representing the non-regulated state of (u)
101 also maintains a high level (inactive).
D1110, which represents the non-regulated state of (v), also maintains a high level (inactive). D1111, which represents the non-specified state in (w), also maintains a high level (inactive).

The CAPACCCS-N signal (z), which represents the CPU1 address buffer enable signal c, becomes high level (inactive). CAPCRAMRDY-N representing the CPU1 response READY signal b of (za)
The signal becomes high level (inactive). (Zb)
The ALMACCCS-N signal, which is the address buffer enable signal f of the CPU 2 of, repeats high level (inactive) and low level (active). It is low level (active) for most of the period. (Z
c) represents a response READY signal e to the CPU 2,
The ALMRDY signal repeats low level (inactive) and high level (active). It is at low level (active) for most of the period.

(Zd) CRAMCS-, which is the input chip select signal ramcs-n to the S-RAM circuit 8.
The N signal repeats high level (inactive) and low level (active). The high level period and the low level period are almost the same and have a width of about two clock cycles.

As described above, the CPU 1 is made to stand by,
When the chip select of only the CPU 2 is fixed to the significant state, the operation of giving the control right to only the CPU 2 is performed, which is a simple operation.

(Operation when both chip select signals of CPU1 and CPU2 are continuously fixed to the significant state):
In FIG. 4, the CSCR, which is the chip select signal master1cs-n output from the CPU 1 in (b),
The AM-N signal is low level (active).
(C) Chip select signal mas output by CPU2
The ALMCS-N signal, which is ter2cs-n, is also low level (active). Here, the chip select signals of the CPUs 1 and 2 are generated at the same time. (D) ~
The output signals REG1OUT to REG4OUT of the registers REG1 to REG4 in (g) repeat high level and low level. The D0000 signal indicating the no access state (0000) in (h) maintains the high level.

The ALM0001-N signal (i), which indicates that the CPU 2 is given the control right, switches between a high level (inactive: non-control right granted) and a low level (active: control right granted). It's repeating badly.
The CPU 2 of (j) represents the access waiting state, D001
The 0 signal repeats high level (inactive: non-control right grant) and low level (active: control right grant). The high level period is long and the low level (granting control right) occurs twice in the width of one clock cycle.
(K) is a D0011 signal that is in an out-of-specification state and maintains a high level.

The signal D0100, which represents the CPU 1 access waiting state (1), repeatedly repeats high level (inactive) and low level (active). The high-level period is long and the low-level period is twice in the width of one clock cycle. (M) CPU2 access / CP
The D0101 signal, which represents the U1 access wait state, repeats high level (inactive) and low level (active). The high-level period is long and the low-level period is twice in the width of one clock cycle. (N)
The D0110 signal representing the non-regulated state of is maintained at the high level.

(O) represents the CPU2 idle access state,
The D0111 signal repeats high level (inactive) and low level (active). The high-level period is long and the low-level period is twice in the width of one clock cycle. The CAP1000-N signal, which indicates when the control right is given to the CPU 1 in (p), is at a high level (inactive) and a low level (active: control right is given).
Is repeated. The high-level period is long and the low-level period is twice in the width of one clock cycle.
The D1001 signal representing the out-of-specification state of (q) maintains the high level. (R) CPU1 access CPU
The D1010 signal, which represents the two-access waiting state, repeats high level (inactive) and low level (active). The high-level period is long and the low-level period is twice in the width of one clock cycle.

The D1011 signal indicating the non-specified state of (s) is maintained at the high level (inactive).
The D1100 signal indicating the out-of-specification state of (t) also maintains the high level (inactive). D1101 representing the non-regulated state of (u) also maintains a high level (inactive). D1110, which represents the non-regulated state of (v), also maintains a high level (inactive). D1111, which represents the non-regulated state in (w), is also high level (inactive)
Has been maintained.

The CAPACCCS-N signal (z) representing the CPU1 address buffer enable signal c repeats high level (inactive) and low level (active: enable). The high-level period is long, and the high-level period is low level about twice in the width of 3 to 4 clock cycles. (Za) CPU1 response READY
The CAPCRAMRDY-N signal representing the signal b repeats high level (inactive) and low level (active: enable). The high-level period is long and the low-level period is about twice in one clock cycle.

The ALMACCCS-N signal, which is the address buffer enable signal f of the CPU 2 in (zb), is
High level (inactive) and low level (active: enable) are repeated. The high level period and the low level period are almost the same and have a width of about 4 clock cycles. (Zc) response to CPU2 READ
The ALMRDY signal, which represents the Y signal e, repeats high level (active) and low level (inactive). The high level period is about one clock width.
The CRAMCS-N signal, which is the input chip select signal ramcs-n to the (zd) S-RAM circuit 8, is at a high level (inactive) and a low level (active).
Is repeated. The high level period and the low level period are almost the same and have a width of about two clock cycles.

In FIG. 4, the CSCR A of FIG.
The signals of both MN and ALMCS-N of FIG. 4C are fixed to a significant state (active: low level), that is, the two types of CPUs 1 and 2 are S-RAM circuits 8
4C, the CAPACCCS-N signal which is the CPU1 address buffer enable signal c of FIG. 4Z and the C of FIG.
AL which is the address buffer enable signal f of PU2
Focusing on the MACCCS-N signal, they are alternately in a significant state (active: low level). This means that the address bus, data bus, and
On the other hand, the two types of CPUs 1 and 2 do not compete with each other, and FIG.
As shown in (p), it is shown that the control right is given equally. There is a slight difference in the lengths of the low-level and high-level signals because the lengths of the system clock cycles of the CPUs 1 and 2 are different in this case.
That is, the CPU 1 has one cycle as two system clocks, and the CPU 2 has one cycle as four system clock cycles.

(Effects of the Embodiment of the Present Invention) According to the embodiments of the present invention described above, it is possible to configure a circuit having the same function as that of the multiport memory circuit by using the S-RAM circuit. A master, which is a CPU or a microprocessor, can access at any time without checking the release state of the bus of the common S-RAM circuit 8, and can perform a special operation, for example, a firmware of the bus arbitration circuit 10 or the like. The checking operation in terms of wear is unnecessary.

The control waiting time is at most the operation time of the control priority selection unit and one clock cycle of the CPU of the master on the other side. Further, even if the processing cycle periods of the CPUs 1 and 2 are different, the control right can be given and processed in response to the control request, so that the processing can be performed efficiently.

Therefore, the multi-C can easily access the single-port S-RAM circuit 8 from a plurality of CPUs through one bus line.
A PU device can be realized.

Other Embodiments: (1) In the above embodiments, the microprocessor of 80186 is used as the master of the microprocessor. However, the microprocessor of other standards or specifications is used. Even when the processor is used, it can be applied by changing the generation time of the timing generation unit.

(2) Further, by changing the control priority selection section, more microprocessors can use one S-.
A configuration for accessing the RAM circuit is also possible.

(3) Further, instead of the S-RAM circuit, D
(Dynamic) -RAM circuit, S-RAM
A memory circuit having a mixed configuration of a circuit and a D-RAM circuit may be used, or a register circuit including a register may be used. D
-RAM is a memory that requires a memory holding operation, but S-RA
Since M does not need this operation, the configuration is simple.
In the D-RAM, high speed operation can be realized by using the synchronous D-RAM.

(4) Furthermore, the multi-CPU system described above is suitable for making a small system efficient and functional by applying it to the following system, for example. That is, in the monitoring device for monitoring the failure abnormality of the transmission system and notifying the monitoring state, the first CPU for monitoring the state of the circuit of each part and detecting the abnormal portion
When an abnormal point is detected, an S-RAM circuit for storing the abnormal point as information, and a second CPU for transmitting the information stored in the S-RAM circuit to the host side every moment. It is also preferable to be composed of

[0083]

As described above, according to the present invention, when chip select signals from a plurality of CPUs compete with each other, the control right is given instead of the control request for the plurality of chip select signals. Output control right signal,
During the period in which the control right is not given, the control is made to wait for the control request, and the control permission response signal for giving the control permission to the CPU corresponding to the control right signal is generated and given to the CPU to wait for the control. By giving a control wait response signal to the CPU that is outputting the chip select signal, and generating and giving a chip select signal for the memory circuit so as to correspond to the access time of the memory circuit based on the control right signal, a single signal is obtained. To realize a multi-CPU device that easily allows a plurality of CPUs to access a port storage circuit (for example, an S-RAM circuit, a D-RAM circuit, etc.) through a single bus line. You can

[Brief description of drawings]

FIG. 1 is a functional configuration diagram of a multi-CPU device according to an embodiment of the present invention.

FIG. 2 is a detailed transition diagram of an operation state of an example of the control priority selection circuit A of the multi CPU device according to the embodiment of FIG.

3 is a detailed circuit configuration of an example of a control priority selection circuit A of FIG.

FIG. 4 is an operation timing chart when the chip select signals of both CPU1 and CPU2 of the embodiment continue to be fixed to a significant state.

FIG. 5 is an operation timing chart when the chip select of only the CPU 1 of the embodiment is fixed to a significant state.

FIG. 6 is an operation timing chart when the chip select of only the CPU 2 of the embodiment is fixed to a significant state.

[Explanation of symbols]

1, 2 ... CPU, 8 ... S-RAM circuit, 9 ... AND circuit, 10 ... Bus arbitration circuit, A ... Control priority selection circuit, B ...
CPU1READY response timing generation circuit, C ... CP
U1 address buffer control timing generation circuit, D ... C
PU1 chip select input timing generation circuit, E ... C
PU2READY response timing generation circuit, F ... CPU
2 address buffer control timing generation circuit, G ... CP
U2 chip select input timing generation circuit, H ... CP
U1 address buffer circuit, I ... CPU2 address buffer circuit, J ... CPU1 data buffer circuit, K ... CP
U2 data buffer circuit.

Claims (3)

[Claims] 1. A multi-C in which a plurality of CPUs access a single-port memory circuit through a single bus line.
In the PU device, the active / inactive state of the chip select signals output from each of the CPUs is monitored, and if chip select signals from two or more CPUs compete at the same time, these multiple chip select signals are detected. Arbitration means for giving a control right instead of the control request to the control request signal, outputting a control right signal, and waiting for the control request during the period when the control right is not given, and a CPU corresponding to the control right signal. Generate a control permission response signal for giving control permission to
A control permission / permission waiting response signal generating means for giving a control waiting response signal to the CPU outputting the chip select signal for making the control wait, and an address from the CPU given the control permission for the bus. While giving to the above memory circuit through the line,
A memory circuit chip select signal generating means for generating a memory circuit chip select signal corresponding to the access time of the memory circuit based on the control right signal and giving the memory circuit chip select signal to the memory circuit. Multi C
PU device. 2. The address from the CPU to which the control permission is given is output to an address bus line unit, and data is transmitted and received through the data bus line unit between the CPU and the memory circuit. The multi-CPU device according to claim 1. 3. The multi-CPU device according to claim 1, wherein the processing cycle period of each CPU is different.