JPH09251545A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture processor whereby picture data is read from a frame memory without reducing the processing efficiency of the picture processor in configuration where one frame memory is shared with the plural picture processors. SOLUTION: Input picture data is written in frame memory blocks 11 -1n having capacity which is one-n-th of one frame by division and data of plural picture elements in the same area are written every picture element unit in accordance with a writing address from a writing address generator 4. Picture element data which is inputted to the picture processors 31 -3n is picture data within the respectively and mutually different areas and also is the one within the same area as that of preceding time in the same picture processor. The picture processors 31 -3n executes an interpolation processing based on the input picture element data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus in which a plurality of image processors read out and control a frame memory in which input image data is written.

[0002]

2. Description of the Related Art As a conventional image processing apparatus in which a plurality of image processors read out and control a frame memory in which input image data is written, there is known an image processing apparatus having a block diagram shown in FIG. In the figure, image data is stored in the frame memory 6. The image data accumulated in the frame memory 6 is read by each of _m (m is an integer of 2 or more) image processors 7 _{1 to} 7 _m , and the read output image data is processed and output by the read image processor. It

When a plurality of image processors out of the image processors 7 _{1 to} 7 _m try to read image data from the frame memory 6 at the same time, the read arbitrator 8 is used.
By permitting access to only one image processor and causing the other image processors to wait for reading until the end of the access, collision of read access does not occur.

FIG. 4 is a block diagram of another example of the conventional image processing apparatus. In this image processing apparatus, frame memories 9 _{1 to} 9 _m are provided corresponding to the _m image processors 10 ₁ to 10 _m , respectively. As a result, each of the image processors 10 ₁ to 10 _m reads the image data from the corresponding dedicated frame memories 9 _{1 to} 9 _m without any interference with other image processors.

[0005]

However, the above-mentioned conventional image processing apparatus having the configuration of FIG. 3 has another image processor until one image processor finishes the read access to the frame memory 6. Is in a state of waiting for access, there is a problem that the processing efficiency of the plurality of image processors 7 _{1 to} 7 _m forming the apparatus is greatly impaired.

Further, the conventional image processing apparatus of the configuration shown in FIG. 4 has no problem in processing efficiency, but it requires as many frame memories for storing the entire input image data as there are image processors. However, there is a problem that the circuit scale is large and the cost is high, and the image data stored in each frame memory is the same, which is wasteful.

[0007] The present invention has been made in view of the above points,
An object of the present invention is to provide an image processing device capable of reading image data from a frame memory without lowering the processing efficiency of the image processor.

Another object of the present invention is to provide an image processing apparatus in which the capacity of the frame memory is minimized to a minimum and image data can be written without waste.

[0009]

To achieve the above object, the present invention provides a plurality of memory blocks each of which has a value obtained by dividing a predetermined total capacity into a plurality of values, and a plurality of memory blocks. A writing unit that writes input image data in pixel units, a plurality of image processors that are provided corresponding to a plurality of memory blocks and perform image processing, and pixel data that are respectively output from the plurality of memory blocks are separately provided to the plurality of image processors. And a connection switching means for sequentially switching the connection between the plurality of memory blocks and the plurality of image processors.

According to the present invention, in each of the plurality of image processors, the pixel data output from the plurality of memory blocks are separately distributed and input by the connection switching means, and the total capacity of the plurality of memory blocks is determined. It can be one frame.

Further, according to the present invention, each pixel data of a region consisting of a first plurality of pixels in the horizontal direction and a second plurality of pixels in the vertical direction of the screen represented by the input image data by the writing means is stored in a plurality of memories. Each block is written separately, and by the connection switching means, all pixel data of a region composed of the first plurality of pixels in the horizontal direction and the second plurality of pixels in the vertical direction of the screen represented by the input image data are plural. The connection switching is performed so that the same image processor among the other image processors is sequentially input.

Thus, according to the present invention, any one image processor can input pixel data in the same area and in a number equal to the sum of the first plurality of pixels and the second plurality of pixels. Pixel data in different areas can be input between different image processors.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of an image processing apparatus according to the present invention. This image processing device is a connection to which n (n is an integer of 2 or more, for example, 16) frame memory blocks 1 ₁ to 1 _n and output image data of these frame memory blocks 1 ₁ to 1 _n are input. Switch 2
, The image processors 3 _{1 to} 3 _{n to} which the output image data of the connection switching device 2 is input, and the frame memory blocks 1 ₁ to 1 _n.
And a timing generator 5 for controlling the switching of the connection switching device 2.

Frame memory block 1₁~ 1_nFigure 2
One frame memory for each pixel as shown in
It is divided into 16 (= n), and the total capacity is 1
It is for a frame. Connection switch 2 is timing generator 5
Frame memory block 1 based on the output switching signal of₁
~ 1 _nEach output pixel data of is sequentially switched in a predetermined order
Output and image processor 3₁~ 3_nTo supply.

Next, the operation of this embodiment will be described. As shown in FIG. 2, the input image data corresponds to each frame memory block 1 ₁ to 1 _n according to the write address generated by the write address generator 4, as shown in FIG.
Are sequentially written to. In FIG. 2, P1 to P16 indicate the positions on the screen of the respective pixel data written in the frame memory blocks 1 ₁ to 1 _n , and 16 pixel data in the region of 4 horizontal pixels and 4 vertical pixels in FIG. Are stored separately in each of the frame memory blocks 1 ₁ to 1 _n (that is, n = 16 in this example). In this way, the input image data is sequentially written into the frame memory blocks 1 ₁ to 1 _n for one screen (for one frame) in units of pixels.

Then, based on the output switching signal of the timing generator 5, the connection switching device 2 firstly selects the k-th (k = 1, 1) frame frame block 1 ₁ to 1 _n .
2,. . . , N), the output pixel data of the frame memory block 1 _k is connected so as to be input to the k-th image processor 3 _k of the image processors 3 _{1 to} 3 _n .

As a result, 16-pixel data is input in parallel to the image processors 3 _{1 to} 3 _n . However, the pixel data input to the image processors 3 _{1 to} 3 _n is the _first pixel data shown by P1 in FIG. 2 in the area of the horizontal 4 pixels and the vertical 4 pixels which are different from each other.

Next, the connection switching device 2 outputs the pixel data of the k-th frame memory block 1 _k of the frame memory blocks ₁ 1 to 1 _n is the image processor 3 ₁ to 3 k-1 th among _n It is connected so as to be input to the image processor 3 _k−1 (however, when k = 1, the nth image processor 3 _n ). As a result, 16-pixel data is input to the image processors 3 _{1 to} 3 ₁₆ in parallel.

In this case, the pixel data input to the image processors 3 _{1 to} 3 _n are the horizontal 4 different from each other.
Pixel data is pixel data in an area of 4 vertical pixels, and in the same 16-pixel area as the previous time in the same image processor,
This is the second pixel data shown by P2 in FIG.

At the next timing, in the connection switcher 2, the output pixel data of the k-th frame memory block 1 _k of the frame memory blocks 1 ₁ to 1 _n is converted to _k- of the image processors 3 _{1 to} 3 _n . Second image processor 3
Switch and connect as input to _k-2 . However, the output pixel data of the frame memory blocks 1 _1, 1 ₂ are input to the image processor 3 _n-1, 3 _n.

As a result, 16-pixel data is input in parallel to the image processors 3 _{1 to} 3 _n . In this case, the pixel data input to the image processors 3 _{1 to} 3 _n are the pixel data in the areas of the horizontal 4 pixels and the vertical 4 pixels which are different from each other, and the same pixel data of the same 16 pixels as the previous time are used. This is the third pixel data shown by P3 in FIG. 2 in the area.

Thereafter, the connection switching device 2 performs the switching operation in the same manner as described above, and by the 16 times of the connection switching operation, each of the image processors 3 _{1 to} 3 _n receives the pixel data from the memory block shown in the order of Table 1. Is entered. However, Table 1
Among them, MBk is output pixel data of the k-th frame memory block 1 _k , and n = 16.

[0024]

[Table 1] As a result, all 16-pixel data in a total of 16 different areas of 4 horizontal pixels and 4 vertical pixels are input to each of the image processors 3 _{1 to} 3 _n (= 3 ₁₆ ). That is, for example, the image processor 3 ₁ is supplied with pixel data of an area consisting of horizontal 4 pixels and vertical 4 pixels P1 to P16 shown in the upper left of FIG.

In this way, in this embodiment, pixel data is input to each of the image processors 3 _{1 to} 3 _n without collision of read accesses to the frame memories of the image processors and without waiting for access. Each image processor can perform interpolation processing in the range of horizontal and vertical 4 pixels in the vicinity of the pixel of interest, that is, 16-point interpolation processing.

In the above embodiment, n = 16 is used to perform 16-point interpolation, but the present invention is not limited to this.

[0027]

As described above, according to the present invention,
Pixel data output from a plurality of memory blocks is separately input to each of the plurality of image processors by the connection switching means, so that the pixel data can be read and accessed without being accessed by the plurality of image processors. There is no waiting.

Further, according to the present invention, by setting the total capacity of the plurality of memory blocks to one frame, one screen of image data can be stored in the plurality of memory blocks.
The capacity is not wasted, and the cost can be significantly reduced as compared with the conventional apparatus in which a dedicated frame memory is provided for each image processor.

Further, according to the present invention, a plurality of pixel data in the same area is input to any one image processor,
Further, since pixel data of different areas are input between different image processors, the pixel data of the above areas can be interpolated to the respective image processors.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the main part of FIG.

FIG. 3 is a block diagram of an example of the related art.

FIG. 4 is a block diagram of another example of the related art.

[Explanation of symbols]

1 ₁ to 1 _n frame memory block 2 connection switching device 3 _{1 to} 3 _n image processor 4 write address generator 5 timing generator

Claims (3)

[Claims] 1. A plurality of memory blocks each of which has a value obtained by dividing a predetermined total capacity into a plurality of values, a writing unit for writing input image data to each of the plurality of memory blocks in pixel units, and the plurality of memory blocks. A plurality of image processors are provided corresponding to the memory blocks to perform image processing, and pixel data respectively output from the plurality of memory blocks are separately input to the plurality of image processors, and the plurality of memory blocks and the plurality of memory blocks are provided. And a connection switching unit that sequentially switches connections between the image processors. 2. The predetermined total capacity is one frame,
The writing means separately outputs each pixel data of an area, which is represented by the input image data, of the first plurality of pixels in the horizontal direction and the second plurality of pixels in the vertical direction of the screen to each of the plurality of memory blocks. The image processing apparatus according to claim 1, wherein writing is performed. 3. The connection switching means is configured such that all pixel data of an area consisting of a first plurality of pixels in the horizontal direction and a second plurality of pixels in the vertical direction of the screen represented by the input image data are the plurality of pixel data. 3. The image processing apparatus according to claim 2, wherein connection switching is performed so that the same image processor among the image processors is sequentially input.