JPH09247575A - Scanning line converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of a vertical resolution by adding offsets to the coefficient of interpolation in an odd-numbered field and an even- numbered field in scanning line conversion. SOLUTION: This converter is provided with a timing generation circuit 7 for discriminating the odd-numbeved/even-numbered fields and interlace/non- interlace of input signals and generating an interpolation coefficient for performing vertical interpolation in the scanning line conversion and a synchronizing signal generation circuit 6 for generating the respective kinds of pulses for driving a liquid crystal panel. The timing generation circuit provides the interpolation coefficient with the offset for each field by performing reset for each frame and prevents the degradation of the vertical resolution. The synchronizing signal generation circuit 6 generates stable synchronizing signals even for non-standard signals by performing reset for each field.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning line conversion device in electronic equipment centering on a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, a scanning line conversion device has been used to display an image on a display element such as a liquid crystal panel having a pixel number different from that of an input signal. An example of the operation for performing the scan line conversion is an example of the digital video processing operation shown in "Application of Digital Signal Processing", page 271, edited by the Institute of Electronics and Communication Engineers. Hereinafter, a conventional scanning line conversion device will be described with reference to the drawings.

FIG. 10 is a system diagram of a conventional scanning line conversion apparatus in the case of reduction, and FIG. 11 is a diagram showing an interpolation reduction operation.

In FIG. 10, 20 is a reference counter, 2
1 is a comparator, 22 is a register, 23 is an adder, 24 is an interpolation circuit, 25 is a memory, and 26 is an address generation circuit. Further, FIG. 8 shows the operating principle when the reduction ratio is 0.6. In FIG. 8, short vertical lines of the input signal represent sample values of the original image signal, and black dots are values that need to be newly created by interpolation. First, the reciprocal of the reduction ratio SH = (standard screen size) / (size to be reduced) is input. This SH is composed of a register and an adder Σ
Added to SH circuit. The ΣSH circuit integrates in SH steps each time a coincidence pulse appears in the output of the comparator.

Now, the integer part of the integrated output ΣSH is compared with the output of the reference counter, and when the values are equal, the comparator generates a coincidence pulse. This coincidence pulse indicates the position of the sample point to be interpolated. Meanwhile, Σ
The fractional part of SH is used as a coefficient for interpolation at that time. The sample value obtained as a result of the interpolation is written in a predetermined position on the main memory in accordance with the write address created by the counter from the coincidence pulse.

As described above, a new image data is interpolated and written in the memory each time a coincidence pulse is generated, so that a reduced image can be formed on the memory. If the A conversion is performed, a reduced analog image signal can be obtained. In the above example, the example of horizontal reduction has been described, but the same applies to the case of vertical reduction, in which the clock is a pulse synchronized with the horizontal synchronizing signal.

In order to convert the number of samples in this way, it is necessary to calculate sample points and interpolation coefficients for interpolation based on a reference clock (or horizontal synchronizing pulse) and shape a data string by a memory. .

For a television signal such as NTSC, the number of scanning lines is doubled to VGA (pixel number 640 ×
480) Generally, the structure is such that it is displayed on a panel. At this time, in order to double the number of scanning lines, a structure in which an input signal is written in the FIFO and one line is read twice at a speed twice that of writing to double the number of scanning lines is usually used. However, with this configuration, the field memory is not required and only the FIFO (line memory) is required because of the simple configuration, but since the interlacing does not occur, the vertical resolution deteriorates. In order to secure vertical resolution, a field memory such as motion adaptive scanning line interpolation that interpolates a signal between fields is required.

[0009]

As described above, NTS
In the case of supporting an interlaced signal such as C, it is necessary to use a field memory in order to perform scanning line conversion while ensuring vertical resolution.

In view of the above-mentioned problems, the present invention provides a scanning line conversion device in which vertical resolution does not deteriorate regardless of a small circuit scale.

[0011]

In order to solve the above-mentioned problems, the scanning line conversion apparatus of the present invention discriminates the field polarity of an input signal and a sync separation circuit for detecting a horizontal sync signal and a vertical sync signal of an input signal. Field discriminating circuit,
A scanning line number conversion circuit that converts the number of horizontal scanning lines of the input signal, a first delay device that delays the output of the scanning line conversion circuit for one horizontal period, and an output of the first delay device that is 1 A second delay device for delaying a horizontal period, a sync signal generating circuit for creating a horizontal sync signal and a vertical sync signal after scanning line conversion from the output of the sync signal separation circuit, and an input signal of an interlaced or non-interlaced signal format. An interlace discriminating circuit for discriminating whether to generate a pulse and a vertical interpolation coefficient for use in scanning line conversion in cooperation with the timing generating circuit and the interlace discriminating circuit, and the output of the timing generating circuit. Interpolating circuit for interpolating signals from the outputs of the first and second delay devices, and the synchronizing signal generating circuit and the timer depending on the format of the input signal. A control circuit for controlling the reset signal of the timing generating circuit and a function capable of forcibly initializing various output pulses of the synchronizing signal generating circuit and the timing generating circuit in synchronization with the vertical synchronizing signal of the input signal It is characterized by.

[0012]

A scanning line conversion apparatus according to claim 1 of the present invention determines the polarities of an interlaced / non-interlaced signal and an odd / even field as an input signal, and when the input signal is an interlaced signal, an odd field By differentiating the interpolation processing in the even field, the scanning line conversion can be performed without deteriorating the vertical resolution.

In the scanning line converting apparatus according to the second aspect of the present invention, the interpolation timing generating circuit for performing the vertical interpolation when the input signal is the non-interlaced signal is reset every frame to drive the liquid crystal panel. The reset of the sync signal generator that generates the various pulses required to achieve this is performed for each field so that stable synchronization can be obtained even with non-standard signals, and scan line conversion is performed without degrading vertical resolution. It has the effect that

According to a third aspect of the present invention, there is provided a scanning line conversion apparatus which comprises a sync separation circuit for detecting a horizontal sync signal and a vertical sync signal of an input signal, a field discrimination circuit for discriminating a field polarity of the input signal, and an input. A scanning line number conversion circuit for converting the number of scanning lines of a signal horizontal scanning line, a first delay device for delaying the output of the scanning line conversion circuit for one horizontal period, and an output of the first delay device for one horizontal period. A second delay device for delaying a period, a sync signal generation circuit for generating a horizontal sync signal and a vertical sync signal after scanning line conversion from the output of the sync signal separation circuit, and scanning line conversion in cooperation with the timing generation circuit. Timing generating circuit for generating a pulse and a vertical interpolation coefficient for use in, and an interpolation circuit for interpolating a signal from the outputs of the first and second delay devices according to the output of the timing generating circuit. And characterized by including, it has the effect of preventing deterioration of the vertical resolution by varying the vertical interpolation coefficient for interpolating signals at the even and odd fields.

According to a fourth aspect of the present invention, there is provided a scanning line conversion apparatus which comprises a sync separation circuit for detecting a horizontal sync signal and a vertical sync signal of an input signal, a field discrimination circuit for discriminating a field of the input signal, and an input signal. Scanning line number conversion circuit for converting the number of scanning lines of the horizontal scanning line, a first delay device for delaying the output of the scanning line conversion circuit for one horizontal period, and an output of the first delay device for one horizontal period. A second delay device for delaying, a synchronizing signal generating circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal after scanning line conversion from the output of the synchronizing signal separation circuit, and scanning line conversion in cooperation with the timing generating circuit. A timing generation circuit for generating a pulse and a vertical interpolation coefficient for use, and an interpolation circuit for interpolating a signal from the outputs of the first and second delay devices according to the output of the timing generation circuit, It is characterized by comprising a control circuit for controlling the reset signal of the synchronizing signal generating circuit and the timing generating circuit according to the format of the force signal, and a vertical interpolation coefficient for interpolating the signal in the even field and the odd field. While preventing deterioration of vertical resolution by changing
By resetting the synchronization signal generation circuit for each field and resetting the timing generation circuit for each frame, it is possible to supply a stable output even when the synchronization of the input signal is disturbed.

According to a fifth aspect of the present invention, there is provided a scanning line conversion apparatus which comprises a sync separation circuit for detecting a horizontal synchronizing signal and a vertical synchronizing signal of an input signal, a field discriminating circuit for discriminating a field of the input signal, and an input signal. Scanning line number conversion circuit for converting the number of scanning lines of the horizontal scanning line, a first delay device for delaying the output of the scanning line conversion circuit for one horizontal period, and an output of the first delay device for one horizontal period. A second delay device for delaying, a sync signal generating circuit for producing a horizontal sync signal and a vertical sync signal after scanning line conversion from the output of the sync signal separation circuit, and whether the signal format of the input signal is interlaced or non-interlaced An interlace discriminating circuit for discriminating and a pulse and a vertical interpolation coefficient for use in scanning line conversion are generated in cooperation with the timing generating circuit and the interlace discriminating circuit. Timing generating circuit, an interpolation circuit for interpolating signals from the outputs of the first and second delay devices according to the output of the timing generating circuit, the synchronizing signal generating circuit and timing according to the format of the input signal It is characterized by having a control circuit that controls the reset signal of the generation circuit.When the input signal is interlaced, the vertical resolution coefficient is changed by changing the vertical interpolation coefficient for interpolating the signal in the even field and the odd field. While preventing deterioration, reset the synchronization signal generation circuit for each field, reset the timing generation circuit for each frame, and in the case of non-interlace, reset the synchronization signal generation circuit and the timing generation circuit for each field. By doing so, there is an effect that a stable output can be supplied even when the synchronization of the input signal is disturbed.

According to a sixth aspect of the present invention, there is provided a scanning line conversion apparatus which comprises a sync separation circuit for detecting a horizontal sync signal and a vertical sync signal of an input signal, a field discrimination circuit for discriminating a field of the input signal, and an input signal. Scanning line number conversion circuit for converting the number of scanning lines of the horizontal scanning line, a first delay device for delaying the output of the scanning line conversion circuit for one horizontal period, and an output of the first delay device for one horizontal period. A second delay device for delaying, a sync signal generating circuit for producing a horizontal sync signal and a vertical sync signal after scanning line conversion from the output of the sync signal separation circuit, and whether the signal format of the input signal is interlaced or non-interlaced An interlace discriminating circuit for discriminating and a pulse and a vertical interpolation coefficient for use in scanning line conversion are generated in cooperation with the timing generating circuit and the interlace discriminating circuit. Timing generating circuit, an interpolation circuit for interpolating signals from the outputs of the first and second delay devices according to the output of the timing generating circuit, the synchronizing signal generating circuit and timing according to the format of the input signal It has a control circuit that controls the reset signal of the generation circuit and a function that can forcibly initialize various output pulses of the synchronization signal generation circuit and the timing generation circuit in synchronization with the vertical synchronization signal of the input signal. The feature is that by changing the vertical interpolation coefficient for interpolating the signal in the even field and the odd field, it is possible to prevent deterioration of the vertical resolution and to supply a stable output even to a non-standard signal. .

(Embodiment 1) An embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4.

In FIG. 1, 1 is a sync separation circuit, 2 is a field discrimination circuit, 3 is a scanning line number conversion circuit, 4 is a first delay device for delaying the output of the scanning line number conversion circuit 3 for one horizontal period, 5 Is a second delay device that delays the output of the delay device 4 for one horizontal period, 6 is a synchronizing signal generation circuit, 7 is a timing generation circuit, and 8 is an interpolation circuit. FIG. 2 is an operation principle diagram showing the operation of vertical interpolation, and FIG. 3 is a diagram showing the state of vertical interpolation in an interlaced signal. FIG. 4 is a diagram showing an internal configuration of the timing generating circuit, FIG. 4 is a diagram showing an internal configuration of the timing generating circuit 7, and 27 is a selector.

The input video signal is input to the sync separation circuit 1, and the horizontal sync signal (Hsync) and the vertical sync signal (Vsync) are separated and output. Based on the separated sync signal, the field discrimination circuit 2 determines whether the current field is an even field or an odd field, for example, Hsy.
It is determined and output by observing the phase relationship between nc and Vsync.

Further, in the synchronizing signal generating circuit 6, the input signal H
Based on sync and Vsync, a sync signal after the conversion of the number of scanning lines necessary for driving the liquid crystal panel module, for example, a pulse such as a horizontal sync signal (HS), a vertical sync signal (VS), an enable signal (EN), etc. create. As the internal configuration of the synchronization signal generation circuit 6, for example, a dot clock is reproduced by a PLL based on Hsync, and the clock is frequency-divided by a counter to create HS, VS and the like.

The scanning line number conversion circuit 3 converts the horizontal frequency of the input video signal and outputs it. In the scanning line number conversion circuit 3, for example, the number of samples in the horizontal period is converted as in the case of the reduction described in the conventional example. The signal whose number of scanning lines has been converted is input to the delay unit 4 and the delay unit 5 and output as shown in FIG. The signal output from the delay unit 4 and the signal output from the delay unit 5 are input to the interpolation circuit 8, and the interpolation circuit 8 interpolates the signal in the vertical direction and outputs the signal. In the example of FIG. 2, when the number of scanning lines is doubled, the outputs of the delay units 4 and 5 are interpolated according to the coefficient calculated by the timing generation circuit 7.

By the way, when the input signal is an interlaced signal such as NTSC, as shown in FIG. 3A, when the original signal is a progressive signal, the sending side has an odd field (o) and an even field (e). ) And send. Here, white circles represent signals with high brightness, and black circles represent signals with low brightness. Most of the interlaced signals transmitted in this way are interpolated and displayed for each even field or odd field on the image receiving side. A conventional example is shown in FIG. The scanning lines (indicated by double circles) interpolated for each even-numbered field and odd-numbered field are interpolated by using the FIFO for the converted signal (non-interlace) without using the field memory to perform scanning-line conversion. It is an example. A line is interpolated between the 1st line and the 2nd line of the odd field (o). Since the number of scanning lines is doubled, the interpolation coefficient becomes 0.5, and the average of the first line and the second line becomes the signal value of the interpolation line. In this example, the brightness of one line is low and the brightness of two lines is high, so that the interpolation line has an intermediate brightness. Similarly, the even line (e) is also interpolated and the number of scanning lines is doubled.

In general, the reference counter 20 can be set to an arbitrary division ratio so that PAL can be used in addition to NTSC.
Vsyn to support various signals such as
It is necessary to reset with c. At this time, since the interpolation timing and the coefficient are created with reference to the vertical synchronizing signal Vsync for both the odd field and the even field, a shift occurs for each field. Therefore, when the signal obtained by combining the odd field and the even field is viewed on the liquid crystal panel, it becomes a value obtained by integrating each field from the response characteristics of the viewer's eyes. This is represented by f of the converted signal (non-interlaced conversion) in FIG. 3C, whereas the original signal changes at a frequency of signal 1 having low luminance and signal 2 having high luminance. Low brightness after conversion (intermediate brightness)
3, there are changes in the low frequency and the high brightness part 3. When the signal from the sending side is non-interlaced, it is good, but in the case of interlaced, the vertical resolution is degraded as shown in FIG.

In the scanning line conversion apparatus of the present invention, an offset of 0.5 is added only to the interpolation coefficient of the even field. The odd fields are 0, 0.5, 0, 0.5. . . .
And the interpolation coefficient is created by the reference counter, while the even fields are 0.5, 0, 0.5. . . . . And
In that case, interpolation is performed as indicated by e after conversion (interlace conversion). Therefore, the signal seen on an actual liquid crystal panel is f, and a change in frequency similar to that of the original signal 1 of low luminance (intermediate luminance) signal 1 with respect to high luminance (intermediate luminance) signal 2 is obtained.

The level of the luminance of the signal in FIG. 3 is represented by the color density of circles in the figure (white circles have high luminance, and black circles have low luminance).

As shown in the internal configuration diagram of the timing generation circuit shown in FIG. 4, the selector 27 selects the offset of the adder 23 of the ΣSH circuit based on the result of the field discrimination. In the odd field, the selector 27 selects 0, and in the even field, the selector 27 selects the offset value. The offset value is a number obtained by multiplying SH indicating the reciprocal of the reduction rate by 0.5.

With the above configuration, the interpolation coefficients of the even field and the odd field are offset, and the interpolated signal as if interlaced can be obtained.

According to this structure, it is possible to prevent deterioration of the vertical resolution by changing the vertical interpolation coefficient for interpolating the signal in the even field and the odd field.

(Second Embodiment) Next, another embodiment of the present invention will be described with reference to FIGS.

The same components as those in the above-mentioned embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 5, reference numeral 9 denotes Vsy which is synchronously separated.
This is a control circuit for controlling the synchronization signal generation circuit 6 and the timing signal generation circuit 7 based on nc. FIG. 6 shows an example of the internal configuration of the control circuit, and 28 in FIG. 6 is an AND circuit. In the first embodiment, resetting is performed by Vsync for every odd field and even field.
Although the interpolation coefficient has an offset of 0.5, in the second embodiment, the timing generation circuit 7 is reset not for each field but for each frame. Since the reset is applied for each frame, the interpolation coefficient is also completed in one frame, and the same interpolation as that for applying the offset to the interpolation coefficient is applied for each field. At this time, the synchronization signal generating circuit 6 performs the same for each field as in the first embodiment.

According to this configuration, even if the input synchronization is not normal such as when a non-standard signal is input, various pulses for driving the liquid crystal panel are synchronized with the input signal, and a stable image can be obtained. As in the first embodiment, deterioration of vertical resolution can be prevented.

(Third Embodiment) Next, another embodiment of the present invention will be described with reference to FIGS.

The same components as those in the above-mentioned embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 7, 10 is an interlace discriminating circuit for discriminating whether the input signal is interlaced or non-interlaced. FIG. 8 shows the internal configuration of the control circuit of this embodiment. In FIG. 8, 29 is a selector. In the interlace discrimination circuit, for example, in the case of interlace, the result of the field discrimination is that the odd field and the even field are alternately discriminated, but in the case of non-interlace, it is always discriminated as the odd field.
Interlaced / non-interlaced can be discriminated by monitoring the result of the field discrimination circuit over a plurality of fields.

When the input signal is interlaced, the selector 29 selects the output of the AND circuit 28 so that the timing generation circuit is reset every frame as in the second embodiment. When the input signal is a non-interlaced signal such as a game machine, the selector 29 selects the input Vsync for resetting every field. With this configuration, optimum vertical interpolation can be performed according to the input signal.

(Fourth Embodiment) Next, another embodiment of the present invention will be described with reference to the internal configuration diagram of the synchronizing signal generating circuit of FIG.

In FIG. 9, 11 is a counter, 12 is a first comparator, 13 is a second comparator, 14 is an inverter, 15 is a first AND circuit, 16 is a second AND circuit, and 17 is a second comparator. 1 OR circuit, 18 is a second OR circuit, 1
9 is RS-FF.

The synchronizing signal generating circuit of FIG. 9 describes an example of generating VS. The input HS signal is counted by the counter 11 for the number of HS. The counted value (10 bits) is compared with the start line value and end line value set by the comparators 12 and 13, and a coincidence pulse is output. The coincidence pulse generates a VS signal by RS-FF (reset / set flip-flop).

For example, in the case of the start line 10 and the end line 30, lines 10 to 30 output "H" level pulses. At this time, the OR circuits 17 and 18 forcibly set or reset VS during the input Vsync period (in this case, positive polarity).
The inverter 14 and the AND circuits 15 and 16 select set / reset. That is, it is set when S / R is at "H" level. For example, when the input signal is a non-standard signal of NTSC and the number of lines is only 260 lines / field, the scanning line is doubled to be 520 lines. When the VS given to the liquid crystal panel is a standard signal and the HS is set to have a width of 30 lines from 495 lines to 525 lines, the counter 1 is provided if the OR circuits 17 and 18 forming the forced set / reset circuit are not provided.
The count value of 1 is only 1 to 520, and cannot take the value of 525 which is the end line. Therefore, VS is always in the set state. Therefore, if a nonstandard signal is forcibly reset in the above example according to the input Vsync, VS can generate a pulse width of 495 to 520 lines. In the above example, the case of VS is described, but the same can be said for all other pulses.

According to this structure, various stable pulses can be generated even when the input signal is a non-standard signal,
Optimal vertical interpolation is possible.

[0043]

As described above, according to the scanning line conversion apparatus of the present invention, the sync separation circuit for detecting the horizontal synchronizing signal and the vertical synchronizing signal of the input signal and the field discriminating circuit for discriminating the field of the input signal. A scanning line number conversion circuit for converting the number of scanning lines of horizontal scanning lines of the input signal, and a first delay device for delaying the output of the scanning line conversion circuit by one horizontal period,
A second delay device for delaying the output of the first delay device by one horizontal period; and a sync signal generation circuit for creating a horizontal sync signal and a vertical sync signal after scanning line conversion from the output of the sync signal separation circuit, An interlace discriminating circuit for discriminating whether the signal format of the input signal is interlace or non-interlace, and a timing generating circuit for interlocking with the timing generating circuit and the interlace discriminating circuit to generate a pulse and a vertical interpolation coefficient for use in scanning line conversion. When,
According to the output of the timing generation circuit, the first and second
An interpolation circuit for interpolating a signal from the output of the delay device, a control circuit for controlling the reset signal of the synchronizing signal generating circuit and the timing generating circuit according to the format of the input signal, and a synchronizing circuit for synchronizing the vertical synchronizing signal of the input signal. Thus, it is possible to provide a scanning line conversion device that can forcibly initialize various output pulses of the synchronization signal generation circuit and the timing generation circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a scanning line conversion device according to a first embodiment of the present invention.

FIG. 2 is an operation principle diagram showing an operation of the scanning line conversion apparatus.

FIG. 3 is a diagram for explaining vertical interpolation of the scanning line conversion apparatus.

FIG. 4 is a diagram showing an example of a timing generation circuit of the scanning line conversion apparatus.

FIG. 5 is a circuit diagram of a scanning line conversion device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of control means of the scanning line conversion apparatus.

FIG. 7 is a circuit diagram of a scanning line conversion device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of control means of the scanning line conversion apparatus.

FIG. 9 is a diagram showing an example of a synchronization signal generator of a scanning line conversion device of the present invention.

FIG. 10 is a diagram showing a conventional scanning line conversion device.

FIG. 11 is an interpolation reduction operation diagram in the conventional scanning line conversion apparatus.

[Explanation of symbols]

 1 Sync Separation Circuit 2 Field Discrimination Circuit 3 Scanning Line Number Conversion Circuit 4 Delay Device 1 5 Delay Device 2 6 Synchronization Signal Generation Circuit 7 Timing Generation Circuit 8 Interpolation Circuit 9 Control Circuit 10 Interlace Discrimination Circuit 11 Counter 12 Comparator 1 13 Comparator 2 14 Inverter 15 AND circuit 1 16 AND circuit 2 17 OR circuit 1 18 OR circuit 2 19 SR-FF

Front page continuation (72) Inventor Kaho Shindo 1-1, Matsushita-machi, Ibaraki-shi, Osaka Matsushita AV Technology Co., Ltd.

Claims (6)

[Claims] 1. A scanning line conversion apparatus for performing polarity discrimination between an interlaced / non-interlaced signal and an odd / even field of an input signal, and performing different interpolation processing for an odd field and an even field in the case of an interlaced signal. 2. A synchronization signal generating circuit for resetting an interpolation timing generating circuit for performing vertical interpolation when an input signal is a non-interlaced signal, for each frame, and for generating various pulses necessary for driving the display means. A scanning line conversion device characterized in that the circuit is reset every field. 3. A sync separation circuit for detecting a horizontal sync signal and a vertical sync signal of an input signal, a field discrimination circuit for discriminating a field polarity of the input signal, and a scan for converting the number of horizontal scanning lines of the input signal. A line number conversion circuit; a first delay device that delays the output of the scanning line conversion circuit for one horizontal period; a second delay device that delays the output of the first delay device for one horizontal period; and the timing generation. A signal is generated from the output of the first and second delay devices according to the output of the timing generation circuit and the timing generation circuit that generates a pulse and a vertical interpolation coefficient for use in scanning line conversion in cooperation with the circuit. A scanning line conversion device having an interpolating circuit to be inserted. 4. A sync separation circuit for detecting a horizontal synchronizing signal and a vertical synchronizing signal of an input signal, a field discriminating circuit for discriminating a field of the input signal, and a scanning line for converting the number of horizontal scanning lines of the input signal. Number conversion circuit, a first delay device that delays the output of the scanning line conversion circuit for one horizontal period, a second delay device that delays the output of the first delay device for one horizontal period, and the synchronization signal separation A synchronizing signal generating circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal after scanning line conversion from the output of the circuit, and a timing for generating a pulse and a vertical interpolation coefficient used for scanning line conversion in cooperation with the timing generating circuit. A generation circuit, an interpolation circuit for interpolating a signal from the outputs of the first and second delay devices according to the output of the timing generation circuit, and the synchronization signal generation circuit according to the format of the input signal. And a scanning line conversion device including a control circuit for controlling a reset signal of a timing generation circuit. 5. A sync separation circuit for detecting a horizontal sync signal and a vertical sync signal of an input signal, a field discrimination circuit for discriminating a field of the input signal, and a scanning line for converting the number of scanning lines of horizontal scanning lines of the input signal. Number conversion circuit, a first delay device that delays the output of the scanning line conversion circuit for one horizontal period, a second delay device that delays the output of the first delay device for one horizontal period, and the synchronization signal separation A synchronizing signal generating circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal after scanning line conversion from the output of the circuit, an interlace judging circuit for judging whether the signal format of the input signal is interlaced or non-interlaced, the timing generating circuit and interlace A timing generation circuit for generating a pulse and a vertical interpolation coefficient for use in scanning line conversion in cooperation with the discrimination circuit; According to the output of the generating circuit, the first,
A scanning line conversion device comprising: an interpolation circuit for interpolating a signal from the output of the second delay device; and a control circuit for controlling a reset signal of the synchronization signal generation circuit and the timing generation circuit according to the format of the input signal. 6. A sync separating circuit for detecting a horizontal synchronizing signal and a vertical synchronizing signal of an input signal, a field discriminating circuit for discriminating a field of the input signal, and a scanning line for converting the number of scanning lines of horizontal scanning lines of the input signal. Number conversion circuit, a first delay device that delays the output of the scanning line conversion circuit for one horizontal period, a second delay device that delays the output of the first delay device for one horizontal period, and the synchronization signal separation A synchronizing signal generating circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal after scanning line conversion from the output of the circuit, an interlace judging circuit for judging whether the signal format of the input signal is interlaced or non-interlaced, the timing generating circuit and interlace A timing generation circuit for generating a pulse and a vertical interpolation coefficient for use in scanning line conversion in cooperation with the discrimination circuit; According to the output of the generating circuit, the first,
An interpolation circuit for interpolating a signal from the output of the second delay device, and a control circuit for controlling the reset signals of the synchronization signal generation circuit and the timing generation circuit according to the format of the input signal,
A scanning line conversion device having a function of forcibly initializing various output pulses of a synchronizing signal generating circuit and a timing generating circuit in synchronization with a vertical synchronizing signal of an input signal.