JPH09246986A - Encoded signal decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To update the write address of a memory for storing inputted encoded signals corresponding to synchronizing signals in the encoded signals. SOLUTION: The inputted encoded signals (SRD) are stored in the memory 11 by the write address of d first address generation means 12. The data of the memory 11 are read by the read address of a second address generation means 13 and supplied to a decoding means 14. When a synchronization detection means 10 detects the synchronizing signal, the first address generation means 12 address-shifts the data of the memory 11 and performs address conversion so as to bring the synchronizing signal to a head position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coded signal decoding apparatus for decoding coded signals of voice and image information.

[0002]

2. Description of the Related Art In recent years, a transmission device capable of more efficiently transmitting information by encoding information such as voice and images and a recording / reproducing device capable of more efficiently recording / reproducing the above information have been developed. There is. For example, International Standards Organization (Internatio
nal Standard Organization (hereinafter referred to as ISO), a CD-ROM disc defined by a standard ISO 9660 is a video CD player that is an MPEG of ISO.
(Moving Pictures Experts Group) A moving picture and a sound are recorded and reproduced by an encoding method standardized by the standard ISO / IEC11172.

A moving picture or audio signal coded according to the MPEG standard is formed by a coded signal in frame units including a sync signal, coded information and coded data as shown in FIG. In FIG. 5, the synchronization signal is a bit string that represents the beginning of the unit frame and is used to extract the unit frame when decoding the encoded signal. What is encoded information?
It includes ancillary information related to the encoding process necessary for decoding such as the bit rate and sampling frequency of the encoded data included in the frame.

In such a coded signal decoding apparatus, an input coded signal in units of frames is subjected to error detection / correction processing, separation processing of a video signal and an audio signal, etc. in advance, and therefore is decoded. Data is not input to the processing unit at a constant rate, but is often input in bursts.
For this reason, a memory buffer is provided at the input stage of the code processing unit, and the input coded signal is temporarily stored in this memory buffer and then input to the decoding processing unit at a predetermined transfer rate to output the desired audio signal. And a video signal.

In order to realize such a function, the conventional coded signal decoding device has a structure as shown in FIG. Here, the configuration and operation of the conventional coded signal decoding device will be described more specifically with reference to FIGS. 3 and 4.

In the conventional coded signal decoding apparatus shown in FIG. 3, the memory 11 is a memory for storing the input coded signal of at least one frame. The first address generating means 22 is means for generating a write address of the memory 11. The second address generation means 23 is means for generating a read address of the memory 11.

The synchronization detecting means 20 is means for detecting the synchronization signal in the encoded signal read from the memory 11. The decoding means 24 is means for extracting and decoding the coding information and the coded data from the coded signal according to the output of the synchronization detecting means 20.

FIG. 4 shows an address change (line A, C) when writing to the memory 11 and an address change (line B, line) when reading.
It is an explanatory view showing D). In FIG. 3, the encoded signal S
When RD is input, the signal is stored in the memory 11. The storage address at that time is the first address generation means 2
Generated by 2. Here, the first address generating means 22 stores the coded signals in order from the head address A ₀ of the memory 11 and stores up to the maximum capacity of the address A _n , as indicated by the line A in FIG. After that, as shown by the portion of the straight line C, the signal is stored again from the head address and the write address is generated so that the memory 11 becomes the ring buffer.

The encoded signal SRD is input when the request signal RQD generated by the decoding means 24 is active (RQD = Hi), and the request signal RQ is input when the memory 11 is full.
D becomes inactive (RQD = Lo).

The coded signal stored in the memory 11 as described above is sequentially read according to the read address generated by the second address generating means 23. The sync signal in the read coded signal is detected by the sync detecting means 20.

The decoding means 24 extracts the coded information and the coded data from the coded signal read according to the sync signal of the sync detection means 20, decodes the coded data based on the coded information, and outputs the decoded coded data. Generate the signal DAD. Also decryption means 2
4 controls the second address generating means so that the read address generated by the second address generating means 23 interlocks with the write address generated by the first address generating means 22. Then, each time the decoding of the coded signal of the data of the predetermined frame stored in the memory 11 is completed, the request signal RQD
Is output. Thus, the memory 11 is requested to replenish the encoded signal again. Since the amount of encoded data changes for each frame, the read processing time may be shortened as indicated by the broken line D in FIG.

[0012] Here, the encoded signal input to the encoded signal decoding device may have data interruption in the middle of a frame when the reproducing device is in a poor reproduction state or when fast-forward reproduction is performed. In addition, the interval between frames may be outside the predetermined range. To cope with such a situation, in the conventional coded signal decoding device, the sync detection means 20 manages the detection cycle of the sync signal in the coded signal read from the memory 11. If the synchronization state is abnormal, instead of reading the coded signal having the abnormal sync signal to the second address generation means 23, the coded signal having the immediately preceding valid sync signal is read. I was controlling to put it out.

As described above, the conventional coded signal decoding apparatus sequentially stores the input coded signal in the ring buffer included in the memory 11, decodes the coded data while reading the coded signal, and controls the read address. Was going on.

[0014]

However, in the conventional configuration, since the memory 11 is used to form the ring buffer, the first address generating means 22 generates the cyclic address, and further the second address generating means 23. Is designed to generate a read address linked to the cyclic address. In such a configuration, the input to the memory 11 is generally a burst input, while the output must be at a constant rate. For this reason, there are problems that it is difficult to determine the relationship between the input address and the output address at the system design stage, and control of address generation becomes complicated.

Further, when the reproduction state of the reproducing apparatus is abnormal, interpolation reproduction is performed by substituting the immediately preceding effective coded signal. For this reason, the memory 11 stores the effective coded signal and the latest coded signal. However, there is a problem that it must have a capacity capable of storing at least two frames of coded signals including the above.

SUMMARY OF THE INVENTION The first object of the present invention is to solve such a conventional problem, and it is a first object of the present invention to provide a coded signal decoding device in which input / output address control of a memory constituting a ring buffer is simple. A second object of the present invention is to provide a coded signal decoding device which can realize interpolation processing at the time of abnormal reproduction with a smaller memory capacity and can decode a reproduced signal of high quality.

[0017]

According to a first aspect of the invention of the present application, a synchronization detection is performed, in which a synchronization signal and a coded signal to which coded information is added in frame units are input and a sync signal in the coded signal is detected. Means, a memory for storing the encoded signal, a first address generating means for updating a write address of the memory according to an output of the synchronization detecting means, and a reading of the encoded signal stored in the memory. Second address generating means for generating an address and the coded signal read by the second address generating means are input, the coded signal is decoded to generate an output signal, and coded in the memory. The synchronization detecting means generates a write request signal for storing a signal, and further generates a write address in the first address generating means and a read address in the second address generating means. It is characterized in that it comprises a decoding means for controlling in response to the output.

In the invention of claim 2 of the present application, the first address generating means stores a write address when the encoded signal is stored in the memory according to the output of the synchronization detecting means. The decoding means controls the update of the write address so that the address of the synchronization signal becomes the head address for the first address generation means when the synchronization detection means detects the synchronization signal. To do.

In the invention of claim 3 of the present application, the decoding means identifies the synchronization signal in the encoded signal by the output of the synchronization detection means, and when the periodicity of the synchronization signal is abnormal, the decoding signal is transmitted. The output of the request signal for replenishing the memory is stopped, and the updating of the generated address in the first address generating means and the second address generating means is controlled to control the past valid code stored in the memory. It is characterized in that the encoded signal is decoded again.

In the invention of claim 4 of the present application, the decoding means calculates the frame length of the coded signal from the coded information in the coded signal read from the memory, and determines the cycle of the synchronization signal and the calculated frame. When the lengths are different from each other, the first address generating means is instructed to prohibit updating the address according to the output of the synchronization detecting means.

In the invention of claim 5 of the present application, the decoding means calculates the frame length of the coded signal from the coded information in the coded signal read from the memory, and calculates the cycle of the synchronization signal and the calculated frame. When the length is different, the reproduction level of the encoded signal read from the memory by the second address generating means is attenuated and then decoded.

According to the invention of claim 1 of the present application having such a feature, the write address of the encoded signal to be stored in the memory can be updated and controlled according to the synchronization state of the encoded signal.

According to the second aspect of the present invention, since only the coded signal of the valid frame in the synchronized state is stored in the memory from the head address, the latest coded signal of the valid frame and the latest synchronized state are identified. With the memory capacity required to store the synchronization signal, the encoded signal can be decoded and interpolated.

According to the third aspect of the present invention, for an input having an abnormal synchronization state, the encoded signal stored in the memory can be substituted for the output signal until the synchronization becomes stable.

According to the invention of claim 4, the reliability of synchronization detection can be confirmed by comparing the cycle of the detected synchronization signal with the frame length calculated from the encoded information.

Further, according to the fifth aspect of the present invention, when the synchronization state is abnormal, the signal level can be made inconspicuous by attenuating the output level when the encoded signal is decoded.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION A coded signal decoding apparatus according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the encoded signal decoding device according to the present embodiment. FIG. 2 shows the data in the memory 11 as addresses. The straight lines E, H, and I show the address change at the time of writing, and the broken line G shows the address conversion at the time of reading. In FIG. 3, a memory 11, a first address generating means 12 for generating a write address, a second address generating means 13 for generating a read address, and a decoding means 14 for an encoded signal are provided. This is similar to the conventional example. Unlike the conventional example, the memory 11 has a capacity of at least one frame, and the synchronization detecting means 10 is provided at the input portion of the encoded signal (SRD). The synchronization detecting means 10 is a means for detecting the synchronization signal included in the encoded signal and supplying it to the first address generating means 12 and the decoding means 14. If it is difficult to determine the synchronization signal due to the interruption of the input signal, only the confirmed signal is output.

The operation of the coded signal decoding apparatus of this embodiment (claim 1) configured as described above will be described. In FIG. 1, the coded signal input in bursts is temporarily stored in the memory 11. At that time, the synchronization detecting means 10 detects the synchronization signal in the encoded signal. The first address generation means 12 updates the write address according to the synchronization signal of the synchronization detection means 10. That is, when the input coded signal is in an asynchronous state, the write address is not updated. When the asynchronous state transits to the synchronous state, the first address generating means 12 sequentially outputs the synchronization signal and the coded information and the coded data following it from the head address E _{0 of the} memory, as indicated by the straight line E in FIG. Store.

Then, while the synchronization state continues, as shown in FIG.
The encoded signal is replenished up to the final write address E _n of the memory shown in FIG. 1, that is, until the memory 11 is full. Then, as indicated by a broken line G in FIG. 2, the encoded signal stored in the memory 11 is read at a constant bit rate based on the read address generated by the second address generating means 13, and the decoding means 14 Entered in.

The decoding means 14 is the second address generating means 1
After the coded signal input based on the output of 3 is identified as a sync signal, coded information, or coded data, the coded data is decoded using these.

The decoding means 14 is the second address generation means 1
When the fact that the encoded information for one frame stored in the memory 11 has been read out by the output of FIG.
The request signal RQD is output from t ₂ to request the memory 11 for input to supplement the coded signal.

[0032] If when the position of the synchronizing signal by the mismatch of the coded signal in the input is changed to the address E ₁ 2, may be shifted to data of the address E ₁ to E _n. That start address H ₀ of the first address generating unit 12 memory 11 as the output of the broken line F storage address E ₁ to E _n of the encoded signal is not read from the memory 11 in response to the decoding means 14 (= Shift to E ₀ ).

Then, the next coded signal input according to the result of the request signal RQD is sequentially stored from time t ₃ onward at the address H _{1 and} thereafter. Request signal RQ output by the decoding means 14
D stops writing when the write address by the first address generating means 12 reaches the final address H _{n of the} memory shown at time t ₄ .

As described above, in the coded signal decoding means of this embodiment, when the coded signal is stored in the memory 11, it is stored in the write address according to the detection result of the sync signal.
The decoding means 14 can accurately identify whether the coded signal read by the read address is a sync signal, coded information, or coded data.

Next, as a coded signal decoding measure according to claim 2 of the present invention, the second address generation means 13 has a function of storing the write address of the synchronization signal in the coded signal. In this way, by shifting the encoded signal stored in the memory 11, for example, the synchronizing signal existing at the address E ₁ is shifted to the address H ₀ (address E ₀ ),
The sync signal detected at address H ₂ can be shifted to address I ₀ on dashed line I. In this case, the sync signal is always stored in the head address of the memory 11, and the decoding means 14 can more easily decode the coded information and the coded data.

[0036]

As described above in detail, according to the present invention, when storing a coded signal input in bursts in a memory, a write address is formed according to a sync signal in the coded signal. Thus, generation and writing of the read address of the encoded signal necessary for decoding can be simplified. Further, even in the case of interpolation reproduction performed when the reproduction state is abnormal, the read address can be easily updated because the coded signal of the valid frame is stored from the head address of the memory. Therefore, the capacity of the memory for storing the encoded signal may be small, and an encoded signal decoding device having a small circuit scale can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a coded signal decoding device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a change in a write address of a memory in the encoded signal decoding device according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional coded signal decoding device.

FIG. 4 is an explanatory diagram showing changes in a write address of a memory in a conventional coded signal decoding device.

[Explanation of symbols]

 10 synchronization detection means 11 memory 12 first address generation means 13 second address generation means 14 decoding means

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[Procedure amendment]

[Submission date] July 5, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of the drawing

[Correction method] Change

[Correction contents]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a coded signal decoding device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing changes in a write address of a memory in the encoded signal decoding device according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional coded signal decoding device.

FIG. 4 is an explanatory diagram showing changes in a write address of a memory in a conventional coded signal decoding device.

FIG. 5 is a signal arrangement for each frame used in MPEG
FIG.

[Description of Reference Signs] 10 synchronization detecting means 11 memory 12 second address generating means 13 second address generating means 14 decoding means

Claims (5)

[Claims] 1. A synchronization detecting means for inputting a coded signal to which a sync signal or coded information is added in units of frames and detecting a sync signal in the coded signal, and a memory for storing the coded signal, First address generating means for updating a write address of the memory according to an output of the synchronization detecting means, second address generating means for generating a read address of an encoded signal stored in the memory, The coded signal read by the second address generation means is input, the coded signal is decoded to generate an output signal, and a write request signal for storing the coded signal in the memory is generated. And decoding means for controlling the generation of the write address in the first address generating means and the read address in the second address generating means according to the output of the synchronization detecting means. Coded signal decoding apparatus, characterized by Bei. 2. The first address generating means stores a write address for storing an encoded signal in the memory according to an output of the synchronization detecting means, and the decoding means comprises: 2. The updating of the write address is controlled by the first address generating means so that the address of the synchronizing signal becomes the head address when the synchronizing detecting means detects the synchronizing signal. The coded signal decoding device described. 3. The decoding means identifies the synchronization signal in the encoded signal based on the output of the synchronization detection means, and replenishes the encoded signal in the memory when the periodicity of the synchronization signal is abnormal. Stopping the output of the request signal, controlling the update of the generated address in the first address generating means and the second address generating means, and decoding the past valid coded signal stored in the memory again. The coded signal decoding device according to claim 1, wherein 4. The decoding means calculates a frame length of the coded signal from the coded information in the coded signal read from the memory, and when the cycle of the synchronization signal and the calculated frame length are different from each other, 2. The coded signal decoding apparatus according to claim 1, further comprising: an instruction to instruct the first address generating means to prohibit updating of an address according to an output of the synchronization detecting means. 5. The decoding means calculates a frame length of the encoded signal from the encoded information in the encoded signal read from the memory, and when the cycle of the synchronization signal and the calculated frame length are different from each other, 2. The coded signal decoding device according to claim 1, wherein the coded signal read out from the memory by the second address generation means is attenuated in a reproduction level and decoded.