JPH09246931A - Overload protective circuit for semiconductor device - Google Patents

Overload protective circuit for semiconductor device

Info

Publication number
JPH09246931A
JPH09246931A JP4784396A JP4784396A JPH09246931A JP H09246931 A JPH09246931 A JP H09246931A JP 4784396 A JP4784396 A JP 4784396A JP 4784396 A JP4784396 A JP 4784396A JP H09246931 A JPH09246931 A JP H09246931A
Authority
JP
Japan
Prior art keywords
current
voltage
reference value
circuit
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4784396A
Other languages
Japanese (ja)
Other versions
JP3191661B2 (en
Inventor
Hiroyuki Kawakami
浩之 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP04784396A priority Critical patent/JP3191661B2/en
Publication of JPH09246931A publication Critical patent/JPH09246931A/en
Application granted granted Critical
Publication of JP3191661B2 publication Critical patent/JP3191661B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To appropriately protect a semiconductor by utilizing a fact that a voltage applied to the semiconductor element of various ratings is almost similarly changed corresponding to the degree of an overload state, making a voltage monitoring device monitor the voltage and switching a comparison reference value with the current detection signal of a current monitoring device when it exceeds a reference value. SOLUTION: The voltage monitoring device 20 compares the current detection signals Si with a current reference value Eia while the value of a current (i) is normal or less than a regular overcurrent and the current reference value Eib is short-circuited, however, compares the current detection signals Si with a higher current reference value Eia+Eib since the current reference value Eib is released when the current (i) is increased more and the voltage (v) exceeds a voltage reference value Ev. In such a manner, by different comparison references corresponding to the current (i) made to flow to the semiconductor element 1, thus the degree of the voltage (v) applied to it, the device 20 is made to detect the overload state, normally an overcurrent state and a short-circuit state, by mutually different references and the element 1 is protected. Then, an optimum value corresponding to the degree of the weight of the overload state to be detected of the element 1 is accurately set by the current reference values Eia and Eib.

Description

【発明の詳細な説明】Detailed Description of the Invention

【発明の属する技術分野】本発明は電力用ブリッジ回路
等に用いられる半導体素子を軽度の過電流状態やその負
荷の短絡による重度の短絡電流状態等である過負荷状態
に応じて合理的に保護するための過負荷保護回路に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention rationally protects a semiconductor element used in a power bridge circuit or the like according to an overload condition such as a mild overcurrent condition or a severe short-circuit current condition due to a short circuit of its load. To an overload protection circuit.

【従来の技術】ブリッジ回路装置等に用いられる半導体
素子を保護するには、それに過電流や短絡電流等の異常
電流が流れていることを検出した上で電流を遮断し,な
いしは安全な電流値まで絞る必要があるので、半導体素
子に流れる電流をふつうは電流検出抵抗を用いて検出し
て検出信号値のレベルから正常状態か,過電流状態か,
短絡状態か等を判定し、この判定の結果に応じて半導体
素子に対し必要な保護を施すのが通例である。図4はか
かる従来例を示すものである。保護を施すべき対象は図
4の例では絶縁ゲートバイポーラトランジスタである半
導体素子1であり、ブリッジ回路装置の場合はもちろん
複数の半導体素子1がそれに組み込まれるが図にはブリ
ッジの下アーム側の1個だけが示されており、細線で示
すブリッジの電源2の電圧Vに対して負荷3と直列にコ
レクタ側の出力端子Toを介して接続されている。半導体
素子1用の駆動回路4はブリッジ回路を全体制御するブ
リッジ制御回路5からスイッチング指令Swを受け、それ
に応じて半導体素子1をそのゲート抵抗1bを介して駆動
する。半導体素子1の電流を検出するには図のようにそ
れに補助エミッタ1aを設けて電流検出抵抗6を接続し、
後者が前者から受ける電流によるその電圧降下を検出信
号Siとして取り出すのが通例である。この検出信号Siは
コンパレータ7と8に与えられる。コンパレータ7は検
出信号Siの信号値を短絡検出基準値Esと比べてそれを越
えたときに短絡状態と判定し、コンパレータ8は検出信
号Siの信号値を過電流検出基準値Eoと比べてそれを越え
たときに過電流状態と判定してそれぞれハイの比較出力
を発する。過電流検出基準値Eoはもちろん短絡検出基準
値Esより小さく設定される。両コンパレータ7と8の比
較出力は図の例ではそれぞれ遅延回路7aと8aを介してオ
アゲート9に与えられ、このオアゲート9のハイの出力
が保護指令Spとして駆動回路4に与えられる。検出信号
Siの信号値が過電流検出基準値Eoより高く短絡検出基準
値Esより低い過電流状態ではコンパレータ8の比較出力
だけがハイになり、遅延回路8aによる遅延時間の経過後
にオアゲート9から保護指令Spが出力される。短絡状態
では両コンパレータ7と8の比較出力がともにハイにな
るが、遅延回路7aの遅延時間が遅延回路8aより短く設定
されているので、コンパレータ8の比較出力が優先して
過電流状態の場合より短い時間後にオアゲート9から保
護指令Spが出力される。駆動回路4はこの保護指令Spを
受けると例えば半導体素子1に対する駆動動作を直ちに
停止するので、これにより半導体素子1はオフ動作して
それに流れている過電流または短絡電流である異常電流
を遮断する。なお、図4のコンパレータ7, 8やオアゲ
ート9等を含む保護回路は、場合により電流検出抵抗6
も含めて、各半導体素子1ごとに設けられる駆動回路4
用の集積回路チップに組み込んでおいて種々な定格の半
導体素子1の駆動と保護用に共通に利用するのがコスト
面で有利である。
2. Description of the Related Art In order to protect a semiconductor element used in a bridge circuit device or the like, an abnormal current such as an overcurrent or a short circuit current is detected and then the current is cut off, or a safe current value is set. Since it is necessary to narrow down the current to the semiconductor element, it is usually detected by using the current detection resistor to detect the level of the detection signal value from the normal state to the overcurrent state.
It is customary to determine whether or not a short-circuit state is present, and to apply necessary protection to the semiconductor element according to the result of this determination. FIG. 4 shows such a conventional example. The object to be protected is the semiconductor element 1 which is an insulated gate bipolar transistor in the example of FIG. 4, and in the case of the bridge circuit device, of course, a plurality of semiconductor elements 1 are incorporated therein. Only one of them is shown and connected to the voltage V of the power source 2 of the bridge indicated by the thin line in series with the load 3 via the output terminal To on the collector side. The drive circuit 4 for the semiconductor element 1 receives the switching command Sw from the bridge control circuit 5 that controls the bridge circuit as a whole, and accordingly drives the semiconductor element 1 via the gate resistor 1b. To detect the current of the semiconductor element 1, as shown in the figure, an auxiliary emitter 1a is provided and the current detection resistor 6 is connected,
It is customary for the latter to take out the voltage drop due to the current received from the former as the detection signal Si. This detection signal Si is given to the comparators 7 and 8. The comparator 7 compares the signal value of the detection signal Si with the short circuit detection reference value Es and determines that it is in the short circuit state when it exceeds it, and the comparator 8 compares the signal value of the detection signal Si with the overcurrent detection reference value Eo. When it exceeds, it is judged as an overcurrent state and a high comparison output is issued. Of course, the overcurrent detection reference value Eo is set smaller than the short circuit detection reference value Es. In the illustrated example, the comparison outputs of the two comparators 7 and 8 are given to the OR gate 9 via the delay circuits 7a and 8a, respectively, and the high output of the OR gate 9 is given to the drive circuit 4 as the protection command Sp. Detection signal
In the overcurrent state where the signal value of Si is higher than the overcurrent detection reference value Eo and lower than the short circuit detection reference value Es, only the comparison output of the comparator 8 becomes high, and the protection command Sp is output from the OR gate 9 after the delay time by the delay circuit 8a elapses. Is output. In the short-circuited state, the comparison outputs of both comparators 7 and 8 both become high, but the delay time of the delay circuit 7a is set shorter than that of the delay circuit 8a. After a shorter time, the OR gate 9 outputs the protection command Sp. When the drive circuit 4 receives this protection command Sp, for example, the drive operation for the semiconductor element 1 is immediately stopped, so that the semiconductor element 1 is turned off and the overcurrent or the abnormal current that is a short-circuit current flowing through it is cut off. . The protection circuit including the comparators 7 and 8 and the OR gate 9 shown in FIG.
Drive circuit 4 provided for each semiconductor element 1 including
It is advantageous in terms of cost to incorporate the same into an integrated circuit chip for use and commonly use it for driving and protecting the semiconductor elements 1 having various ratings.

【発明が解決しようとする課題】しかし、図4のような
従来の保護回路には構成回路要素の個数がかなり多くて
コスト面で不利なほか、前述の短絡検出基準値Esや過電
流検出基準値Eoの設定が必ずしも容易でない問題があ
る。すなわち、図4の保護回路の2個のコンパレータ
7, 8とオアゲート9にそれぞれ数〜10個のトランジス
タが必要なので、駆動回路4用の集積回路に組み込む際
に保護回路の方に駆動回路4よりも広いチップ面積を割
く必要が生じてチップコストが高くついてしまうからで
ある。また、半導体素子1の定格が異なると保護に最も
望ましい短絡検出基準値Esと過電流検出基準値Eoの差な
いしは比率が微妙に異なってくるので、単に各半導体素
子1の電流定格に合わせて電流検出抵抗6の抵抗値を設
定するだけでは充分な対処ができず、従って前述のよう
に種々な定格の半導体素子1に共通に同じ集積回路チッ
プを用いるのでは充分な保護を施せないことになる。本
発明の課題は従来の保護回路がもつかかる問題点を解決
して、半導体素子の電流定格や電圧定格が種々異なる場
合にもできるだけ簡単な回路構成で従来より望ましい保
護を施すことができる過負荷保護回路を提供することに
ある。
However, the conventional protection circuit as shown in FIG. 4 has a large number of constituent circuit elements, which is disadvantageous in terms of cost. In addition, the above-mentioned short-circuit detection reference value Es and overcurrent detection reference are provided. There is a problem that setting the value Eo is not always easy. That is, since the comparators 7 and 8 and the OR gate 9 of the protection circuit of FIG. 4 each require several to ten transistors, the protection circuit needs to be connected to the drive circuit 4 more than the drive circuit 4 when it is incorporated in the integrated circuit for the drive circuit 4. This is because it is necessary to devote a large chip area and the chip cost becomes high. If the rating of the semiconductor element 1 is different, the difference or ratio between the short-circuit detection reference value Es and the overcurrent detection reference value Eo, which is the most desirable for protection, will be slightly different. Therefore, simply adjust the current according to the current rating of each semiconductor element 1. Sufficient measures cannot be taken merely by setting the resistance value of the detection resistor 6. Therefore, as described above, if the same integrated circuit chip is commonly used for the semiconductor elements 1 having various ratings, sufficient protection cannot be provided. . An object of the present invention is to solve the problems of the conventional protection circuit, and to provide more desirable protection than the conventional one with a circuit configuration as simple as possible even when the semiconductor device has various current ratings and voltage ratings. It is to provide a protection circuit.

【課題を解決するための手段】上記の課題は本発明の半
導体素子の過負荷保護回路によれば、保護を施すべき半
導体素子に流れる電流を検出してその電流値を表す信号
値の検出信号を発する電流検出手段と,検出信号の信号
値を監視してそれが電流基準値を越えたときに保護指令
を出力する電流監視手段と,半導体素子に掛かる電圧値
を電圧基準値と比較して両値の大小に応じ論理状態が変
わる比較信号を発する電圧監視手段と,比較信号の論理
状態に応じて電流基準値と電流検出信号値のいずれかの
レベルを切り換える切換手段とを用い、保護指令に基づ
いて半導体素子を過負荷状態から解除することによって
解決される。上記の構成をもつ本発明の保護回路は、半
導体素子の電流や電圧の定格が種々異なってもそれに掛
かる電圧が過負荷状態に応じて同様に変化する点に着目
し、それを利用して半導体素子にその過電流状態や短絡
状態に適した合理的な保護を施すようにしたものであ
る。すなわち本発明は、上記構成にいう電圧監視手段に
半導体素子に掛かる電圧値を所定の電圧基準値と比較し
ながら両値の大小に応じ論理状態が変わる比較信号を発
生させ、切換手段によりその論理状態に応じ電流検出手
段に与えるべき電流基準値または電流検出信号値を切り
換えることにより半導体素子にその過負荷状態に適した
合理的な保護を施すものである。なお、本発明において
も前記構成にいう切換手段により、従来と同様に半導体
素子の過電流状態と短絡状態とを区別して電流監視手段
に検出させるように電流基準値や電流検出信号値を切り
換えるのがよい。また、過電流状態や短絡状態はごく短
時間だけ発生することが多く、そのつどに半導体素子に
保護を施すと負荷電流の無用な遮断が頻発することにな
り兼ねないので、電流監視手段に付随して保護指令の遅
延手段を設けて、遅延後の保護指令に基づいて半導体素
子に対する保護を開始するようにした方が実用面で有利
である。電圧監視手段は例えばコンパレータを利用して
適宜構成することができるが、その回路構成をできるだ
け簡単化するために制御電源電圧を受ける分圧手段と,
その分圧点に接続されて半導体素子に掛かる電圧を逆方
向に受けるダイオードとから電圧監視手段を構成し、分
圧手段の分圧点の電位を比較信号として導出するのが非
常に有利である。電流検出手段に与える電流基準値や電
流検出信号値を簡単に切り換えるには、2個の電流基準
値を用いて切換手段に一方の電流基準値を短絡または釈
放させることにより、電流監視手段に他方の電流基準値
と両電流基準値の和を切り換えて付与するようにし、あ
るいは電流検出手段として直列接続された2個の電流検
出抵抗を用いて一方の電流検出抵抗を切換手段に短絡ま
たは釈放させるのが有利である。この場合の切換手段は
通常のトランジスタを用いて簡単に構成できるが、デプ
リーション形のトランジスタを利用することにより構成
をさらに簡単化することができる。
According to the overload protection circuit for a semiconductor device of the present invention, the above-mentioned problem is detected by detecting a current flowing through a semiconductor device to be protected and detecting a signal value representing the current value. Comparing the voltage value applied to the semiconductor device with the voltage value applied to the semiconductor element, the current detection means for emitting a signal, the current monitoring means for monitoring the signal value of the detection signal and outputting a protection command when it exceeds the current reference value. Using a voltage monitoring means for issuing a comparison signal whose logic state changes depending on the magnitude of both values, and a switching means for switching between the current reference value and the current detection signal value level according to the logic state of the comparison signal, a protection command is provided. It is solved by releasing the semiconductor device from the overload state based on The protection circuit of the present invention having the above-mentioned configuration pays attention to the fact that the voltage applied to the semiconductor element varies similarly in accordance with the overload state even if the current and voltage ratings of the semiconductor element are different, and a semiconductor circuit The element is provided with reasonable protection suitable for the overcurrent state and the short-circuit state. That is, the present invention generates a comparison signal whose logic state changes according to the magnitude of both values while comparing the voltage value applied to the semiconductor element with the predetermined voltage reference value in the voltage monitoring means having the above-mentioned configuration, and the switching means outputs the logic signal. By switching the current reference value or the current detection signal value to be given to the current detection means according to the state, the semiconductor element is provided with a reasonable protection suitable for the overload state. Also in the present invention, the current reference value and the current detection signal value are switched by the switching means in the above-described configuration so that the current monitoring means can detect the overcurrent state and the short-circuit state of the semiconductor element as in the conventional case. Is good. In addition, an overcurrent state or a short-circuit state often occurs only for a very short time, and protection of the semiconductor element in each case may lead to frequent unnecessary interruption of the load current. Then, it is more practical in practice to provide a protection command delay means and start protection of the semiconductor element based on the protection command after the delay. The voltage monitoring means can be appropriately configured by using, for example, a comparator, but in order to simplify the circuit configuration as much as possible, voltage dividing means for receiving the control power supply voltage,
It is very advantageous to construct the voltage monitoring means from the diode connected to the voltage dividing point and receiving the voltage applied to the semiconductor element in the opposite direction, and derive the potential at the voltage dividing point of the voltage dividing means as the comparison signal. . In order to easily switch the current reference value and the current detection signal value given to the current detection means, the current monitoring means is made to short-circuit or release one current reference value by using the two current reference values. The current reference value and the sum of both current reference values are switched and applied, or one current detection resistance is short-circuited or released by the switching means by using two current detection resistances connected in series as the current detection means. Is advantageous. The switching means in this case can be easily configured by using a normal transistor, but the configuration can be further simplified by using a depletion type transistor.

【発明の実施の形態】以下、図面を参照しながら本発明
の望ましい実施形態を説明する。図1は電流基準値を切
り換える本発明の実施形態を示すブロック回路図、図2
は図1の実施形態に対応する具体回路図、図3は電流検
出信号値を切り換える実施形態を示す回路図であって、
いずれにも図4に対応する部分に同じ符号が付されてい
るので重複部分の説明は適宜省略することとする。 図
1に示す半導体素子1は前に説明した図4の従来例と同
様にブリッジ回路の下アームに組み込まれており、ブリ
ッジの負荷3がふつうは誘導性なのでフリーホイーリン
グ用のダイオード1cが半導体素子1に対し逆並列に接続
されている。ブリッジ回路が受ける入力電圧Vの直流電
源2, 負荷3, 駆動回路4, ブリッジ制御回路5等は図
4の従来例と同じである。半導体素子1に流れる電流i
を検出する電流検出手段10は従来例と同じく補助エミッ
タ1aに接続された電流検出抵抗11からなり、その補助エ
ミッタ電流による電圧降下が電流検出信号Siとして導出
される。なお、半導体素子1は所定周期でオンオフ動作
し, それに伴って電流iが断続されるから、検出信号Si
も電流iと同じ断続波形をもっている。電流監視手段20
は単一のコンパレータ21からなり、その一方の入力に上
述の検出信号Siを受けてその信号値を正常な状態では他
方の入力に受けている電流基準値Eiaと比較して、前者
の値が後者の値を越えたとき保護指令Spを出力する。こ
の保護指令Spにより駆動回路4にすぐ半導体素子1をオ
フ動作させてもよいが、図示の実施形態では保護指令Sp
を遅延手段22を介して駆動回路4に与えるように構成さ
れている。電圧監視手段30は半導体素子1に掛かる電圧
v, つまり絶縁ゲートバイポーラトランジスタのコレク
タ・エミッタ間電圧を受けて常時その値を電圧基準値Ev
と比較して両値の大小に応じて論理状態が変わる比較信
号Scを発するもので、この実施形態では監視電圧値vが
電圧基準値Evを越えたとき比較信号Scの論理状態がロー
からハイに変化するものとする。なお、電圧監視手段30
が監視する電圧vは半導体素子1に流れる電流iに対
し、電流値がごく小さい範囲を除いて電流iの増加とと
もにほぼ直線的に上昇して行く特性をもっている。本発
明では上述の比較信号Scの論理状態に応じ切換手段40に
電流監視手段20に与えるべき電流基準値を切り換えさせ
るが、図1の実施形態では直列接続された2個の電流基
準値EiaとEibを設け, 切換手段40に単一のスイッチを
用いて電流基準値Eibを比較信号Scの論理状態がローの
とき短絡し, ハイのとき釈放する。従って、電流監視手
段20には比較信号Scがローのとき電流基準値Eiaが, ハ
イのとき両電流基準値Eia, Eibの和がそれぞれ与えられ
る。以上のように構成された図1の保護回路では、電圧
監視手段30に付与する電圧基準値Evを例えば半導体素子
1に流れる電流iが短絡電流に近付いたときそれに掛か
る電圧vと同じ程度になるように設定する。これによ
り、電流監視手段20は電流iの値が正常かふつうの過電
流以下で電流基準値Eibが短絡されている間は電流検出
信号Siを電流基準値Eiaと比較するが、電流iがさらに
増えて電圧vが電圧基準値Evを越えると電流基準値Eib
が釈放されるから電流検出信号Siをより高い電流基準値
Eia+Eibと比較する。このように本発明回路では半導体
素子1に流れる電流i, 従ってそれに掛かる電圧vの程
度に応じて異なる比較基準で電流監視手段20にその過負
荷状態, ふつうは過電流状態と短絡状態とを互いに異な
る基準で検出させて半導体素子1を保護する。以上のよ
うに本発明では半導体素子1の電流iとともに増加する
電圧vを電圧監視手段30に監視させ、それが電圧基準値
Evを越えたとき切換手段40により電流基準値を切り換え
るので、電流監視手段20による電流の検出信号Siとの比
較動作基準としての電流基準値をこの実施形態では電流
基準値EiaとEibにより半導体素子1の検出すべき過負
荷状態の軽重の度合いに応じた最適値に容易かつ正確に
設定することができる。電流監視手段20がこのような電
流基準値 Eiaまたは Eia+Eibに基づいて半導体素子1の
過負荷状態を検出したとき発する保護指令Spは電流検出
信号Siが前述のように断続波形である場合はそれに応じ
て繰り返しパルス波形になるが、それを受ける遅延手段
22は保護指令Spのかかる波形の確定を確かめる機能をも
ち、その確認後に始めてハイの保護指令Spを駆動回路4
に与える。駆動回路4はこの実施形態では保護指令Spに
応じ通例のように半導体素子1をオフ動作させて電流i
を遮断させることによりそれを過負荷状態から解除す
る。図2に図1の保護回路のより具体的な構成例を示
す。この実施形態の電圧監視手段30は半導体素子1から
監視すべき電圧vを逆方向に受けるダイオード31と,制
御電源電圧Vdを受け分圧点がダイオード31と接続された
分圧手段32からなり、分圧手段32の分圧点の電位が比較
信号Scとして導出される。分圧手段32は通例のように1
対の分圧抵抗32a, 32bから構成され、その分圧が電圧基
準値Evである。この電圧基準値Evは正常状態やふつう程
度の過電流状態において半導体素子1に掛かる電圧vと
ダイオード31の順方向電圧との和より高く設定されてい
るので、これらの状態ではダイオード31が導通して比較
信号Scはローの論理値をとるが、短絡状態に近くなって
電圧vが増加するとダイオード31が非導通状態になるの
で電圧基準値Evが比較信号Scのハイの論理値として出力
される。この実施形態の切換手段40には常時オン状態に
あるデプリーション形のトランジスタ41が用いられてお
り、電流基準値 Eibを比較信号Scがローのとき短絡し,
ハイのとき釈放する。もちろん、かかる切換手段40はエ
ンハンスメント形トランジスタを2段に組み合わせても
構成できる。なお、半導体素子1のオンオフ動作に伴い
それに掛かる電圧vも変動するが、ブリッジ回路では半
導体素子1のオフ状態でフリーホイーリングダイオード
1cが導通して電圧vは負値をとる。このため、ふつうの
過電流状態では電圧vが電圧基準値Evを常に下回って比
較信号Scは安定したローの状態になるが、短絡状態にな
ると比較信号Scはパルス状のハイを繰り返す波形にな
る。この短絡状態で電流監視手段20は電流基準値として
Eia+Eibと Eiaを交互に受けるが、電流基準値がEiaに
なる時間内は幸いなことに電流検出信号Scが0かごく小
さな値をとるので電流監視手段20の短絡状態の検出動作
に支障は生じない。図2の実施形態では遅延手段22に抵
抗22aとキャパシタ22bからなるCR時定数回路ないしは
充放電回路を用いる。過負荷状態で電流監視手段20から
発せられる保護指令Spは前述のようにハイのパルスの繰
り返し波形になるので、抵抗22aを介してキャパシタ22
bが保護指令Spのハイの時間内に充電され, ローの時間
内に放電される。キャパシタ22bが充分充電される前に
過負荷状態が消失するとこの短時間の過負荷状態は無視
されてしまうが、充電電圧が所定のしきい値まで立ち上
がると駆動回路4はそれを確定したハイの保護指令Spと
して受け付けて直ちに半導体素子1に対する保護動作に
入る。いま、半導体素子1が過電流状態にあって電流監
視手段20が電流基準値 Eiaを受けているとすると、その
際の検出信号Siのピーク値はもちろん過電流の程度に応
じて変化し、このピーク値が高いほど検出信号Siの信号
値が電流基準値 Eiaを越える時間が長くなり, 電流監視
手段20が発する保護指令Spのハイのパルス幅が広くなる
から、上述のキャパシタ22bの充電電圧はピーク値が低
いときより早く立ち上がる。これからわかるように、こ
の図2の遅延手段22により過電流状態の半導体素子1を
駆動回路4に保護させるまでの遅延時間ないしは時限を
過電流の大きさに応じて自動調整することができる。短
絡状態の半導体素子1はもちろん短時限で保護すること
が望ましく、ふつうは電流基準値 Eibを Eiaと同じ程度
に設定することによりこの要請を満たすことができる。
図3の実施形態では電圧監視手段30による比較信号Scの
論理状態に応じて電流検出手段10の検出感度を切り換え
る。このため、電流検出手段10用に図示の実施形態では
直列接続された2個の電流検出抵抗11aと11bを設け
て、接地点E側の電流検出抵抗11bを切換手段40により
比較信号Scのハイまたはローに応じて短絡または釈放す
る。例えば半導体素子1の短絡状態を検出する際にはこ
の電流検出抵抗11bを短絡し, その過電流状態を高感度
で検出する際にはそれを釈放する。このように短絡状態
と過電流状態を検出する場合は両電流検出抵抗11aと11
bを同程度の抵抗値に設定するのがよい。電流監視手段
20はこの電流検出手段10から検出信号Scをコンパレータ
21に受けるが, 検出信号Scが半導体素子1の電流iを上
述のように調整された感度で検出した結果であるからそ
の信号値を比較すべき電流基準値はこの実施形態では一
定値Eiに固定することでよい。電圧監視手段30はもちろ
ん図2と同じ構成としてもよいが、図の実施形態ではコ
ンパレータ33と遅延手段34から構成される。コンパレー
タ33は半導体素子1に掛かる電圧vを電圧基準値Evと比
較するもので、遅延手段34はその出力を受ける抵抗34a
とキャパシタ34bとを備える保護指令Sp用の遅延手段22
と同様な充放電回路である。前述のように電圧vの波形
のピーク値が電圧基準値Evを越えたときコンパレータ33
はハイのパルスの繰り返し波形をもつ出力を発し、この
パルスにより遅延回路34のキャパシタ34bの充電電圧が
所定値まで立ち上がったときこの電圧監視手段30による
比較信号Scのハイが確立する。電圧監視手段30によるこ
の比較信号Scは図2の実施形態の場合の繰り返しパルス
状波形とは異なり、ローとハイの確定した2個の論理状
態をとる。この実施形態では前述の電流検出抵抗11bを
短絡, 釈放する切換手段40としてふつうのエンハンスメ
ント形のnチャネルトランジスタが用いられている。こ
の切換手段40は検出抵抗11bを比較信号Scがローの間は
釈放し, そのハイの確立に応じて短絡する動作を行な
う。さらに、図3の実施形態では電圧監視手段30による
比較信号Scが駆動回路4に与えられる。これは半導体素
子1の過電流状態と短絡状態でその保護形態を切り換え
得るようにするためであり、駆動回路4は例えば比較信
号Scがハイの状態で保護指令Spを受けると短絡発生と判
断して半導体素子1を直ちにオフさせるが、比較信号Sc
がローの状態で保護指令Spを受けたときは過電流状態と
判断して異常信号Soをブリッジ制御回路5に送る。通常
はマイクロプロセッサであるブリッジ制御回路5はその
時のブリッジ回路の運転状態から判断して駆動回路4に
対するスイッチング指令Swを直ちに停止するか, そのオ
ンオフのデューティ比を下げて半導体素子1を保護する
かを選択できるので、ブリッジ回路全体の観点からより
合理的な保護を半導体素子1に施すことができる。本発
明は以上の実施形態に限らず種々な回路構成で実施でき
る。例えば、比較信号Scのハイの論理状態の確立のため
図3の回路で用いた遅延手段34のかわりにフリップフロ
ップを利用してもよい。また、以上の実施形態では半導
体素子1をすべて絶縁ゲートバイポーラトランジスタと
したが、もちろんそれが他の半導体素子であっても本発
明を適用できる。
BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. 1 is a block circuit diagram showing an embodiment of the present invention for switching a current reference value, FIG.
Is a specific circuit diagram corresponding to the embodiment of FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment for switching the current detection signal value.
In each case, the same reference numerals are given to the portions corresponding to FIG. 4, and the description of the overlapping portions will be omitted as appropriate. The semiconductor element 1 shown in FIG. 1 is incorporated in the lower arm of the bridge circuit as in the conventional example of FIG. 4 described above. Since the load 3 of the bridge is usually inductive, the diode 1c for freewheeling is a semiconductor. It is connected in antiparallel to the element 1. The DC power supply 2 of the input voltage V received by the bridge circuit 2, the load 3, the drive circuit 4, the bridge control circuit 5 and the like are the same as in the conventional example of FIG. Current i flowing through the semiconductor element 1
The current detecting means 10 for detecting is composed of the current detecting resistor 11 connected to the auxiliary emitter 1a as in the conventional example, and the voltage drop due to the auxiliary emitter current is derived as the current detection signal Si. The semiconductor element 1 is turned on and off at a predetermined cycle, and the current i is interrupted accordingly.
Also has the same intermittent waveform as the current i. Current monitoring means 20
Consists of a single comparator 21, receives the above-mentioned detection signal Si at one of its inputs, compares the signal value with the current reference value Eia received at the other input in a normal state, and the former value is When the latter value is exceeded, protection command Sp is output. Although the semiconductor element 1 may be immediately turned off by the drive command 4 by this protection command Sp, in the illustrated embodiment, the protection command Sp
Is provided to the drive circuit 4 via the delay means 22. The voltage monitoring means 30 receives the voltage v applied to the semiconductor element 1, that is, the collector-emitter voltage of the insulated gate bipolar transistor, and always sets the value to the voltage reference value Ev.
The comparison signal Sc whose logic state changes depending on the magnitude of both values is compared with the above. In this embodiment, when the monitoring voltage value v exceeds the voltage reference value Ev, the logic state of the comparison signal Sc changes from low to high. Shall be changed to. The voltage monitoring means 30
Has a characteristic that the voltage v monitored by is increased almost linearly with respect to the current i flowing through the semiconductor element 1 with the increase of the current i except in the range where the current value is very small. In the present invention, the switching means 40 is caused to switch the current reference value to be given to the current monitoring means 20 according to the logic state of the above-mentioned comparison signal Sc. In the embodiment of FIG. 1, two current reference values Eia connected in series are used. Eib is provided, and a single switch is used as the switching means 40 to short-circuit the current reference value Eib when the logic state of the comparison signal Sc is low and when it is high. Therefore, the current monitoring means 20 is provided with the current reference value Eia when the comparison signal Sc is low and the sum of both current reference values Eia and Eib when it is high. In the protection circuit of FIG. 1 configured as described above, the voltage reference value Ev applied to the voltage monitoring means 30 becomes about the same as the voltage v applied to the short circuit current when the current i flowing through the semiconductor element 1 approaches the short circuit current. To set. As a result, the current monitoring means 20 compares the current detection signal Si with the current reference value Eia while the value of the current i is normal or less than a normal overcurrent and the current reference value Eib is short-circuited. When the voltage increases and the voltage v exceeds the voltage reference value Ev, the current reference value Eib
The current detection signal Si to a higher current reference value
Compare with Eia + Eib. As described above, in the circuit of the present invention, the current monitoring means 20 is set to the overloaded state, usually the overcurrent state and the short-circuited state, on the basis of the different comparison reference depending on the current i flowing in the semiconductor element 1 and thus the voltage v applied thereto. The semiconductor element 1 is protected by detecting with different criteria. As described above, according to the present invention, the voltage v which increases with the current i of the semiconductor element 1 is monitored by the voltage monitoring means 30, which is the voltage reference value.
When Ev is exceeded, the current reference value is switched by the switching means 40. Therefore, in this embodiment, the current reference value as a reference operation for comparing the current with the detection signal Si of the current by the current monitoring means 20 is determined by the current reference values Eia and Eib. It is possible to easily and accurately set the optimum value of 1 according to the degree of lightness of the overload state to be detected. The protection command Sp issued when the current monitoring means 20 detects the overload state of the semiconductor element 1 based on the current reference value Eia or Eia + Eib is as follows when the current detection signal Si has an intermittent waveform. According to it, it becomes a repetitive pulse waveform, but the delay means to receive it.
22 has a function of confirming the confirmation of the waveform to which the protection command Sp is applied. Only after the confirmation, the protection command Sp of high is driven by the drive circuit 4
Give to. In this embodiment, the drive circuit 4 turns off the semiconductor element 1 in accordance with the protection command Sp to turn off the current i as usual.
It is released from the overload condition by shutting off. FIG. 2 shows a more specific configuration example of the protection circuit of FIG. The voltage monitoring means 30 of this embodiment comprises a diode 31 which receives the voltage v to be monitored from the semiconductor element 1 in the reverse direction, and a voltage dividing means 32 which receives the control power supply voltage Vd and has a voltage dividing point connected to the diode 31. The potential at the voltage dividing point of the voltage dividing means 32 is derived as the comparison signal Sc. The voltage dividing means 32 is 1 as usual.
It is composed of a pair of voltage dividing resistors 32a and 32b, and the voltage dividing value is the voltage reference value Ev. Since the voltage reference value Ev is set higher than the sum of the voltage v applied to the semiconductor element 1 and the forward voltage of the diode 31 in the normal state or a normal overcurrent state, the diode 31 conducts in these states. Accordingly, the comparison signal Sc takes a low logical value, but when the voltage v increases near the short-circuited state and the diode 31 becomes non-conductive, the voltage reference value Ev is output as a high logical value of the comparison signal Sc. . The switching means 40 of this embodiment uses a depletion type transistor 41 that is always on, and shorts the current reference value Eib when the comparison signal Sc is low,
Release when high. Of course, the switching means 40 can also be constructed by combining enhancement type transistors in two stages. Although the voltage v applied to the semiconductor element 1 also fluctuates with the on / off operation of the semiconductor element 1, in the bridge circuit, the free wheeling diode is used when the semiconductor element 1 is off.
1c becomes conductive and the voltage v takes a negative value. Therefore, in a normal overcurrent state, the voltage v is always lower than the voltage reference value Ev and the comparison signal Sc is in a stable low state, but in the short-circuit state, the comparison signal Sc has a waveform in which pulse-like high is repeated. . In this short-circuit state, the current monitoring means 20
Eia + Eib and Eia are received alternately, but fortunately the current detection signal Sc takes 0 or a very small value during the time when the current reference value becomes Eia, which hinders the detection operation of the short circuit state of the current monitoring means 20. Does not occur. In the embodiment of FIG. 2, a CR time constant circuit or a charging / discharging circuit including a resistor 22a and a capacitor 22b is used as the delay means 22. Since the protection command Sp issued from the current monitoring means 20 in the overload state has a repetitive waveform of high pulse as described above, the capacitor 22 is connected via the resistor 22a.
b is charged during the high time of the protection command Sp and discharged during the low time. If the overload state disappears before the capacitor 22b is sufficiently charged, this short-time overload state is ignored, but when the charging voltage rises to a predetermined threshold value, the drive circuit 4 determines it to be high. The protection operation for the semiconductor element 1 is immediately started after being accepted as the protection command Sp. Now, assuming that the semiconductor element 1 is in the overcurrent state and the current monitoring means 20 receives the current reference value Eia, the peak value of the detection signal Si at that time naturally changes according to the degree of the overcurrent. The higher the peak value, the longer the signal value of the detection signal Si exceeds the current reference value Eia, and the wider the high pulse width of the protection command Sp issued by the current monitoring means 20 is. Therefore, the charging voltage of the capacitor 22b is It rises faster than when the peak value is low. As can be seen from this, the delay time or the time until the drive circuit 4 protects the semiconductor element 1 in the overcurrent state can be automatically adjusted by the delay means 22 of FIG. 2 according to the magnitude of the overcurrent. Of course, it is desirable to protect the semiconductor element 1 in the short-circuited state for a short period of time. Usually, this requirement can be satisfied by setting the current reference value Eib to the same level as Eia.
In the embodiment of FIG. 3, the detection sensitivity of the current detection means 10 is switched according to the logic state of the comparison signal Sc by the voltage monitoring means 30. Therefore, in the illustrated embodiment, two current detection resistors 11a and 11b connected in series are provided for the current detection means 10, and the current detection resistance 11b on the ground point E side is switched by the switching means 40 to the high level of the comparison signal Sc. Or short circuit or release depending on low. For example, the current detection resistor 11b is short-circuited when detecting the short-circuit state of the semiconductor element 1, and released when detecting the overcurrent state with high sensitivity. In this way, when detecting a short circuit state and an overcurrent state, both current detection resistors 11a and 11
It is preferable to set b to the same resistance value. Current monitoring means
20 is a comparator for the detection signal Sc from the current detection means 10.
21, the detection signal Sc is the result of detecting the current i of the semiconductor element 1 with the sensitivity adjusted as described above, so that the current reference value with which the signal value is to be compared is a constant value Ei in this embodiment. It can be fixed. The voltage monitoring means 30 may of course have the same configuration as that of FIG. 2, but in the illustrated embodiment, it comprises a comparator 33 and a delay means 34. The comparator 33 compares the voltage v applied to the semiconductor element 1 with the voltage reference value Ev, and the delay means 34 receives the output of the resistor 34a.
And a delay means 22 for protection command Sp including a capacitor 34b
It is a charging / discharging circuit similar to. As described above, when the peak value of the waveform of the voltage v exceeds the voltage reference value Ev, the comparator 33
Emits an output having a repeating waveform of a high pulse, and when this pulse causes the charging voltage of the capacitor 34b of the delay circuit 34 to rise to a predetermined value, the high level of the comparison signal Sc by the voltage monitoring means 30 is established. This comparison signal Sc by the voltage monitoring means 30 has two defined logic states of low and high, unlike the repetitive pulse-like waveform in the embodiment of FIG. In this embodiment, a normal enhancement type n-channel transistor is used as the switching means 40 for short-circuiting and releasing the current detecting resistor 11b. The switching means 40 releases the detection resistor 11b while the comparison signal Sc is low, and short-circuits according to the establishment of the high level. Furthermore, in the embodiment of FIG. 3, the comparison signal Sc from the voltage monitoring means 30 is given to the drive circuit 4. This is so that the protection mode can be switched between the overcurrent state and the short circuit state of the semiconductor element 1, and the drive circuit 4 judges that a short circuit has occurred when the protection signal Sp is received when the comparison signal Sc is high, for example. To turn off the semiconductor element 1 immediately, but the comparison signal Sc
When the protection command Sp is received in a low state, it is determined that the current is an overcurrent state and the abnormal signal So is sent to the bridge control circuit 5. Whether the bridge control circuit 5, which is usually a microprocessor, immediately stops the switching command Sw to the drive circuit 4 by judging from the operating state of the bridge circuit at that time, or reduces the on / off duty ratio to protect the semiconductor element 1 Can be selected, the semiconductor element 1 can be protected more reasonably from the viewpoint of the entire bridge circuit. The present invention is not limited to the above embodiments and can be implemented with various circuit configurations. For example, a flip-flop may be used in place of the delay means 34 used in the circuit of FIG. 3 for establishing the high logic state of the comparison signal Sc. Further, in the above embodiments, all the semiconductor elements 1 are insulated gate bipolar transistors, but of course, the present invention can be applied to other semiconductor elements.

【発明の効果】以上のように本発明による過負荷保護回
路では、保護を施すべき半導体素子に流れる電流を検出
してその電流値を表す検出信号を発する電流検出手段
と,その信号値を監視して電流基準値を越えたとき保護
指令を出力する電流監視手段と,半導体素子に掛かる電
圧値を電圧基準値と比較して両値の大小に応じ論理状態
が切り換わる比較信号を発する電圧監視手段と,比較信
号の論理状態に応じて電流基準値または電流検出信号値
のレベルを切り換える切換手段を用い、保護指令に基づ
いて半導体素子の過負荷状態を解除するようにしたの
で、種々な定格の半導体素子に掛かる電圧が過負荷状態
の程度に応じてほぼ同様に変化する点を利用して電圧監
視手段にこの電圧を監視させ、それが電圧基準値を越え
たときに電流監視手段の電流検出信号との比較基準値を
切換手段により切り換えるので、半導体素子の電流定格
や電圧定格が異なっても過負荷状態の程度,例えば過電
流状態や短絡状態を区別しながらそれぞれ正確に検出し
てその軽重の度合いに応じた適切な保護を半導体素子に
施すことができる。本発明回路は電流基準値や電圧基準
値を適宜に設定すれば同じ回路構成で各種定格の半導体
素子の保護に共通に利用できるので、これを小形チップ
に集積化しあるいは駆動回路用の集積回路チップに組み
込むことにより、ブリッジ回路等を構成する半導体素子
ごとに用いられる過負荷保護回路のコストを従来より大
幅に低減することができる。なお、電流監視手段に付随
して保護指令用に遅延手段を設けて、遅延後の保護指令
に基づいて半導体素子に保護を施す本発明の実施形態
は、ごく短時間だけの過負荷状態に応じて負荷電流の遮
断等の有害無益な保護動作が頻発するおそれをなくし、
遅延手段に適度な動作時定数ないしは充放電特性をもた
せることにより過負荷保護動作に望ましい時限特性を付
与できる効果を有する。また、電圧監視手段として所定
の電源電圧を受ける分圧手段と,その分圧点に接続され
て半導体素子に掛かる電圧を逆方向に受けるダイオード
とを用い、分圧手段の分圧点の電位を比較信号として導
出する本発明の実施形態は、ごく簡単な回路構成により
電圧基準値を分圧手段の分圧比により容易かつ正確に設
定できる利点を有する。さらに、2個の電流基準値を用
いて切換手段に一方の電流基準値を短絡または釈放させ
ることにより、電流監視手段に他方の電流基準値と両電
流基準値の和を切り換えて付与する実施形態、および電
流検出手段として直列接続された2個の電流検出抵抗を
用いて一方の電流検出抵抗を切換手段により短絡または
釈放する実施形態は、いずれもごく簡単な切換手段によ
って電流基準値や電流検出信号のレベルを正確に切り換
え得る利点がある。
As described above, in the overload protection circuit according to the present invention, the current detection means for detecting the current flowing through the semiconductor element to be protected and issuing a detection signal representing the current value, and monitoring the signal value thereof. Current monitoring means for outputting a protection command when the current reference value is exceeded, and voltage monitoring for issuing a comparison signal that compares the voltage value applied to the semiconductor element with the voltage reference value and switches the logic state according to the magnitude of both values. Means and a switching means for switching the level of the current reference value or the current detection signal value according to the logic state of the comparison signal, and the overload state of the semiconductor element is released based on the protection command, so that various ratings can be obtained. The voltage monitoring means is made to monitor this voltage by utilizing the fact that the voltage applied to the semiconductor element changes substantially in the same manner depending on the degree of the overload condition, and when it exceeds the voltage reference value, the current monitoring means Since the reference value for comparison with the current detection signal is switched by the switching means, even if the semiconductor element has different current ratings or voltage ratings, it is possible to accurately detect the degree of an overload state, for example, an overcurrent state or a short-circuit state. The semiconductor element can be appropriately protected according to the degree of its weight. Since the circuit of the present invention can be commonly used for protection of semiconductor elements of various ratings with the same circuit configuration by appropriately setting the current reference value and the voltage reference value, it is integrated in a small chip or an integrated circuit chip for a drive circuit. The cost of the overload protection circuit used for each semiconductor element forming the bridge circuit or the like can be significantly reduced as compared with the conventional case. It should be noted that the embodiment of the present invention in which a delay unit is provided for a protection command in association with the current monitoring unit and the semiconductor element is protected based on the protection command after the delay is provided in accordance with an overload state for only a very short time. Eliminates the risk of frequent unnecessary and harmful protective actions such as interruption of load current,
By providing the delay means with an appropriate operation time constant or charge / discharge characteristic, it is possible to provide a desired time characteristic for the overload protection operation. Further, as the voltage monitoring means, a voltage dividing means for receiving a predetermined power supply voltage and a diode connected to the voltage dividing point for receiving a voltage applied to the semiconductor element in the opposite direction are used, and the potential at the voltage dividing point of the voltage dividing means is The embodiment of the present invention that derives as the comparison signal has the advantage that the voltage reference value can be easily and accurately set by the voltage dividing ratio of the voltage dividing means with a very simple circuit configuration. Further, an embodiment in which two current reference values are used to cause the switching means to short-circuit or release one of the current reference values so that the current monitoring means switches and gives the sum of the other current reference value and both current reference values. , And two current detection resistors connected in series as the current detection means are used to short-circuit or release one of the current detection resistors by the switching means. There is an advantage that the signal level can be accurately switched.

【図面の簡単な説明】[Brief description of drawings]

【図1】電流基準値を切り換える本発明の実施形態を示
すブロック回路図である。
FIG. 1 is a block circuit diagram showing an embodiment of the present invention for switching a current reference value.

【図2】図1の実施形態に対応する具体回路図である。FIG. 2 is a specific circuit diagram corresponding to the embodiment of FIG.

【図3】電流検出信号値を切り換える本発明の実施形態
を示す回路図である。
FIG. 3 is a circuit diagram showing an embodiment of the present invention that switches a current detection signal value.

【図4】過負荷保護回路の従来例を示す回路図である。FIG. 4 is a circuit diagram showing a conventional example of an overload protection circuit.

【符号の説明】[Explanation of symbols]

1 半導体素子 1a 半導体素子の電流検出用補助エミッタ 3 半導体素子の負荷 4 半導体素子用の駆動回路 5 ブリッジ制御回路 10 電流検出手段 11 電流検出抵抗 11a,11b 2個の電流検出抵抗 20 電流監視手段 21 電流監視手段用のコンパレータ 22 保護指令用の遅延手段 30 電圧監視手段 31 電圧監視手段用のダイオード 32 電圧監視手段用の分圧回路 33 電圧監視手段用のコンパレータ 34 電圧監視手段用の遅延手段 40 切換手段 41 切換手段用のデプリーション形のトランジス
タ 42 切換手段用のエンハンスメント形のトランジ
スタ E 半導体素子の接地端子 Ei 電流監視手段用の電流基準値 Eia,Eib 電流監視手段用の2個の電流基準値 Ev 電圧監視手段用の電圧基準値 i 半導体素子に流れる電流 Sc 比較信号 Si 電流検出信号 So 異常信号 Sp 保護指令 Sw 半導体素子に対するスイッチング指令 To 半導体素子の出力端子 v 半導体素子に掛かる電圧 Vd 分圧回路用の制御電源電圧
1 semiconductor element 1a auxiliary emitter for current detection of semiconductor element 3 load of semiconductor element 4 drive circuit for semiconductor element 5 bridge control circuit 10 current detection means 11 current detection resistors 11a, 11b two current detection resistors 20 current monitoring means 21 Comparator for current monitoring means 22 Delay means for protection command 30 Voltage monitoring means 31 Diode for voltage monitoring means 32 Voltage dividing circuit for voltage monitoring means 33 Comparator for voltage monitoring means 34 Delay means for voltage monitoring means 40 Switching Means 41 Depletion type transistor for switching means 42 Enhancement type transistor for switching means E Ground terminal of semiconductor element Ei Current reference value for current monitoring means Eia, Eib Two current reference values Ev voltage for current monitoring means Voltage reference value for monitoring means i Current flowing in semiconductor element Sc Comparison signal Si Current detection signal So Abnormal signal Sp Protection command Sw Semiconductor element Switching command To the semiconductor element of the output terminal v control power supply voltage of the voltage Vd dividing circuit for acting on the semiconductor element against

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】半導体素子に流れる電流を検出してその電
流値を表す信号値の検出信号を発する電流検出手段と、
電流検出信号の信号値を常時監視してそれが電流基準値
を越えたとき保護指令を発する電流監視手段と、半導体
素子に掛かる電圧値を電圧基準値と比較して両値の大小
に応じて論理状態が変わる比較信号を発する電圧監視手
段と、比較信号がとる論理状態に応じて電流基準値と電
流検出信号値のいずれかのレベルを切り換える切換手段
とを備え、保護指令に基づいて半導体素子を過負荷状態
から解除するようにしたことを特徴とする半導体素子の
過負荷保護回路。
1. A current detection means for detecting a current flowing through a semiconductor element and issuing a detection signal of a signal value representing the current value,
Current monitoring means that constantly monitors the signal value of the current detection signal and issues a protection command when it exceeds the current reference value, and compares the voltage value applied to the semiconductor element with the voltage reference value according to the magnitude of both values. The semiconductor device is provided with a voltage monitoring means for issuing a comparison signal whose logic state changes, and a switching means for switching one of a current reference value and a current detection signal value level according to the logic state of the comparison signal, based on a protection command. An overload protection circuit for a semiconductor device, which is configured to release an overload condition.
【請求項2】請求項1に記載の回路において、切換手段
により電流基準値と電流検出信号値のいずれかのレベル
が電流監視手段に半導体素子の過電流状態と短絡状態と
を区別して検出させるように切り換えられることを特徴
とする半導体素子の過負荷保護回路。
2. The circuit according to claim 1, wherein the level of either the current reference value or the current detection signal value is detected by the switching means by the current monitoring means by distinguishing between the overcurrent state and the short-circuit state of the semiconductor element. An overload protection circuit for a semiconductor device, which is characterized by being switched as follows.
【請求項3】請求項1に記載の回路において、電圧監視
手段として制御電源電圧を受ける分圧手段と,その分圧
点に接続され半導体素子から電圧を逆方向に受けるダイ
オードを用い、分圧手段の分圧点から比較信号を導出す
るようにしたことを特徴とする半導体素子の過負荷保護
回路。
3. The circuit according to claim 1, wherein a voltage dividing means for receiving a control power supply voltage is used as the voltage monitoring means, and a diode connected to the voltage dividing point for receiving the voltage in the reverse direction from the semiconductor element is used. An overload protection circuit for a semiconductor device, wherein a comparison signal is derived from a voltage dividing point of the means.
【請求項4】請求項1に記載の回路において、電流監視
手段に付随して保護指令の遅延手段を設け、遅延後の保
護指令に基づいて半導体素子の過負荷状態を解除するよ
うにしたことを特徴とする半導体素子の過負荷保護回
路。
4. The circuit according to claim 1, wherein a protection command delay means is provided in association with the current monitoring means, and the overloaded state of the semiconductor element is released based on the delayed protection command. An overload protection circuit for semiconductor devices, characterized by:
【請求項5】請求項1に記載の回路において、電流基準
値を2個用いて切換手段により一方の電流基準値を短絡
または釈放することにより、電流監視手段に他方の電流
基準値と両電流基準値の和とを切り換えて付与するよう
にしたことを特徴とする半導体素子の過負荷保護回路。
5. The circuit according to claim 1, wherein two current reference values are used and one of the current reference values is short-circuited or released by the switching means so that the current monitoring means and the other current reference value are supplied. An overload protection circuit for a semiconductor device, characterized in that the sum of reference values is switched and applied.
【請求項6】請求項1に記載の回路において、電流検出
手段として直列接続された2個の電流検出抵抗を用い、
一方の検出抵抗を切換手段により短絡または釈放するよ
うにしたことを特徴とする半導体素子の過負荷保護回
路。
6. The circuit according to claim 1, wherein two current detection resistors connected in series are used as the current detection means,
An overload protection circuit for a semiconductor device, characterized in that one detection resistor is short-circuited or released by a switching means.
JP04784396A 1996-03-06 1996-03-06 Semiconductor element overload protection circuit Expired - Lifetime JP3191661B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04784396A JP3191661B2 (en) 1996-03-06 1996-03-06 Semiconductor element overload protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04784396A JP3191661B2 (en) 1996-03-06 1996-03-06 Semiconductor element overload protection circuit

Publications (2)

Publication Number Publication Date
JPH09246931A true JPH09246931A (en) 1997-09-19
JP3191661B2 JP3191661B2 (en) 2001-07-23

Family

ID=12786659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04784396A Expired - Lifetime JP3191661B2 (en) 1996-03-06 1996-03-06 Semiconductor element overload protection circuit

Country Status (1)

Country Link
JP (1) JP3191661B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000139071A (en) * 1998-11-02 2000-05-16 Fuji Electric Co Ltd Gate driving circuit for power converter
JP2013118756A (en) * 2011-12-02 2013-06-13 Aisin Seiki Co Ltd Driving device of power switching element
JP2014216756A (en) * 2013-04-24 2014-11-17 ニチコン株式会社 Overcurrent detection device
JP2019187172A (en) * 2018-04-16 2019-10-24 株式会社デンソー Drive circuit of switch
US11563371B2 (en) 2019-12-02 2023-01-24 Fuji Electric Co., Ltd. Switching control circuit and power supply circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000139071A (en) * 1998-11-02 2000-05-16 Fuji Electric Co Ltd Gate driving circuit for power converter
JP2013118756A (en) * 2011-12-02 2013-06-13 Aisin Seiki Co Ltd Driving device of power switching element
JP2014216756A (en) * 2013-04-24 2014-11-17 ニチコン株式会社 Overcurrent detection device
JP2019187172A (en) * 2018-04-16 2019-10-24 株式会社デンソー Drive circuit of switch
US11563371B2 (en) 2019-12-02 2023-01-24 Fuji Electric Co., Ltd. Switching control circuit and power supply circuit

Also Published As

Publication number Publication date
JP3191661B2 (en) 2001-07-23

Similar Documents

Publication Publication Date Title
US5200878A (en) Drive circuit for current sense igbt
US5138515A (en) Pulse-controlled gate circuit with protection against short-circuit
US7405916B2 (en) Control apparatus of semiconductor switch
JP2669117B2 (en) Drive circuit for voltage-driven semiconductor devices
KR100777884B1 (en) A charge/discharge control circuit and a charging-type power-supply unit
US11545970B2 (en) Current detection circuit, current detection method, and semiconductor module
US4432032A (en) Auxiliary voltage snubber circuit
US6320359B1 (en) DC-DC converter and controller for detecting a malfunction therein
US7265958B2 (en) Overcurrent protection circuit and semiconductor apparatus
JPH0620348B2 (en) Method and apparatus for sensing a short circuit in a motor control circuit
JP2002281737A (en) Igbt series connection type gate drive circuit
US11581886B2 (en) Current detection circuit, current detection method, and semiconductor module
JPH06209592A (en) Circuit configuration feeding inductive load
JPH09246931A (en) Overload protective circuit for semiconductor device
JPH1198835A (en) H-bridge step-up circuit
KR100807547B1 (en) A drive circuit of a semiconductor switch for an inverter
JP3240489B2 (en) IGBT overcurrent protection device and IGBT protection device
JPS5826572A (en) Controlling device
JPH08321756A (en) Semiconductor device drive circuit
JP4900321B2 (en) Overcurrent protection circuit
JPH10336876A (en) Current breaker
JP6566261B2 (en) Earth leakage breaker
EP1011186A2 (en) Electric load management circuit
US20240103093A1 (en) Aircraft solid state power controller and method of testing an aircraft solid state power controller
JPH07336872A (en) Pulse generator

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080525

Year of fee payment: 7

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080525

Year of fee payment: 7

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090525

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090525

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100525

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100525

Year of fee payment: 9

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100525

Year of fee payment: 9

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110525

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110525

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120525

Year of fee payment: 11

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120525

Year of fee payment: 11

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120525

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130525

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130525

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140525

Year of fee payment: 13

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term