JPH09244585A - Level shifter circuit with latch function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shifter circuit in which the driving capacity is high, smaller number of transistors is used to constitute the circuit and the number of rows is reduced in the layout of the driver ICs of a liquid crystal display device. SOLUTION: When a clock signal ϕ is '1' (an inverted clock signal *ϕis '0', the digital signals of a voltage VH system, which are made by inverting the digital signals of a voltage VL (for example, 3 volts) system being inputted to the gate of an Nch field effect transistor(FET) 1, are inputted to a three state inverter 10a and the inverter 10a inverts and outputs the inputted signals. Moreover, when the signal ϕ is '0', the inverter 10a is put in a high impedance state and the signals ϕ keep the output state the same as the state immediately before the signal ϕ becomes '0' by the loop which is formed by an inverter 20 and a three state inverter 10b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit with a latch function suitable for use in a driver IC for driving a TFT (thin film transistor) of a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, there has been a TFT driving method as a driving method for a liquid crystal display device. The TFT driving method has the characteristics of high gradation display quality, excellent screen brightness and contrast, and high display image quality. It is also excellent in performance other than image quality such as fast response speed and wide viewing angle. The principle of this TFT driving method will be described with reference to FIG. In the figure, reference numeral 50 is a thin film transistor, and when a voltage is input from the outside through a source line 51 and a voltage is applied to the gate line 52, the voltage input to the source line 51 is applied to the liquid crystal layer 53. As a result, the liquid crystal molecules of the liquid crystal layer 53 change the angle and allow light from a backlight or the like to pass through. In addition, the gradation is displayed with the source line 5
This is performed by changing the voltage input to 1 and controlling the angle of the liquid crystal molecules of the liquid crystal layer 53.

In general, a liquid crystal display has a large number of circuits shown in FIG. 10 in a matrix (for example, VGA (video grap).
In the case of hics array), it is configured by arranging 640 × 480 pieces). In such a liquid crystal display, a driver IC for driving a TFT (hereinafter simply referred to as a driver IC) is used to apply a voltage based on image data to the thin film transistors in each row, and the thin film transistors are sequentially turned on for each row. By doing so, the image is displayed.

In the above-mentioned driver IC, conventionally, a voltage is applied to each thin film transistor of a liquid crystal display based on a data latch unit that holds digital data for gradation control input from the outside and the input digital data. Circuits such as a driver unit are included. In the data latch section, another digital IC whose drive voltage is lowered from 5V in the related art to 3V in order to reduce power consumption.
The drive voltage is set to 3V in order to match the above. Further, in the driver section, a higher voltage is required to improve the response characteristics of the liquid crystal display device, that is, to change the angle of the liquid crystal molecules in a very short time. Voltage is used. As described above, in the driver IC, circuits that are driven by different voltages are mixed in one IC. Therefore, a level shift unit that boosts a 3V system signal output from the data latch unit to a 5V system signal is provided. There is.

Here, FIG. 11 shows a circuit configuration of a conventional data latch section and level shift section. In this figure, 6
Reference numeral 0 is a data latch unit, and 70 is a level shift unit. In addition, the data latch unit 60 includes P-channel or N-channel field effect transistors (hereinafter, P
chFET, NchFET) and circuits 61a and 61b and a circuit 62. The circuit 61a includes PchFETs 611 and 61 connected in series.
2 and NchFETs 613 and 614, PchFE
A voltage of 3V is applied to the source of T611, and NchF
The source of ET614 is grounded.

A clock signal φ, which is a digital signal (hereinafter referred to as a 3V system digital signal) representing "1" at a voltage of 3V and "0" at a ground potential, is input to the gate of the NchFET 614. . Also, PchFE
An inverted clock signal * φ (3V system) obtained by inverting the clock signal φ is input to the gate of T611. Further, the gates of the PchFET 612 and the NchFET 613 are externally supplied with a digital data bit signal D (3V).
System) is input, and the connection point a between the drain of the PchFET 612 and the drain of the NchFET 613 is the circuit 62.
Are connected to the gates of the PchFET 621 and NchFET 622 and the gate of the NchFET 702 of the level shift unit 70, respectively.

The circuit 62 is a PchFE connected in series.
It consists of T621 and NchFET622, and PchFET
A voltage of 3V is applied to the source of the 621, and NchFE
The source of T622 is grounded. Also, PchFE
The connection point C between the drain of T621 and the drain of NchFET 622 is PchFET 612 and N of circuit 61b.
The gate of the chFET 613 and the N of the level shift unit 70
Each of them is connected to the gate of the chFET 701.

The circuit 61b has the same configuration as the circuit 61a, but the clock signal φ is input to the gate of the PchFET 611, and the inverted clock signal * φ is the NchFET 6.
It is input to 14 gates. In addition, PchFET6
The connection point B between the drain of 12 and the drain of NchFET 613 is the PchFET 621 and NchF of the circuit 62.
It is connected to the gate of ET622.

In the circuit 61a described above, for example, the clock signal φ is "0", that is, the inverted clock signal *.
When φ is “1”, PchFET 611 and NchFET6
Both 14 are turned off, and the output is in a high impedance state. On the other hand, the clock signal φ is “1”, that is,
When the inverted clock signal * φ is "0", PchFET61
Both 1 and NchFET 614 are turned on, and when "0" is input to the gates of PchFET 612 and NchFET 613 in this state, PchFET 612 turns on and Nc.
The hFET 613 is turned off, and the voltage 61 V is output from the circuit 61 a, that is, the digital signal “1” of 3 V system is output. In addition, PchFET 612 and NchFET 61
When "1" is input to the gate of PchFET612
Turns off, NchFET 613 turns on, and circuit 6
The ground potential, that is, "0" of a 3V digital signal is output from 1a.

As described above, the circuit 61a can be said to be a kind of three-state inverter that functions as an inverter when the clock signal φ is "1" and has a high impedance output when it is "0". In addition, the circuit 6
It can be said that 1b functions as an inverter when the clock signal is "0", and its output is in a high impedance state when the clock signal is "1". And circuit 6
When 2 is input to the gates of PchFET 621 and NchFET 622, PchFET 621 becomes OF
The F and Nch FETs 622 are turned on, and the ground potential, that is, "0" is output from the circuit 61a. Also, "0"
Is input, PchFET 621 turns on, NchFE
T622 is turned off and the voltage from the circuit 61a is 3V.
That is, "1" is output. Therefore, the circuit 62 functions as an inverter.

On the other hand, the level shift section 70 uses the NchFE
It is configured by T701 and 702 and PchFETs 703 and 704. A voltage of 5V is applied to the sources of the PchFETs 703 and 704, and
The sources of 701 and 702 are grounded. The drains of the NchFET 701 and the PchFET 703 are connected to each other, and the connection point is also connected to the gate of the PchFET 704. Also, NchFET 702
And the drains of the PchFET 704 are also connected to each other, and the connection point is connected to the gate of the PchFET 703. Furthermore, the drain of the NchFET 702 and the PchFE
The connection point of the drain of T704 is connected to a driver unit (not shown).

In the operation of the circuit of FIG. 11 described above, first, in the data latch unit 60, when the clock signal φ is "1" and the inverted clock signal * φ is "0", the circuit 61
The output of b becomes a high impedance state, while the circuit 61a becomes movable and the digital signal D input from the outside is inverted to output the signal * D to the gate of the NchFET 702 of the level shift unit 70 and the circuit. To 62. In addition, the circuit 62 has an inverted digital signal * D
Is further inverted to the NchFET 7 of the level shift unit 70.
Output to the gate of 01.

For example, when the digital signal D input to the circuit 61a is "1", Nc of the level shift unit 70 is
The gate of hFET702 is "0", and NchF is also
“1” is input to the gate of the ET 701. As a result, the NchFET 701 turns on, and the NchFET 7
Since 02 is turned off, the PchFET 704 is turned on, and the digital signal “1” (voltage 5V) of 5V system is output to the driver unit (not shown).

On the other hand, when the digital signal D is "0", "1" is input to the gate of the NchFET 702 of the level shift section 70 and "0" is input to the gate of the NchFET 701. By this, NchFET701
Turns off, NchFET 702 turns on, and PchF
The ET 703 is turned on and outputs "1" to the gate of the PchFET 704. Therefore, PchFET 704
Is turned off, and the NchFET 702 is turned off at this time.
Since it is N, 5V is applied to the driver unit (not shown).
"0" (ground potential) of the system digital signal is output.

Next, when the clock signal φ becomes "0" and the inverted clock signal * φ becomes "1", the output of the circuit 61a goes into a high impedance state and the circuit 61b goes into a movable state. The output signal is held by the loop formed by the circuit 61b and the circuit 62, so that the voltage output from the level shift unit 70 has the clock signal φ of “1” and the inverted clock signal *. It is held until φ becomes “0”. As described above, the circuit of FIG. 11 boosts a 3V digital signal input from the outside to a 5V digital signal, and
The output state is maintained according to the clock signal φ.

Here, the above-mentioned driver IC is, for example, C
-MOS (complementary metal oxide semiconducto
In the case of actually forming an IC according to r), the layout of the IC chip is as shown in FIG. 12, a circuit array (hereinafter referred to as 3V system row) 80 in which circuits driven by a voltage of 3V are arranged in a line, Circuit row in which circuits driven by a voltage of 5V are arranged in a row (hereinafter referred to as 5V system row) 90
You need two types of rows. As an example, in this figure, the width of each row has a length of about 80 μm, and the rows are formed with a spacing of about 40 μm.

FIG. 13 shows a detailed layout of the above-mentioned row. In this figure, FIG.
7 shows a layout of the circuit 62 of the data latch unit 60 of FIG. In this figure, 81 is a 3V power supply line, and 82 is a PchFET (PchFET 621 in FIG. 11).
, 83 is an NchFET (NchFET of FIG. 11)
(Corresponding to 622), 84 is an input line of the circuit 62, 85 is an output line of the circuit 62, and 86 is a ground line. The power supply line 81 and the ground line 86 are shown in FIG.
The circuit extends in the left-right direction, and another circuit of the data latch unit 60 of FIG. 11 is formed between the power supply line 81 and the ground line 86.

An IC in which each of the circuits described above is formed
After the chip is mounted on the lead frame, it is resin-sealed, mounted on the TAB tape, or directly mounted on the glass plate of the liquid crystal display device, and the driver I
Used as C. Further, as shown in FIG. 14, generally, the driver ICs 95 are mounted in a line in the X direction in the figure at the frame portion (hatched portion in the figure) of the liquid crystal display device main body 100.

[0019]

By the way, today, the miniaturization of the main body of the liquid crystal display device is strongly desired in portable electronic equipment typified by a notebook personal computer. The length of the frame portion of the liquid crystal display device main body 100 shown in FIG. 14 in the Y direction is made as short as possible, and the driver IC 95 is set to the liquid crystal display portion 11
It is necessary to make the width of the frame portion of the liquid crystal display device main body 100 as narrow as possible by arranging it without greatly exceeding the width of 0 (length in the X direction).

In particular, in order to shorten the length of the frame portion in the Y direction, it is necessary to make the dimension of the driver IC chip corresponding to the Y direction as short as possible.
As shown in FIG. 5, the IC chip 96 of the driver IC is formed into a horizontally long rectangle, and the rows 80 and 90 described above are integrated into the IC.
The driver IC 95 is mounted on the frame portion of the liquid crystal display device main body 100 so that the chip 96 is laid out in the lateral direction and the longitudinal direction of the IC chip 96 is the X direction in FIG.

Therefore, by reducing the number of rows formed in the widthwise direction of the IC chip 96, the Y direction of the frame portion of the liquid crystal display device main body 100 can be shortened. For example, as shown in FIG. In the layout, the length of the frame portion in the Y direction is inevitably long. Further, in order to reduce the size of the IC chip, it is important to have as many functions as one circuit and to reduce the number of transistors formed in the IC chip. In particular, reduction of the number of transistors simplifies the manufacturing process. , Yield improvement,
Effects other than miniaturization of the liquid crystal display device body, such as low power consumption, can be expected. Further, the level shift unit 70 shown in FIG.
However, due to its circuit configuration, the output impedance was high, and the driving ability for the circuit in the next stage was low.

The present invention has been made in view of such circumstances, and not only can it be configured with a transistor having a high drive capability and a smaller number of transistors,
It is an object of the present invention to provide a level shifter circuit with a latch function that can reduce the number of rows in the layout of a driver IC of a liquid crystal display device.

[0023]

According to the first aspect of the present invention,
When a control signal which is a binary digital signal is input and the control signal is at a high level, the first level digital signal input from the outside is converted into a second level digital signal which is a level higher than the first level. When the control signal is inputted to the level converting means for converting and outputting and the control signal is at the high level, the logic of the second level digital signal outputted from the level converting means is inverted and outputted to the outside. First
Logic inversion means, second logic inversion means for inverting the second level digital signal output from the first logic inversion means, and the control signal being input, and when the control signal is at a low level, A level shifter circuit with a latch function, comprising: a third logic inverting means for outputting the second level digital signal output from the second logic inverting means to the output of the first logic inverting means. is there. In addition,
Correspondence between the operations of the level conversion means, the first logic inversion means, and the third logic conversion means described above and the level (low level or high level) of the control signal may be inverted.

According to a second aspect of the present invention, the level conversion means includes a first N-channel field effect transistor having a gate to which the control signal is input and a source grounded, and the first N-channel field effect transistor. A second N-channel field effect transistor having a source connected to the drain of the transistor and a gate to which the first level digital signal is input; and a drain connected to the drain of the second N-channel field effect transistor. A P-channel field effect transistor having a grounded gate and a source to which the same voltage value as the high level of the second level digital signal is applied, the drain of the second N channel field effect transistor and the P-channel field effect transistor. The connection point with the drain of the channel field effect transistor is connected to the input of the first logic inverting means. It is, and the first, second N
Channel field effect transistor and P-channel FET
The voltage at the connection point when the switch is turned on is VA = VH {(RN1 + RN2) / (RP + RN1 + RN2)} <
Vth (where VA is the voltage at the connection point when the first and second N-channel field effect transistors and the P-channel FET are turned on, VH is the high level voltage of the second level digital signal, and RN1 Is the on-resistance of the first N-channel field effect transistor, RN2 is the on-resistance of the second N-channel field effect transistor, and RP is the P-channel F
2. The level shifter circuit with a latch function according to claim 1, wherein the on-resistance of ET, Vth satisfies the condition of (input threshold voltage of the first logic inverting means).

According to a third aspect of the present invention, in the level shifter circuit with a latch function according to the first aspect, the level conversion means has a first N-channel electric field having a gate to which the control signal is input and a source grounded. An effect transistor, a second N-channel field effect transistor having a source connected to the drain of the first N-channel field effect transistor and a gate to which the first level digital signal is input; and the second N-channel field effect transistor. A P-channel field effect transistor having a drain connected to the drain of the channel field effect transistor, a gate to which the control signal is input, and a source to which the same voltage value as the high level of the second level digital signal is applied. And the drain of the second N-channel field effect transistor and the P-channel field effect transistor. Wherein the connection point between the drain of the transistor is connected to the input of the first logic inversion means.

According to a fourth aspect of the invention, in the level shifter circuit with a latch function according to the third aspect, the gate connected to the output of the first logic inverting means and the high level of the digital signal of the second level are the same. It comprises a P-channel field effect transistor having a source to which a voltage value is applied and a drain connected to the input of the first logic inverting means.

The invention according to claim 5 is the invention according to claims 2 to 4.
In the level shifter circuit with a latch function according to any one of the above, a plurality of the first level digital signals are input instead of the second N-channel field effect transistor, and the plurality of first level digital signals are input. It is characterized by comprising a logic circuit which is turned on when the state of 1 satisfies a predetermined condition.

According to a sixth aspect of the present invention, in the level shifter circuit with a latch function according to the fifth aspect, the logic circuit is composed of third and fourth N-channel electric field transistors. ON when the source is connected to the drain of the fourth N-channel field-effect transistor and the two first-level digital signals input to the gates of the third and fourth N-channel field-effect transistors are both at high level. It is characterized in that

According to the seventh aspect of the invention, the 3-bit digital data of the first level is decoded, the decoding result is converted into the digital signal of the second level which is higher than the first level, and the digital signal is output. A level shifter circuit with a latch function according to claim 2, and a decoder for holding the decoding result according to a control signal input from the outside, and the level shifter circuit according to any one of claims 1 to 4.
The level shifter circuit with a latch function according to claim 1, and one input terminal and two output terminals, and the one of the one based on a second level digital signal output from the level shifter circuit with a latch function according to claim 2. Switching means for outputting a signal input to an input terminal from any one of two output terminals, which corresponds to each of the level shifter circuits with a latch function according to the first to fourth aspects. The first to fourth switching means provided for the second N-channel electric field transistor of the level shifter circuit with a latch function according to claim 2 are provided with the least significant bit of the 3-bit digital data. The level shifter circuit with a latch function according to the first aspect of the present invention receives the 3 bits at the respective gates of the third and fourth N-channel electric field transistors. An inversion signal of the second bit of digital data and an inversion signal of the most significant bit are input to each gate of the third and fourth N-channel electric field transistors of the level shifter circuit with a latch function according to the second aspect. Is a signal of the second bit of the 3-bit digital data,
An inverted signal of the most significant bit is input, and the third and fourth level shifter circuits with a latch function according to the third aspect are provided.
7. The gate of the N-channel electric field transistor of, the inversion signal of the second bit of the 3-bit digital data and the signal of the most significant bit are input, and the fourth level shifter circuit with a latch function according to claim 6 is configured. The decoder is characterized in that the second bit signal of the 3-bit digital data and the most significant bit signal are inputted to the respective gates of the third and fourth N-channel electric field transistors.

[0030]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a level shifter circuit with a latch function according to the first embodiment. In this figure, 1,
Reference numeral 2 denotes an NchFET, and a first level voltage VL (for example, 3V) digital signal DL inputted from the outside is inputted to the gate of the NchFET 1. Also,
The source of NchFET1 is connected to the drain of NchFET2, and the source of NchFET2 is grounded.
The clock signal φ of the voltage VL system is input to the gate of the NchFET 2.

A PchFET 3 has a source to which a voltage VH (for example, 5V) is applied, and a drain connected to the drain of the NchFET 1. And
Since the gate of PchFET3 is grounded, PchFET3
FET3 is always on. Where Pc
Pch so that the potential VA at the connection point A between the drain of hFET3 and the drain of NchFET1 satisfies the following relation:
ON resistance RP of FET3 and O of NchFET1,2
N resistance RN is defined. VA = VH {RN / (RP + RN)} <Vth Here, Vth is an input threshold voltage by which the digital signal input to the next stage circuit can be recognized as "0" (see FIG. 2). . FIG. 2 is a diagram for explaining the relationship between VA and Vth. For the purpose of explanation, the above-mentioned "next stage circuit" FETs 11 to 14 are replaced by an inverter 31, and P
chFET3 is its ON resistance RP, NchFET1,2
Is shown only by its ON resistance RN. Then, the potential VA at the connection point A is RP, so as to satisfy the relationship of the above equation with the input threshold voltage Vth at which the digital signal inputted to the inverter 31 can be recognized as "0".
RN is determined.

Reference numerals 10a and 10b are a kind of three-state inverter having the same structure as the circuit 61a and the circuit 61b of FIG. 11, respectively.
When the clock signal φ is “0” (the inverted clock signal * φ is “1”), the output is in the high impedance state,
When the clock signal φ is “1” (the inverted clock signal * φ is “0”), it functions as an inverter. The 3-state inverter 10b is in a high impedance state when the clock signal φ is "1" and functions as an inverter when the clock signal φ is "0". However, PchFET 12 and NchFE of each 3-state inverter
To the gate of T13, a digital signal of a voltage VH system in which "1" is represented by a voltage VH and "0" is represented by a voltage 0V is input, and the voltage VH is applied to the source of each PchFET 11, and the voltage VH system is applied. The digital signal of is output.

Reference numeral 20 is an inverter having the same configuration as that of the circuit 62 of FIG. 11, which includes a PchFET 21 and an NchF.
A voltage VH system digital signal output from the three-state inverter 10a is input to the gate of the ET22. The voltage VH is applied to the source of the PchFET 21, and a digital signal of the voltage VH system is output. In addition, the drain of PchFET3 and NchFET1
The connection point A with the drain of the three-state inverter 10
The input of a (the gates of PchFET 12 and NchFET 13) is connected, the output of the 3-state inverter 10a (the connection point of the drain of PchFET 12 and the drain of NchFET 13) is connected to the outside, and the input of inverter 20 (PchFET 21 and NchFET 13).
22 gates).

Further, the output of the inverter 20 (PchF
The connection point between the drain of the ET21 and the drain of the NchFET 22) is connected to the input of the 3-state inverter 10b, and the output of the 3-state inverter 10b is connected to the output of the 3-state inverter 10a, the input of the inverter 20, and the outside. . That is, the 3-state inverter 10b and the inverter 20 form a loop on the output side of the 3-state inverter 10a.

Next, the operation of the above-mentioned level shifter circuit with a latch function will be described. First, when the clock signal φ is “1” (the inverted clock signal * φ is “0”), Nc
The hFET2 is turned on, and at this time, when "1" (voltage VL) is input to the gate of the NchFET1, the NchFE
T1 is turned on and the above-mentioned voltage VA is input to the 3-state inverter 10a. When "0" (ground potential) is input to the gate of NchFET1, NchF
ET1 is turned off, and the voltage VH (“1” of the digital signal of the voltage VH system) is input to the 3-state inverter 10a. As described above, the digital signal of the voltage VL system input to the level shifter circuit with the latch function of the present embodiment is output by the NchFETs 1 and 2 and the PchFET 3.
The voltage is boosted to a VH system digital signal. Therefore,
It can be said that the NchFETs 1 and 2 and the PchFET 3 are level shift units of the level shifter circuit with a latch function of this embodiment.

The three-state inverter 10a is
Since the clock signal φ is “1” and the inverted clock signal * φ is “0”, it functions as an inverter. When the voltage VA is input, the voltage VA is supplied to the inverter 20 and the outside.
H (voltage VH system digital signal "1") is output, and when the voltage VH is input, ground potential (voltage VH system digital signal "0") is output. In addition, the inverter 20
Inverts the signal output from the 3-state inverter 10a and outputs the inverted signal to the 3-state inverter 10b. Here, since the clock signal φ is “1” and the inverted clock signal * φ is “0”, the output of the three-state inverter 10b is in a high impedance state. No signals are output at the same time.

From this state, when the clock signal φ changes to “0” (inverted clock signal * φ is “1”), NchFE
T2 is turned off, and the voltage VH is input to the 3-state inverter 10a regardless of the content of the digital signal of the voltage VL system input to the gate of the NchFET 1. Here, the 3-state inverter 10a is the PchFET 11
Since the NchFET 14 and the NchFET 14 are turned off, their outputs are in a high impedance state and the input voltage VH is not inverted and output.

On the other hand, at this time, the 3-state inverter 10b
Functions as an inverter, and clock signal φ is "0"
Immediately before the inverted clock signal * φ turns to “1”, the digital signal output from the inverter 20 is inverted and output to the outside and the inverter 20. As a result, when the clock signal φ is “0”, the 3-state inverter 10
The loop formed by b and the inverter 20 holds the state of the digital signal immediately before the clock signal φ changes to “0” (the inverted clock signal * φ is “1”). Therefore, the three-state inverters 10a and 10b
The inverter 20 and the inverter 20 can be said to be a latch unit of the level shifter circuit with a latch function of the present embodiment.

As described above, in the level shifter circuit with the latch function according to the present embodiment, when the clock signal φ is "1", the input voltage VL system digital signal DL is inputted.
Is boosted to a digital signal of the voltage VH system and output, and when the clock signal φ changes to "0", the state of the output signal immediately before that is held.

Further, since the power supply voltage of the level shifter circuit with a latch function in this embodiment is all the voltage VH, it is possible to integrate the power supply voltages of the circuits of the latch section and the level shift section into one. Since the output impedance of the level shifter circuit with a latch function in this embodiment is lower than that in FIG. 11, the driving capability is improved, and the number of transistors forming the level shifter circuit with a latch function in this embodiment is further increased. Is 13 and the number of transistors can be reduced as compared with the circuit of FIG.

[Second Embodiment] FIG. 3 shows a level shifter circuit with a latch function according to a second embodiment. In this figure, parts corresponding to the respective parts of the level shifter circuit with a latch function shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Here, the 3-state inverter 10
Although the components a and 10b and the internal components of the inverter 20 are omitted in the figure, they have the same components as those in FIG. That is, in FIG. 3, for example, the clock signal φ and the inverted clock signal * φ are both actually input to the 3-state inverter 10a, but the 3-state inverter 10a functions as an inverter when the clock signal φ is "1". Therefore, only the clock signal φ is shown in the figure. Further, for the same reason as this, only the inverted clock signal * φ is described in the 3-state inverter 10b. Here, the level shifter circuit with a latch function shown in FIG. 3 is different from that of FIG. 1 in that the clock signal φ is also input to the gate of the PchFET 3.

The operation of the level shifter circuit with a latch function in this embodiment will be described below. First, when the clock signal φ is "0", the NchFET2 is OFF,
The PchFET 3 is turned on and the voltage VH is input to the 3-state inverter 10a. At this time, the stray capacitance C existing between the point A in the figure and the 3-state inverter 10a
Is charged. Then, when the clock signal φ becomes “1”, the NchFET 2 is turned on and the PchFET 3 is turned off.
It becomes F.

At this time, "1" is applied to the gate of NchFET1.
Is input, the NchFET 1 is turned on, the electric charge charged in the floating capacitance C is discharged through the NchFETs 1 and 2, and "0" is input to the 3-state inverter 10a. Further, when "0" is input to the gate of the NchFET1 and the NchFET1 is turned off, the electric charge charged in the floating capacitance C is stored in the 3-state inverter 10a.
, That is, "1" is input to the 3-state inverter 10a.

The operation thereafter is the same as in the first embodiment, when the clock signal φ is "1", the 3-state inverter 10a is operated.
The digital signal of the voltage VH system input to is inverted and output to the outside and the inverter 20. When the clock signal φ changes to “0”, the state of the output signal immediately before that is held. According to the level shifter circuit with the latch function of the present embodiment, the NchFET 2 and the PchFET 3 are alternately turned on and off in accordance with the clock signal φ, so that when both the NchFETs 1 and 2 are turned on as in the first embodiment, the current flows. It does not flow through the PchFET 3 and the NchFETs 1 and 2, so that the current consumption in the level shift section can be greatly reduced.
Also in the present embodiment, as in the first embodiment,
Since the output impedance can be lowered, the driving ability for the circuit at the next stage is improved. Since the power supply voltage of the level shifter circuit with the latch function is all VH, the power supply voltages of the circuits of the latch section and the level shift section can be integrated into one, and the row can be integrated into one system. Further, the number of transistors forming the level shifter circuit with a latch function in this embodiment is 13, and it is possible to reduce the number of transistors by 3 compared with the circuit of FIG.

[Third Embodiment] FIG. 4 shows a level shifter circuit with a latch function according to a third embodiment. In this figure, parts corresponding to the respective parts of the level shifter circuit with a latch function shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. 4 is different from the level shifter circuit with a latch function of FIG. 3 in that a PchFET 4 is added. The gate of this PchFET4 is 3
It is connected to each output of the state inverters 10a and 10b, and its drain is connected to the input of the three-state inverter 10a. The voltage VH is applied to the source.

Here, in the above-described second embodiment,
When “0” is input to the gate of the NchFET 1 when the clock signal φ is “1”, the electric charge charged in the floating capacitance C is applied to the 3-state inverter 10a, whereby the “1” is applied to the 3-state inverter 10a. It has already been described that "" is input, but at that time, there is a possibility that the electric charge stored in the floating capacitance may be discharged due to some factor. In such a case, it becomes impossible to continue supplying the accurate voltage (here, 5V) representing "1" to the 3-state inverter 10a, and there is a possibility that it does not operate normally. In order to avoid such a situation, the PchFET 4 added in the third embodiment compensates the voltage "1" of the voltage VH system digital signal input to the 3-state inverter 10a.

The operation of the level shifter circuit with a latch function in this embodiment will be described below. First, when the clock signal φ is “0”, the NchFET 2 is turned off and P
The chFET 3 is turned on and the stray capacitance C is charged. Then, the clock signal φ becomes “1”, and N
When "0" is input to the gate of the chFET1, the electric charge charged in the floating capacitance C is applied to the 3-state inverter 10a, whereby "1" is input. At this time, 3
Since the state inverter 10a outputs "0",
The PchFET 4 is turned on and the voltage VH is input to the 3-state inverter 10a.

Therefore, from this point on, while the clock signal φ is "1" and "0" is being input to the gate of the NchFET 1, the PchFET 4 is fixed in the ON state and the voltage is applied to the input of the 3-state inverter 10a. "1" of VH system digital signal is continuously input stably. When the clock signal φ is “0”, the output state immediately before the clock signal φ becomes “0” is held by the loop including the 3-state inverter 10b and the inverter 20. Therefore, even if the discharge path of the stray capacitance C exists for some reason, the 3-state inverter 10a can operate stably. Also in the present embodiment, the driving capability for the circuit of the next stage is improved, the power supply voltages of the circuits of the latch section and the level shift section can be integrated into one, and the row can be unified. The point that the number of transistors can be reduced has the same effect as the first and second embodiments.

[Fourth Embodiment] FIG. 5 shows a level shifter circuit with a latch function according to a fourth embodiment. In this figure, parts corresponding to the respective parts of the level shifter circuit with a latch function shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted. 5 is different from the level shifter circuit with a latch function of FIG. 4 in that a logic circuit 5 is added instead of the NchFET 1. Various circuits are conceivable as the logic circuit 5, but in any case, only when the states of the digital signals DL1 to DLn of the voltage VL system inputted from the outside satisfy the conditions given to the logic circuit 5, 5 is turned on.

6 to 8 show specific embodiments of the logic circuit 5 described above. FIG. 6 shows the above-mentioned logic circuit 5 including the input digital signals DL1 to DL1 of the voltage VL.
NchFE so that it is turned on when DLn is all "1"
This is a form in which the circuit 6 in which the drains and sources of T6-1 to 6-n are connected to each other is used, and the logic circuit 6 is a kind of AND.
Operates like a gate.

That is, when the clock signal φ is "1",
When "1" is input to all the gates of the NchFETs 6-1 to 6-n, "0" is input to the 3-state inverter 10a.
Is input, and the output digital signal DH becomes "1". At this time, if "0" is input to any one of the gates of the NchFETs 6-1 to 6-n, "1" is input to the 3-state inverter 10a and the digital signal DH is output. Becomes "0". Furthermore, since "0" is input to the gate of PchFET4 at this time,
The voltage VH is applied to the input of the 3-state inverter 10a to compensate for "1" of the voltage VH system digital signal.

It is needless to say that the level shifter circuit with a latch function shown in FIG. 6 can be applied to the level shifter circuit with a latch function of the second embodiment (which does not include the PchFET 4) as shown in FIG. Yes.

Next, another specific embodiment of the logic circuit 5 described above is shown in FIG. In this figure, 7 is 4 Nc
This is a logic circuit composed of hFETs 7-1 to 7-4 and operating as an exclusive OR. In this logic circuit 7, the source of NchFET 7-1 and NchFE
The drain of T7-2, and the source of NchFET7-3 and the drain of NchFET7-4 are connected to each other. In addition, NchFET7-1 and Nch
The drains of FET7-3 are connected to each other, and PchFET
It is connected to the drain of 3 and the input of the 3-state inverter 10a. In addition, NchFET7-2 and NchF
The sources of ET7-4 are connected to each other and to the drain of NchFET2.

Then, NchFET 7-1 and NchFE
The gate of T7-3 has a digital signal DLa of voltage VL system.
And its inverted signal * DLa are input respectively, and Nch
The gates of the FET 7-2 and NchFET 7-4 are respectively supplied with the digital signal DLb of the voltage VL system and its inverted signal * DLb. In such a logic circuit 7, when the clock signal φ is “1”, for example, the digital signal DLa is “0” (* DLa is “1”) and the digital signal DLb is “1”.
(* DLb is "0"), NchFET7-
Both 3 and 7-4 are turned off, but NchFET 7-1
, 7-2 are both turned on. Therefore, "0" is input to the 3-state inverter 10a and the digital signal DH of the voltage VH system output to the outside becomes "1".

When the clock signal φ changes to "0" from this state, the three-state inverter 10a is in a high impedance state and the three-state inverter 10b is in a movable state, so that it is formed by the inverter 20 and the three-state inverter 10b. The digital signal DH output to the outside by the loop is kept as "1". Further, even when the digital signal DLa is "1" (* DLa is "0") and the digital signal DLb is "0" (* DLb is "1"), the NchFETs 7-3 and 7-4 are used.
Are both ON, and NchFETs 7-1 and 7-2 are both OFF
Then, the same operation as described above is performed.

On the other hand, when the clock signal φ is "1", for example, both digital signals DLa and DLb are "0" (* DLa,
* If both DLb are "1"), NchFET7
-1 is ON, NchFET7-2 is OFF, NchFET7-3 is OFF, NchFET7-4
Is turned on, and the electric charge charged in the floating capacitance C is applied to the 3-state inverter 10a, that is, "1".
Is entered. As a result, the voltage VH output to the outside
The digital signal DH of the system becomes "0". Further, when the clock signal φ changes to "0" from this state, the 3-state inverter 10a becomes a high impedance state, and the digital signal DH output to the outside is generated by the loop formed by the inverter 20 and the 3-state inverter 10b. It is held as "0".

When the digital signals DLa and DLb are both "1" (* DLa and * DLb are both "0"), the clock signal φ is "1" (that is, the inverted clock signal * φ is "0"). When it becomes, the same operation as described above is performed. In summary, when both the digital signals DLa and DLb of the voltage VL system are "0" or "1", the digital signal DH of the voltage VH system output to the outside is "0",
Digital signal DLa is "0", DLb is "1", or
When the digital signal DLa is "1" and the DLb is "0", the digital signal DH is "1". As described above, in the level shifter circuit with the latch function shown in FIG. 8, the logic circuit 7 inputs the digital signals DLa and DLb of the voltage VL system.
Is exclusive-ORed and the result is boosted and held in accordance with the clock signal φ.

In the level shifter circuit with the latch function of FIG. 8 as well, the clock signal φ is "1" and the logic circuit 7
3 state inverter 10 when is turned off
For the purpose of compensating the state of "1" of the digital signal of the voltage VL system input to a, the PchFET 4 may be added as in the case of FIG.

As described above, according to the level shifter circuit with the latch function in the present embodiment, the level shifter circuit with the latch function shown in FIG.
Since more functions can be added, a multifunctional level shifter circuit can be configured with fewer transistors, and thus the driver IC chip of the liquid crystal display device can be further downsized.

[Fifth Embodiment] FIG. 9 shows a circuit of the present embodiment. In the present embodiment, a case will be described in which a 3-input-8-output decoder circuit is configured using the level shifter circuit with a latch function described above. In FIG. 9, 40 is the same circuit as the level shifter circuit with a latch function of FIG. 1 described in the first embodiment, and the gate of the NchFET 1 has the first bit (least significant bit) of the 3-bit digital data of the voltage VL system. D0 has been entered. Also, Nch
The clock signal φ is input to the gate of the FET2.

41a to 41d are level shifter circuits with a latch function which are substantially similar to the level shifter circuit 40 with a latch function, except that an NchFET 8 is added between NchFET1 and NchFET2. That is, the drain of the NchFET 8 is NchFE
It is connected to the source of T1 and the source of NchFET8 is N
It is connected to the drain of chFET2. Here, in FIG. 9, the internal structure of only the level shifter circuit 41a with a latch function is shown, but the level shifter circuits 41b to 41d with a latch function also have the same structure.

The gate of the NchFET 1 of the level shifter circuit 41a with the latch function is connected to the signal line 32 outputting the inverted signal * DL1 of the second bit DL1 inverted by the inverter 9b, and the gate of the NchFET 8 is connected by the inverter 9a. It is connected to the signal line 30 which outputs the inverted signal * DL2 of the inverted third bit (most significant bit) DL2. The gate of the NchFET 1 of the level shifter circuit 41b with a latch function is connected to the signal line 33 from which the second bit DL1 is output,
The gate of the NchFET 8 is connected to the signal line 30.

The gate of the NchFET 1 of the level shifter circuit 41c with a latch function is connected to the signal line 33, and the gate of the NchFET 8 is connected to the signal line 31 to which the third bit DL2 is output. The gate of the NchFET 1 of the level shifter circuit 41d with a latch function is connected to the signal line 32, and the gate of the NchFET 8 is connected to the signal line 30. Further, each Nc of the level shifter circuits 41a to 41d with a latch function is
The clock signal φ is input to the gate of the hFET2.

Reference numerals 42a to 42d are switching circuits, and since they have the same configuration, only the configuration of the switching circuit 42a is shown. 25a and 26a are NchF, respectively
ET and PchFET, the drain of the NchFET 25a and the source of the PchFET 26a are connected to each other,
It is connected to the 3-state inverter 10a of the level shifter circuit 41a with a latch function. Also, NchFET
The source of 25a and the drain of the PchFET 26a are also connected to each other, and the decode signal SH1 is output from the connection point a1.

The gate of the NchFET 25a is
Inverter 20 of level shifter circuit 40 with latch function
, And the gate of the PchFET 26a is connected to the output of the inverter 27a whose input is connected to the output of the inverter 20 of the level shifter circuit 40 with a latch function. 28a is an NchFET, and its drain is the source of the NchFET 25a and the PchFET 26.
It is connected to the connection point of the drain of a. The source is grounded and the gate is connected to the output of the 3-state inverter 10a of the level shifter circuit 40 with a latch function.

In addition, NchFET 25b, PchFET
26b, the inverter 27b, and the NchFET 28b also have the same connection relationship as the NchFET 25a, the PchFET 26a, the inverter 27a, and the NchFET 28a described above, but the following points are different. That is, the gate of the NchFET 25b and the input of the inverter 27b are respectively connected to the level shifter circuit 40 with a latch function.
Connected to the output of the 3-state inverter 10a
The gate of the hFET 28b is connected to the output of the inverter 20 of the level shifter circuit 40 with a latch function. In addition, the source of the NchFET 25b and the PchFET 26b
The decode signal SH2 is output from the connection point b1 of the drain of the.

Further, switching circuits 42b to 42 (not shown)
d, the level shifter circuit 40 with a latch function, and
The corresponding level shifter circuits 41b with latch function
The connection relationship with 41d is similar to the connection relationship between the switching circuit 42a and the level shifter circuits with latch function 40 and 41a described above. Here, the switching circuit 4 corresponding to the connection points a1 and b1 in the switching circuit 42a.
The connection points in 2b to 42d are respectively a2 to a4 and b.
2 to b4, connection points a2 to a4, b2 to b4,
Table 1 shows the relationship between the decode signals output from each connection point.
become that way.

[Table 1]

Next, the operation of the above-mentioned 3-input-8-output decoder circuit will be described. First, the operation when the 3-bit digital data of the voltage VL system is "000" will be described. When the clock signal φ is “1” (that is, the inverted clock signal * φ is “0”), first, the NchFET 1 of the level shifter circuit 41a with the latch function is
Since “1” is input to both gates of 8, NchF
ET1 and ET8 are turned on. Further, since the clock signal φ is “1”, the NchFET 2 is also turned on and “0” is input to the 3-state inverter 10a.

The 3-state inverter 10a of the level shifter circuit 41a with the latch function outputs "1" (voltage VH) of the digital signal of the voltage VH system to the drain of the NchFET 25a and the source of the PchFET 26a and the drain of the NchFET 25b of the switching circuit 42a. And Pc
It outputs to the source of hFET26b, respectively. This time,
In the level shifter circuit 40 with a latch function, NchFE
Since "0" is input to T1, NchFET1 is O
It becomes FF and the voltage VH is applied to the 3-state inverter 10a.
"1" of the system digital signal is input. Therefore,
The 3-state inverter 10a of the level shifter circuit 40 with a latch function outputs a voltage VH system digital signal "0", and the inverter 20 outputs a voltage VH system digital signal "1".

As a result, all the NchFETs 25a and PchFETs 26a of the switching circuits 42a to 42d are turned on, and the NchFET 28a is turned off. On the other hand, all NchFs of the switching circuits 42a to 42d
Both ET25b and PchFET26b are turned off,
The NchFET 28b is turned on. Therefore, "1" of the digital signal of the voltage VH system output from the three-state inverter 10a of the level shifter circuit 41a with the latch function is the same as the NchFET 25a and Pc of the switching circuit 42a.
It is output to the outside through the hFET 26a. Therefore, the decode signal SH1 becomes "1" of the digital signal of the voltage VH system. Also, the decode signal SH2 is NchFET
Since 28b is ON, it becomes "0".

In the other level shifter circuits 41b to 41d with a latch function, the NchFET 1 or 8 is used.
Since either one or both of them are turned off, "1" is input to each of the three-state inverters 10a, whereby the corresponding switching circuit 42b is input.
"0" is output to 42d. Therefore, the decode signals SH3 to SH8 are all "0".

When the clock signal φ becomes "0" from this state, the level shifter circuits 40 and 41a with the latching function.
The output state of each level shifter circuit with a latch function is held by the loop formed by the three-state inverter 10b and the inverter 20 of 41d, whereby the decode signals SH1 to SH8 are also held in that state.

Next, the operation when the 3-bit digital data of the voltage VL system is "001" will be described. When the clock signal φ is “1” (that is, the inverted clock signal * φ is “0”), first, “1” is input to both gates of the NchFETs 1 and 8 of the level shifter circuit 41a with a latch function, so that NchFET1 , 8 are turned on respectively. Further, since the clock signal φ is “1”, the NchFET 2 is also turned on and the 3-state inverter 1
"0" is input to 0a.

The 3-state inverter 10a of the level shifter circuit 41a with the latch function outputs "1" (voltage VH) of the digital signal of the voltage VH system to the drain of the NchFET 25a and the source of the PchFET 26a and the drain of the NchFET 25b of the switching circuit 42a. And Pc
It outputs to the source of hFET26b, respectively. This time,
In the level shifter circuit 40 with a latch function, NchFE
Since "1" is input to T1, NchFET1 is O
It becomes N, and "0" is input to the 3-state inverter 10a. Therefore, the 3-state inverter 10a of the level shifter circuit 40 with the latch function outputs "1" of the digital signal of the voltage VH system, and the inverter 20 outputs "0" of the digital signal of the voltage VH system.

As a result, all the NchFETs 25a and PchFETs 26a of the switching circuits 42a to 42d are turned off, and the NchFET 28a is turned on. On the other hand, all NchFET 25b and PchFET
26b are both ON, and NchFET 28b is OFF
become. Therefore, the level shifter circuit 4 with a latch function
"1" of the digital signal of the voltage VH system output from the 3-state inverter 10a of 1a is N of the switching circuit 42a.
It is output to the outside through the chFET 25b and PchFET 26b. Therefore, the decode signal SH2 is
It becomes “1” of the H system digital signal. Also, since the NchFET 28a is ON for the decode signal SH1,
It becomes "0".

When the clock signal φ becomes "0" in this state, the level shifter circuits 40 and 41a with a latch function are connected.
The output state of each level shifter circuit with a latch function is held by the loop formed by the three-state inverter 10b and the inverter 20 of 41d, whereby the decode signals SH1 to SH8 are also held in that state.

Below, when the clock signal φ is "1", the upper 2 bits DL2, DL1 of the 3-bit digital data are
Are "0" and "1", respectively, from the level shifter circuit 41b with a latch function, and if "1" and "0", respectively from the level shifter circuit 41c with a latch function, and "1" and "1". , "1" is output from the level shifter circuit 41d with a latch function. In each case, the signals input from the corresponding level shifter circuits with a latch function according to the least significant bit DL0 are output from the connection points a1 to a4 or the connection points b1 to b4 of the switching circuits.

Table 2 shows a summary of the above operations in a truth table. That is, Table 2 shows that when the clock signal φ is “1”, the 3-bit digital data DL2, DL1, D
It shows what the values of the decode signals SH1 to SH8 are with respect to the signal of L0.

[Table 2] As can be seen from this table, according to the decoder circuit of the present embodiment, the input 3-bit digital data of the voltage VL system can be boosted to the digital signal of the voltage VH system and decoded. The output state is maintained according to the signal φ.

[0079]

As described above, according to the level shifter circuit with a latch function of the present invention, since both the level shift section and the latch section are driven by one type of voltage, when the driver of the liquid crystal display device is integrated into an IC, It is possible to integrate the rows into one system, and to use F
Since the number of ETs can be reduced, the size of the IC chip can be significantly reduced. Also, because the output impedance can be lowered,
The driving capability for the next-stage circuit is improved as compared with the conventional circuit. Furthermore, due to the reduction in the number of transistors,
Not only can the power consumption be reduced, but also the manufacturing process can be simplified and the yield can be improved.

[Brief description of drawings]

FIG. 1 is an electrical connection diagram showing a configuration of a level shifter circuit with a latch function according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit when each FET of the level shift unit in the level shifter circuit with a latch function is turned on.

FIG. 3 is a block diagram showing a configuration of a level shifter circuit with a latch function according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a level shifter circuit with a latch function according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a level shifter circuit with a latch function according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a specific example of a logic circuit portion of the level shifter circuit with a latch function.

FIG. 7 is a block diagram showing another form of the level shifter circuit with the latch function.

FIG. 8 is a block diagram showing another specific example of the logic circuit portion of the level shifter circuit with a latch function.

FIG. 9 is a block diagram showing the structure of a 3-input-8-output decoder circuit according to a fifth embodiment of the present invention.

FIG. 10 is an explanatory diagram for explaining the principle of the TFT driving method.

FIG. 11 is an electrical connection diagram showing a circuit configuration of a data latch unit and a level shifter unit in a conventional driver IC.

FIG. 12 is an explanatory diagram illustrating a concept of row in the layout of the driver IC.

FIG. 13 is an explanatory diagram illustrating a detailed layout example of rows in the same layout.

FIG. 14 is an explanatory diagram illustrating a frame portion of a liquid crystal panel.

FIG. 15 is an explanatory diagram for explaining a layout of rows in an IC chip.

[Explanation of symbols]

1, 2 ... NchFET, 3, 4 ... PchFET, 5
... Logic circuit, 6-1, 6-2, ..., 6-n ... Nch
FET, 7-1, 7-2, 7-3, 7-4 ... NchF
ET, 9a, 9b, 27a, 27b ... Inverter, 2
5a, 25b, 28a, 28b ... NchFET, 26
a, 26b ... PchFET, 10a, 10b ... 3-state inverter, 20 ... inverter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03K 19/0185 H03K 19/00 101D (72) Inventor Takashi Taguchi 580 Horikawa-cho, Kawasaki-shi, Kanagawa Prefecture No. 15 stock company Toshiba semiconductor system technology center

Claims (7)

[Claims] 1. A control signal which is a binary digital signal is input, and when the control signal is at a high level, a second level digital signal which is externally input is a second level which is higher than the first level. Level conversion means for converting and outputting to a level digital signal; and when the control signal is input and the control signal is at a high level, the logic of the second level digital signal output from the level conversion means is inverted. And a second logic inverting means for inverting the second-level digital signal output from the first logic inverting means, and the control signal being input to the control circuit. And a third logic inverting means for outputting the second level digital signal output from the second logic inverting means to the output of the first logic inverting means when the signal is at a low level. A level shifter circuit with a latch function. 2. The level converting means is connected to a first N-channel field effect transistor having a gate to which the control signal is input and a source which is grounded, and a drain of the first N-channel field effect transistor. A second N-channel field effect transistor having a source and a gate to which the first level digital signal is input, a drain connected to the drain of the second N-channel field effect transistor, a grounded gate, and A P-channel field effect transistor having a high level of a second level digital signal and a source to which the same voltage value is applied, the drain of the second N channel field effect transistor and the drain of the P channel field effect transistor A connection point with is connected to an input of the first logic inverting means, and 1, the voltage at the connection point when the second N-channel field-effect transistors and P-channel FET is turned on is, VA = VH {(RN1 + RN2) / (RP + RN1 + RN2)} <
Vth (where VA is the voltage at the connection point when the first and second N-channel field effect transistors and the P-channel FET are turned on, VH is the high level voltage of the second level digital signal, and RN1 Is the on-resistance of the first N-channel field effect transistor, RN2 is the on-resistance of the second N-channel field effect transistor, and RP is the P-channel F
2. The level shifter circuit with a latch function according to claim 1, wherein the on-resistance and Vth of ET satisfy the condition of (input threshold voltage of the first logic inverting means). 3. The level converting means is connected to a first N-channel field effect transistor having a gate to which the control signal is input and a source grounded, and a drain of the first N-channel field effect transistor. A second N-channel field effect transistor having a source and a gate to which the first level digital signal is input, a drain connected to the drain of the second N-channel field effect transistor, and the control signal. A P-channel field effect transistor having a gate and a source to which the same voltage value as the high level of the second level digital signal is applied, the drain of the second N channel field effect transistor and the P channel field effect transistor. The connection point with the drain of the effect transistor is connected to the input of the first logic inverting means. Claim 1 characterized by the above.
The level shifter circuit with the described latch function. 4. A gate connected to the output of the first logic inverting means, a source to which the same voltage value as the high level of the second level digital signal is applied, and an input of the first logic inverting means. 4. The level shifter circuit with a latch function according to claim 3, further comprising a P-channel field effect transistor having a drain connected to it. 5. A plurality of the first level digital signals are input instead of the second N-channel field effect transistor, and when the states of the plurality of the first level digital signals satisfy a predetermined condition. 5. The level shifter circuit with a latch function according to claim 2, further comprising a logic circuit which is turned on. 6. The logic circuit comprises third and fourth N-channel field-effect transistors, the source of the third N-channel field-effect transistor and the drain of the fourth N-channel field transistor are connected to each other, and 6. The level shifter circuit with a latch function according to claim 5, wherein when the two first level digital signals input to the respective gates of the third and fourth N-channel field transistors are both at a high level, they are turned on. 7. Control for decoding 3-bit digital data of a first level, converting the decoding result into a digital signal of a second level which is a level higher than the first level, outputting the digital signal, and inputting from the outside. A decoder for holding the decoding result according to a signal, the decoder comprising: a level shifter circuit with a latch function according to claim 2; and a level shifter circuit with a latch function according to any one of claims 1 to 6, The second output from the level shifter circuit with a latch function according to claim 2, having an input end and two output ends.
7. Switching means for outputting a signal input to the one input end from any one of two output ends based on a level digital signal, wherein the switching means is the first to fourth parts. 3. The level shifter circuit with a latch function according to claim 1, further comprising: first to fourth switching means, wherein the gate of the second N-channel electric field transistor of the level shifter circuit with a latch function according to claim 2 comprises: The least significant bit of the 3-bit digital data is input, and the 3-bit digital data is input to the gates of the third and fourth N-channel electric field transistors of the level shifter circuit with a latch function according to the first aspect. The inverted signal of the second bit and the inverted signal of the most significant bit are input, and the third and third level shifter circuits with a latch function according to claim 6 are input. The signal of the second bit of the 3-bit digital data and the inverted signal of the most significant bit are input to each gate of the N-channel electric field transistor of, and the third function of the level shifter circuit with a latch function according to the third aspect. 7. The latch function according to claim 4, wherein an inverted signal of the second bit of the 3-bit digital data and a signal of the most significant bit are input to each gate of the third and fourth N-channel electric field transistors. A decoder characterized in that a signal of the second bit of the 3-bit digital data and a signal of the most significant bit are inputted to each gate of the third and fourth N-channel electric field transistors of the level shifter circuit.