JPH09238348A - Image signal decoding method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store on-screen display(OSD) information in a memory device without increasing the storage capacity of the memory device storing a decoded frame image, a display frame image and a received bit stream in the case of displaying the OSD information onto a displayed image. SOLUTION: In the case that the device has a memory device 10, a decoding control circuit 11 controlling decoding the bit stream and the storage to the memory device 10, and a display control circuit 14, I and P pictures are decoded and stored in the memory device 10. In the case of displaying the OSD information, the storage of the image signal corresponding to the signal stored in areas hidden by B picture OSD information to the memory device 10 is inhibited and the OSD information is stored in the storage area whose storage is inhibited in the memory device 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for decoding an image signal, for example, reproducing an encoded moving image signal recorded on a recording medium such as a magneto-optical disk or a magnetic tape and displaying it on a display device or the like. Recording / reproducing apparatus for reproducing the moving image signal, and a video conference system for receiving the encoded moving image signal transmitted via the transmission line and reproducing the moving image signal also displayed on the display device or the like. It is suitable for use in a receiving device such as.

[0002]

2. Description of the Related Art Conventionally, like a video conference system or a video telephone system, or a broadcast system,
In a system for transmitting a moving image signal to a remote place, in order to efficiently use a transmission line, this image signal is compression-encoded using line correlation or interframe correlation of the image signal. .

For example, when the line correlation is used, the image signal can be compressed by performing orthogonal transformation (for example, DCT (discrete cosine transformation)) and encoding the obtained signal component.

Further, by utilizing the inter-frame correlation, the image signal can be further compressed and encoded. That is, since the images of frames that are temporally adjacent do not usually change so much, when the difference between the two is calculated, the difference signal becomes a small value. Therefore, if this difference signal is encoded, the code amount can be compressed.

However, if only the difference signal is transmitted, the original image cannot be restored. Therefore, a method of compressing and coding the image signal by converting the image of each frame into a signal of a frame format composed of any one of three types of I picture, P picture, and B picture is adopted.

This compression encoding method is shown in FIG. In this compression encoding method, a series of frames is processed in units of 17 frames (frames F1 to F17). This processing unit is called a group of pictures (GOP). This group of pictures is encoded into an I picture, a B picture, and a P picture in order from the first frame F1,
Hereinafter, the fourth and subsequent frames F4 to F17 are alternately encoded into a B picture or a P picture.

Here, the I picture is a picture obtained by directly encoding an image signal for one frame. As shown in FIG. 4A, the P picture basically encodes the difference between the image signal of the I picture that precedes it in time and the difference of the image signal of the P picture that precedes it in time. It is a picture obtained by doing. As shown in FIG. 4B, the B picture is basically a picture obtained by encoding the difference between the image signal and the average value of the temporally preceding frame and the following frame. is there. This coding method is called bidirectional predictive coding.

Incidentally, in addition to bidirectional predictive coding, the following three types of coding methods are actually used for B pictures.

The first encoding method is to transmit the data of the original frame (for example, frame F2) as it is as transmission data. This is called intra-coding, and is a process similar to I-picture. The second encoding method is, for example, the frame F3 temporally subsequent to the frame F2.
Is calculated and the difference is transmitted.
This is called backward predictive coding. The third encoding method is, for example, a method of transmitting the difference between the frame F2 and the frame F1 that precedes in time. This is called forward predictive coding.

At the time of encoding, among the four encoding methods of bidirectional predictive encoding, intra encoding, backward predictive encoding, and forward predictive encoding, data encoded by the method in which the transmitted data is the smallest is encoded. It is used as a B picture.

In an actual encoding device, the image signal thus converted into the frame format (I picture, P picture or B picture) is further converted into a block format signal, and is transmitted to the decoding device via the transmission path. It is designed to be transmitted.

This block format will be described with reference to FIG.

As shown in FIG. 5A, the image signal in the frame format is a collection of V lines of H dots per line. The image signal of this one frame is divided into N slices of which the length is not fixed in units of 16 lines. Each slice is shown in Figure 5.
(B), it is composed of M macroblocks. Each macroblock is, as shown in FIG.
It is composed of a luminance signal corresponding to 16 × 16 pixels (dots), and this luminance signal is divided into blocks Y [1] to Y [4] in units of 8 × 8 dots. The 16 × 16 dot luminance signals correspond to the 8 × 8 dot color signals Cb and Cr, respectively.

The bit stream encoded as described above is input to the decoding device via a transmission line or the like. In this decoding device, the above-mentioned input bitstream is once captured in a code buffer (reception buffer),
Further, decoding is performed by the processing procedure opposite to that at the time of encoding.
Incidentally, the frame image for which the decoding process has been completed is once stored in, for example, a frame memory group according to each frame format, and is used for the decoding process after the current point. Further, the image data decoded by the decoding device is once stored in the display frame memory and then output as display image data to the display device.

In the current decoding device, it has begun to realize the miniaturization of the system configuration by sharing the frame memory group with the display frame memory. In this decoding device, the frame memory group for storing the decoded frame image and the frame image for display, and the code buffer for storing the encoded input bit stream are This is realized by using a memory device such as D-RAM (dynamic RAM). It should be noted that this memory device is
It becomes the external memory of SI.

Here, as one of the image coding methods, the so-called M, which is an international standard for moving image compression / decompression technology, is used.
When a system such as a main level / main profile in PEG2 (Moving Picture Experts Group phase 2) is applied, a memory device having a storage capacity of 2 Mbytes can be used as the memory device of this decoding device.

That is, the above-mentioned MPEG is used as the image coding method.
When 2 is adopted, the amount of data to be stored is as follows depending on whether the input image data corresponds to the current color television broadcasting system NTSC system or PAL system. A memory device with a storage capacity of 2 Mbytes can be used.

For example, when the input image data is the NTSC system, the frame image is composed of 720 pixels × 480 lines, and the data amount of this frame image is 720 × 48.
0 × 8 × 1.5 = 4147200 bits. Here, when the above-mentioned MPEG2 is adopted as the image encoding method, the data of 2 frames (that is, 4147200 bits × 2 = 8294400 bits) for the prediction image of the B picture and the B picture are stored in the memory device. One frame for storage and display (ie 41
It is necessary to store a total of 14276608 bits of data of 47200 bits) and 1835008 bits of data for the code buffer. At this time, since 16777216 bits (2 Mbytes) -14276608 bits = 2500608 bits, when the input image data is the NTSC system, the memory device having the storage capacity of 2 Mbytes can be used.

When the input image data is of the PAL system, the frame image is composed of 720 pixels × 576 lines, and the data amount of this frame image is 720 × 57.
6 × 8 × 1.5 = 4976640 bits. Here, when the above-mentioned MPEG2 is adopted as the image encoding system, the data of two frames (that is, 4976640 bits × 2 = 9953280 bits) for the prediction image of the B picture and the B picture are stored in the memory device. One frame for storage and display (ie 4
977640 bits of data) and 183008 bits of data for the code buffer,
It is necessary to store a total of 167692828 bits of data. At this time, since 16777216 bits (2 Mbytes) -167692828 bits = 12288 bits, it is possible to use the memory device having the storage capacity of 2 Mbytes even when the input image data is the PAL system.

[0020]

By the way, when displaying an image decoded as described above on a display device connected to the decoding device, for example, information such as characters or figures (hereinafter , On-screen display (OSD) information) may be displayed simultaneously with the decoded image.

In order to realize the display of the on-screen display information at the same time as the decoded image, for example, the decoding device switches the decoded image data and the on-screen display information to the display device. Must be output. here,
As one of the most effective methods for switching and outputting the decoded image data and the on-screen display information from the decoding device, first, the decoded image data and the on-screen display information are stored in a memory means,
There is known a method of performing control such that the decoded image data and the on-screen display information are switched and read when reading the data from the memory means.

When such a method is used, it is conceivable to use the memory device as the memory means. Here, if a memory device having a storage capacity of 2 Mbytes is used as described above, the decoded image data and the on-screen display information cannot be stored at the same time in terms of storage capacity. Therefore, in order to store the on-screen display information at the same time, it is necessary to use a memory device having a large storage capacity. Since a memory device such as a D-RAM is usually set to have a capacity of 4 Mbytes after 2 Mbytes, in this case 4 Mbytes are set.
You will be using a byte memory device. However, the use of the 4 Mbyte memory device causes an increase in cost and is not preferable in terms of effective utilization of the storage capacity of the memory device itself.

In the case of using the above method, it is also possible to prepare a storage memory dedicated to on-screen display information as the memory means, in addition to the memory device. However, this leads to an increase in the size of the system configuration and is not preferable in terms of cost.

Therefore, the present invention has been made in consideration of the above points, and when displaying on-screen display information such as characters or figures on a display image, a decoded frame image, a display frame image and an input are displayed. An object of the present invention is to provide an image signal decoding method and apparatus capable of storing on-screen display information on a memory device that stores a bitstream without increasing the storage capacity of the memory device.

[0025]

SUMMARY OF THE INVENTION An image signal decoding method and apparatus of the present invention are for sequentially decoding encoded image signals that have been motion compensated predictive coded to generate decoded image signals. When a coded image signal corresponding to an image to be used is decoded and stored in a storage element and an image different from the decoded image is displayed on the display screen of the decoded image, it corresponds to an image that is not used for prediction. In addition, it is prohibited to store an image signal corresponding to an area hidden by another image on the display screen in a storage element, and store the signal of another image in the storage area on the storage element where the storage is prohibited. The above-mentioned problem is solved by.

That is, according to the present invention, for example, for I pictures and P pictures, as in the case of a normal decoding operation, all the frame data are stored in the memory device, whereas for B pictures not used as prediction images. Does not store the data of the area hidden by the display of the on-screen display information on the memory device.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an image decoding method and apparatus according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the overall configuration of an image signal decoding apparatus of the present invention which realizes the image signal decoding method of the present invention. This image signal decoding device does not perform a decoding operation on an area hidden by the on-screen display information for a B picture on the display screen.

Each unit of the image signal decoding apparatus is configured as follows.

First, the input terminal 20 displays the data of the bit stream S1 input through the recording medium or the transmission line and the on-screen display information (OSD information) such as characters and figures on the display image data. OS at the time
A signal including the D information S15 is supplied, and these signals are sent to the demultiplexer 1. The demultiplexer 1 separates the data of the bit stream S1 and the OSD information S15 from the input signal, and the data of the bit stream S1 is stored in the memory device 10 including a D-RAM having a storage capacity of 2 Mbytes, for example. Of the OSD information S15 is supplied to the controller 19 described later. In addition,
The memory device 10 is an external memory of the LSI when viewed from the decoding LSI.

In the reception buffer area 2 in the memory device 10, the data of the bit stream S1 is temporarily stored, and then the stored data is sent to the variable length decoding circuit 3.

The variable length decoding circuit 3 variable length decodes the bit stream S1 from the reception buffer area 2. The variable length decoding circuit 3 supplies the inverse quantization circuit 4 with the image data obtained by the variable length decoding process, and outputs various flag information used for the subsequent processing to the inverse quantization circuit 4 and the motion compensation circuit 9. To do. The flag information includes the quantization step S2, the frame / field DCT flag S3.
(Hereinafter, referred to as DCT flag S3), motion vector S
4, prediction mode S5, and frame / field prediction flag S6 (hereinafter referred to as prediction flag S6).

Further, the variable length decoding circuit 3 sends and receives various signals to and from the decoding control circuit 11, and controls the variable length decoding process based on these signals. These various signals are picture configuration information S7, picture type information S8, slice address information S9, and decoding control signal S.
10 signals. Here, the picture configuration information S
Reference numeral 7 is a signal indicating whether the picture is a frame structure or field structure, and the picture type information S8 is a signal indicating whether the picture is an I picture, a P picture or a B picture. Also, the slice address information S
Reference numeral 9 is a signal indicating a vertical macroblock position of a decoded image to be subjected to variable length decoding. The dequantization circuit 4 receives the image data from the variable length decoding circuit 3 and dequantizes it based on the quantization scale S2. The data obtained by the inverse quantization in the inverse quantization circuit 4 is sent to the IDCT circuit 5.

The IDCT circuit 5 performs inverse DCT processing on the data (DCT coefficient) input from the inverse quantization circuit 4 and supplies the processing result to the frame / field DCT block rearrangement circuit 6.

The frame / field DCT block rearrangement circuit 6 determines the IDC based on the DCT flag S3.
The data input from the T circuit 5 is rearranged, and the obtained image data S11 is output to the motion compensation circuit unit 7.

The arithmetic unit 8 in the motion compensation circuit unit 7 and the image data S11 obtained by the above processing and the motion compensation circuit 9
The predicted image data S12 input from the above is calculated, and the result is output as the reproduced image signal S13.

The motion compensation circuit 9 reads the image data from the image signal storage area 12 which is a frame memory group in the memory device 10 based on the motion vector S4, the prediction mode S5 and the prediction flag S6, and the predicted image data S1 is obtained.
Generate 2.

If the picture type of the image data S11 is I-picture, the motion compensation circuit 9 does not generate the predicted image data S12.

On the other hand, when the picture type of the image data S11 is the P picture and it is the data encoded in the forward prediction mode, the motion compensation circuit 9 of the memory device 10 based on the motion vector S4. The forward predicted image is read from the image signal storage area 12 to generate predicted image data S12. Incidentally, even if the image data is a P picture, if the data is coded in the intra-prediction mode, the predicted image data S12 is not generated, as is the case with the I picture image data.

If the picture type of the image data S11 is a B picture and it is encoded in the forward prediction mode, the motion compensation circuit 9 determines that the motion vector S11
4, the forward prediction image is read from the image signal storage area 12 of the memory device 10, and the prediction image data S1
Generate 2.

Further, when the picture type of the image data S11 is the B picture and it is encoded in the backward prediction mode, the motion compensation circuit 9 determines the image signal of the memory device 10 based on the motion vector S4. The backward predicted image is read from the storage area 12, and the predicted image data S
12 is generated.

Furthermore, when the picture type of the image data S11 is a B picture and it is encoded in the bidirectional prediction mode, the motion compensation circuit 9 determines the image of the memory device 10 based on the motion vector S4. The forward predicted image and the backward predicted image are read from the signal storage area 12 to generate predicted image data S12. Incidentally, even in the case of B-picture image data, if the data is coded in the intra-picture prediction mode, the predicted image data S12 is not generated as in the case of the I-picture image data.

In addition to the above, the motion compensating circuit 9 performs a motion compensating frame / field process based on the prediction flag S6.

As described above, the image signal storage area 12 of the memory device 10 outputs image data to the motion compensation circuit 9 and stores the reproduced image signal S13. The image signal storage area 12 includes three frame image storage units 12A, 12B and 1 each corresponding to a frame memory.
2C, and the reproduced image signal S1 is stored in any one of these three frame image storage units 12A, 12B, 12C according to the picture type of the current decoded image data.
It is designed to remember 3.

From the image signal storage area 12 of the memory device 10, under the control of the display control circuit 14,
The display image data S16 is output. An image based on the display image data S16 is displayed on the display device (not shown). Here, when the on-screen display information (OSD information) such as characters and figures is displayed on the image based on the display image data S16, the OSD information S15 is the OSD information storage area 13 in the memory device 10. Memorized in. This OSD information S15 is supplied from the controller 19 and
This OSD is stored in the information storage area 13.
The information S15 is read from the OSD information storage area 13 as the OSD display data S17 under the control of the display control circuit 14.

Further, the controller 19 uses the OS
The display image information S14 is generated based on the D information S15,
The display image information S14 is supplied to the decoding control circuit 11 and the display control circuit 14.

The display control circuit 14 controls the display image information S.
Based on 14, the display image data S16 and the OSD display data S17 from the memory device 10 are switched and output as the display data S18. This display data S18
Is sent to a display device (not shown) via the output terminal 21, so that an image based on the display image data S16 and the OSD display data S17 is displayed.

Next, the operation of the decoding control circuit 11 will be described.

The decoding control circuit 11 is provided to the variable length decoding circuit 3 based on the picture configuration information S7, the picture type information S8, the slice address information S9 and the display image information S14 which are input from the variable length decoding circuit 3. for,
Decoding control signal S for instructing whether to perform decoding processing or skip processing in slice units without performing decoding processing
10 is output.

That is, the decoding control circuit 11 determines the area of the display image hidden by the OSD information when the predicted image is a B picture by determining in slice units using the slice address information S9 in the bitstream. , If the slice to be decoded is a position hidden by the display of OSD information, skip the decoding process and perform the decoding process if the slice is not hidden by the display of OSD information. Then, the decoding control signal S10 for controlling the decoding in the variable length decoding circuit 3 is output.

Further, the decoding control circuit 11 makes a different determination depending on whether the picture configuration information S7 in the bitstream is a frame configuration or a field configuration, and outputs a decoding control signal S10 according to this determination. This is because the slice size at the time of decoding processing corresponding to the display image differs between the frame structure and the field structure.

Next, the OSD information display processing operation at the time of frame configuration and field configuration will be described.

First, FIG. 2 shows an example of OSD information display when a frame is constructed. Here, as shown in FIG.
For example, an example is shown in which a picture having a frame structure of M pixels in the horizontal direction and 64 lines in the vertical direction is decoded. Further, since this picture is composed of four slices (1) to (4) and is coded in a frame structure, each slice of the reproduced image is one line as shown in FIG. 2B. Every other eight lines correspond to the display image of the first field, and every other line, eight lines adjacent to those of the first field correspond to the display image of the second field.

For these display images, FIG.
When OSD information consisting of 20 lines as shown in FIG. 2 is displayed below the display image as shown in FIG. 2D, for example, slice (3) and slice (4) of the display image in the first field are displayed. ) Is completely hidden by the OSD information and becomes invisible. The same applies to the display image of the second field.

At this time, the slice (3) and the slice (4) which cannot be seen on the display in the I picture and the P picture are displayed.
Since these are also used as prediction images, it is necessary to decode these slices (3) and slices (4) to create reproduced images. On the other hand, since the B picture is not used as a predicted image, it is not always necessary to decode the slices (3) and slices (4) that are invisible on the display to create a reproduced image.

Therefore, the image signal decoding apparatus of the configuration example of the present invention does not perform the decoding operation for the area hidden by the OSD information for the B picture on the display screen.

The decoding operation processing for B pictures will be described below. As shown in FIG. 2, since the slice (1) is not a slice hidden by the OSD information, the decoding control circuit 11 has the decoding control signal S10.
Instructs the variable length decoding circuit 3 to perform the decoding process. The image signal decoding circuits subsequent to the variable length decoding circuit 3 process this slice (1) to obtain the slice (1).
Generates a playback image of.

At this time, the determination as to whether the slice is hidden by the OSD information can be made by associating the number of lines at which the display of the OSD information is started with the slice of the reproduced image. In the example of FIG. 2, the number of lines to the position where the display of OSD information is started is 12 lines, and the slice (1) in the frame configuration corresponds to 1 to 8 lines in the display image. Therefore, slice (1)
Can be determined to be a slice that is not hidden by the OSD information (the reproduced image of slice (1) is displayed).

Similarly, with respect to the slice (2), it can be judged that the slice corresponds to the 9th to 16th lines in the display image and is not hidden by the OSD information (if there is a part not hidden by the OSD information, the decoding process is performed). The decoding control circuit 11 instructs the variable length decoding circuit 3 to perform a decoding process by the decoding control signal S10. As a result, the variable length decoding circuit 3
The subsequent image signal decoding circuit processes this slice (2) and generates a reproduced image of the slice (2).

Similarly, the slice (3) has 17 to 24 lines in the display image. here,
The number of lines to the position where the display of OSD information starts is 1
Since there are two lines and the number of lines up to the position where the display of the OSD information ends is 32 lines, it can be determined that the slice (3) is a slice hidden by the OSD information. Therefore, the decoding control circuit 11 instructs the variable length decoding circuit 3 not to perform the decoding process but to perform the skip process until the next slice by the decoding control signal S10. As a result, the variable length decoding circuit 3 skips the slice (3) and the subsequent image signal decoding circuit does not process this slice (3), so that the reproduced image of the slice (3) is not generated.

Similarly, the slice (4) has 25 to 32 lines in the display image. At this time, the number of lines to the position where the display of the OSD information is started is 12 lines, while the number of lines to the position where the display of the OSD information is ended is 32 lines, so that the slice (4) depends on the OSD information. It can be judged as a hidden slice. Therefore, the decoding control circuit 11 instructs the variable length decoding circuit 3 not to perform the decoding process but to perform the skip process until the next slice by the decoding control signal S10. As a result, the variable length decoding circuit 3 skips the slice (4) and the subsequent image signal decoding circuit does not process this slice (4), so that the reproduced image of the slice (4) is not generated.

As a result, the slice (3) and the slice (4) are stored in the image signal storage area 12 in the memory device 10.
Is not stored, and an empty area is created in the memory device 10 as compared with storing all slices.

Therefore, the image signal decoding apparatus of the configuration example of the present invention uses this free area as the OSD information storage area 13.

Next, FIG. 3 shows an example of OSD information display in the field configuration. Here, as shown in FIG. 3A, an example is shown in which a picture having a field structure of M pixels in the horizontal direction and 32 lines in the vertical direction is decoded. Also,
Since each picture is composed of two slices (1) and (2) and is encoded by the field structure, each slice of the first field of the reproduced image is as shown in FIG. 3B. All 16 lines correspond to the display image of the first field, and all 16 lines of each slice of the second field of the reproduced image correspond to the display image of the second field.

For these display images, FIG.
When the OSD information consisting of 20 lines as shown in Fig. 3 is displayed below the display image as shown in Fig. 3D, the slice (2) of the display image in the first field is represented by the OSD information. It is hidden and invisible. The same applies to the display image of the second field.

At this time, since the slice (2) of each field, which is invisible on the display in the I picture and the P picture, is also used as a prediction image, it is necessary to decode the slice (2) of each field to create a reproduced image. There is. On the other hand, since the B picture is not used as a prediction image, it is not always necessary to perform a decoding process on the slice (2) of each field that is invisible on the display to create a reproduced image.

Therefore, the image signal decoding apparatus of the configuration example of the present invention does not perform the decoding operation on the area hidden by the OSD information for the B picture on the display screen even in the case of the field configuration.

The decoding operation for B pictures will be described below.

First, as shown in FIG. 3, since the slice (1) of the first field is not a slice hidden by OSD information, the decoding control circuit 11
The decoding control signal S10 instructs the variable length decoding circuit 3 to perform decoding processing. The image signal decoding circuit after the variable length decoding circuit 3 processes the slice (1) of the first field and generates a reproduced image of the slice (1) of the first field.

At this time, the determination as to whether or not the slice is hidden by the OSD information can be made by associating the number of lines at which the display of the OSD information is started with the slice of the reproduced image. In the example of FIG. 3, the number of lines to the position where the display of the OSD information is started is 12 lines, and the slice (1) of the first field in the field configuration corresponds to 1 to 16 lines in the display image. Therefore, it can be determined that the slice (1) of the first field is a slice that is not hidden by the OSD information (the reproduced image of the slice (1) of the first field is displayed) (even if there is a region that is not hidden by the OSD information). In that case, decryption processing is performed).

Similarly, the slice (2) of the first field
Is about 17 to 32 lines in the display image. Here, the number of lines to the position where the display of the OSD information is started is 12 lines, while the number of lines to the position where the display of the OSD information is ended is 32 lines, so that the slice (2 ) Can be determined to be a slice hidden by the OSD information. Therefore, the decoding control circuit 11 instructs the variable length decoding circuit 3 not to perform the decoding process but to perform the skip process until the next slice by the decoding control signal S10. As a result, the variable length decoding circuit 3 skips the slice (2) of the first field, and the subsequent image signal decoding circuit does not process the slice (2) of the first field. The reproduced image of (2) is not generated.

The processing of the second field is performed in the same manner as the first field.

As a result, the slice (2) of the first field is stored in the image signal storage area 12 in the memory device 10.
And the slice (2) of the second field are not stored and all the slices are stored.
There is an empty area at 0.

Therefore, the image signal decoding apparatus of the configuration example of the present invention can use this free area as the OSD information storage area 13 even in the case of the field configuration.

According to the above configuration, when the OSD information is to be displayed, the slice hidden by the OSD information in the B picture is skipped and not decoded, and is not stored in the memory device 10. , The OSD information storage area 13 in the memory device 10
Can be secured. That is, in the image signal decoding apparatus of the configuration example of the present invention, it is not necessary to prepare a memory device different from the memory device 10 for storing the OSD information and to increase the storage capacity of the memory device 10. This means that an image signal decoding circuit using a memory device having a storage capacity of, for example, 2 Mbytes can be realized while securing the OSD information storage area 13 even when the input image data is in the PAL system. Therefore, it is particularly effective.

In the above configuration, the OS is used for the B picture.
Regarding the slice hidden by the D information, the variable length decoding circuit 3 is instructed to skip the read operation and the operation of not storing it in the memory device 10 is realized. Surprisingly, the slice hidden by the OSD information in the B picture is realized. Even if there is, it is decoded by the variable length decoding circuit 3, but the decoded data of the slice hidden by the OSD information is not processed by any circuit portion in the image signal decoding circuit after the variable length decoding circuit 3. Thus, it may be realized that the data is not stored in the memory device 10.

In the above-mentioned configuration example, the case where the data structure of the bit stream S1 has three layers of macroblocks, slices and frames has been described, but the present invention is not limited to this, and more hierarchical structures are possible. Similar processing can be applied to the bit stream S1 to be taken.

Further, in the above-mentioned configuration example, the IDCT processing is executed as the processing after the dequantization processing. However, when the orthogonal transform coding processing other than the DCT is carried out at the time of coding, it corresponds to it. Inverse conversion processing may be executed.

Further, in the above-mentioned configuration example, the case where the slice which is completely hidden by the OSD information in the B picture is skipped from the bit stream S1 and the decoding operation is reunited from the beginning of the slice has been described in the above configuration example. The present invention is not limited to this, and the decoding process may be controlled in units of macroblocks that are lower layers of the slice.

In this case, of the various signals transmitted and received between the variable length decoding circuit 3 and the decoding control circuit 11 having the configuration of FIG. 1, the slice address information S9 becomes macroblock address information S9m, and the decoding control signal S10. Is a decoding control signal S10m for instructing not to perform decoding in macroblock units.

That is, in this case, the decoding control circuit 11
Performs decoding processing on the variable length decoding circuit 3 based on the picture configuration information S7, picture type information S8, macroblock address information S9m and display image information S14 input from the variable length decoding circuit 3. Alternatively, the decoding control signal S10m is output instructing in macroblock units without performing decoding processing.

Further, the decoding control circuit 11 judges the area of the display image which is hidden by the OSD information at the time of the bidirectional prediction image by judging in macroblock units using the macroblock address information S9m, and then performs the decoding process. Do not perform the decoding process if the macroblock is at a position hidden by the display of OSD information.
The decoding control signal S10m for controlling the decoding in the variable length decoding circuit 3 is output so that the decoding process is performed if the position is not hidden by the information display.

The following operation is performed according to the above-mentioned processing in slice units.

[0084]

According to the image signal decoding method and apparatus of the present invention, the coded image signal corresponding to the image used for prediction is decoded and stored in the storage element, and is decoded on the display screen of the decoded image. When displaying an image different from the image, an image signal corresponding to an image not used for prediction and corresponding to an area hidden by another image on the display screen is prohibited from being stored in the storage element, By storing the signal of another image in the storage area on the storage element where the storage is prohibited, the number of storage elements does not increase, and when the decoded image is displayed, there is no failure and the image signal encoding is further performed. An area for storing the signal of another image can be secured on the storage element without restricting the method and the device.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration example of an image signal decoding device of the present invention.

FIG. 2 is a diagram showing an example of OSD information display when a frame is configured.

FIG. 3 is a diagram showing an example of OSD information display at the time of field configuration.

FIG. 4 is a diagram used to describe a picture type of an input image signal.

FIG. 5 is a diagram used to describe a structure of image data.

[Explanation of symbols]

1 demultiplexer, 2 receive buffer area, 3
Variable length decoding circuit, 4 inverse quantization circuit, 5 IDC
T circuit, 6 frame / field DCT block rearrangement circuit, 7 motion compensation circuit section, 8 arithmetic unit,
9 motion compensation circuit, 10 memory device, 11 decoding control circuit, 12 image signal storage area, 13 OSD information storage area, 14 display control circuit, 19 controller

Claims (10)

[Claims] 1. An image signal decoding method for sequentially decoding motion compensated predictive coded coded image signals to generate a decoded image signal, wherein a coded image signal corresponding to an image used for prediction is decoded. Stored in a storage element, and when an image different from the image obtained by decoding the encoded image signal is displayed on the display screen of the decoded image, it corresponds to an image not used for prediction and It is prohibited to store an image signal corresponding to a region hidden by another image in the storage element, corresponds to an image not used for the prediction, and corresponds to a region hidden by the other image on the display screen. An image signal decoding method, characterized in that the signal of the other image is stored in a storage area on the storage element where the storage of the image signal to be stored is prohibited. 2. Storing in the storage element by inhibiting decoding of the coded image signal corresponding to an image not used for the prediction and corresponding to an area on the display screen hidden by the other image. 2. The image signal decoding method according to claim 1, wherein the prohibition is executed. 3. A transmission of a decoded image signal of the encoded image signal, which corresponds to an image not used for the prediction and corresponds to an area hidden by the other image on the display screen, to the storage element. 2. The image signal decoding method according to claim 1, wherein prohibiting storage in the storage element is performed by performing the above. 4. The coded image signal corresponding to a region hidden by the another image on the display screen is searched for based on a predicted image configuration of the coded image signal. The described image signal decoding method. 5. The coded image signal corresponding to a region hidden by the another image on the display screen is searched based on position information in the vertical direction of the coded image signal. Item 1. The image signal decoding method according to Item 1. 6. An image signal decoding apparatus for sequentially decoding a motion-compensated predictive-coded coded image signal to generate a decoded image signal, comprising: a storage element; storage in the storage element; And a control means for controlling the decoding of the encoded image signal corresponding to the image used for prediction, and stores the decoded image signal in the storage element. When an image different from the image obtained by decoding the encoded image signal is displayed, an image signal corresponding to an image not used for prediction and corresponding to an area hidden by the other image on the display screen is stored in the storage element. To a storage area on the storage element which is prohibited from being stored in the storage element and which is prohibited from being stored in the storage device and which corresponds to an image which is not used for the prediction and which is prohibited from being stored in the display screen. another An image signal decoding device characterized by storing an image signal. 7. The control means prohibits decoding of the coded image signal corresponding to an image not used for the prediction and corresponding to an area hidden by the other image on the display screen, 7. The image signal decoding device according to claim 6, wherein prohibition of storage in the storage element is executed. 8. The storage element for storing a decoded image signal of the encoded image signal, which corresponds to an image not used for the prediction and which corresponds to an area hidden by the other image on the display screen. 7. The image signal decoding apparatus according to claim 6, wherein the storage to the storage element is prohibited by prohibiting the transmission to the storage element. 9. The control means searches for the coded image signal corresponding to a region hidden by the another image on the display screen based on a predicted image configuration of the coded image signal. The image signal decoding device according to claim 6. 10. The control means searches for the coded image signal corresponding to a region hidden by the another image on the display screen based on position information in the vertical direction of the coded image signal. The image signal decoding device according to claim 6, wherein