JPH09237259A - Method for controlling maintenance of data consistency in multi processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time required for the control of the maintenance of data consistency when a cache error owing to reading occurs. SOLUTION: When a processor PRi writes data into a block in a shared state on a cache CMi, the update is reflected not only the cache CMi but also on a memory MMi and the latest block is caused to exist in the memory MMi. When the other processor PRi generates the cache error, the latest block can be taken out from the memory MMi and it is not required to give rewrite request to the cache CMi which solely holds the latest block from the memory MMi.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which each processor has a cache,
The present invention relates to a data consistency maintenance control method.

[0002]

2. Description of the Related Art In a multiprocessor system, data having the same address can exist in a plurality of caches existing in the system. Therefore, it is necessary to perform control for maintaining data consistency and control for maintaining data consistency between caches that hold data at the same address.

This data consistency maintenance control is for guaranteeing that each processor can exclusively write data in a certain block and obtain the latest value at the time of reading. Control.
Therefore, first of all, it must be possible to specify in which cache the block to be written exists. And in the case of a mistake during reading,
It must be possible to identify where the latest block is. Here, a block is the minimum unit of data management, and its size is, for example, 64 bytes.

For example, in the literature (“A New Solut
ion to Coherency Problems
in MultiSystems "LUC
IEN M. CENSIER and PAUL FE
AUTRIER, IEEE Transactions
on Computers, p1112-1118, D
The method disclosed in e.
It has the following three features. The first feature is that the cache holds information on whether the block is shared in block units. A second feature is that the memory holds information for identifying the cache holding the block in units of blocks, and information indicating whether the latest block exists in the memory. A third feature is that when writing to a block shared by processors, the blocks of other caches are invalidated to eliminate the shared state, and the latest block exists only in the cache. To do.

The operation of this method will be described below.

Referring to FIG. 1, a multiprocessor system according to the related art and the present invention includes a processor PRi for executing an instruction and a memory access, and each processor PRi.
A cache CMi that is connected to the processor PRi and temporarily holds data accessed by the processor PRi, a memory MMi that holds data, a cache CMi, and an interconnection network 12 that connects the memory MMi. In the system shown in FIG. 1, the interconnection network 12 has eight ports. Port 0 has a cache CM1, port 1 has a cache CM2, port 2 has a cache CM3, and port 3 has a cache CM3. The cache CM4 has a memory MM1 at port 4.
However, the memory MM2 is connected to the port 5, the memory MM3 is connected to the port 6, and the memory MM4 is connected to the port 7.

A series of operations for maintaining data consistency performed by the access will be described below by taking the case where the processor PR1 accesses the data in the memory MM2 as an example.

The operation when the processor PR1 accesses the data of a certain block but the block does not exist in the cache CM1 (hereinafter, this case is referred to as a cache miss) will be described. In this case, first, a read request message is issued from the cache CM1 to the memory MM2. Memory MM2 that received the read request
Checks whether the latest block exists in the memory, and if there is, updates the block in the cache CM1.
Send to If it does not exist, there is the only cache holding the latest block, so the write-back request message is issued to that cache, for example, the cache CM3. The cache CM3 that has received the write-back request writes back the block to the memory MM2. The memory MM2 transmits the block written back from the cache CM3 to the cache CM1. The cache CM1 that received the block again evaluates the memory access performed by the processor PR1 and performs the necessary processing for maintaining the data consistency.

As a result of the above processing, the cache CM1 newly holds the latest block in addition to the cache which previously held the block. Also, the memory M
The latest block also exists in M2.

Next, the operation when the processor PR1 reads data from a certain block and the block is present in the cache CM1 (hereinafter, this case is referred to as a read hit) will be described. In this case, cache C
The processing is completed by M1 passing the data of the block to the processor PR1.

Next, the operation when the processor PR1 writes data in a certain block and the block exists in the cache CM1 and is not in the shared state (hereinafter, this case is referred to as a write hit) will be described. In this case, the writing performed by the processor PR1 in the cache CM1 is reflected in the block held by the cache CM1,
The process is completed by notifying the processor PR1 that the writing has been completed.

Next, the operation when the processor PR1 writes data in a certain block and the block exists in the cache CM1 and is in a shared state (hereinafter, this case is referred to as write shared) will be described. In this case, the write performed by the processor PR1 is reflected in the cache CM1, and a write request message is issued to the memory MM2. The memory MM2 that has received the write request, for example, if cache CM3 and cache CM4 other than the cache CM1 hold blocks, the cache CM3 and cache CM
Issue an invalidation request message to No. 4. The cache CM3 and the cache CM4 which have received the invalidation request invalidate the block and transmit an invalidation completion message to the memory MM2. Upon receiving the invalidation completion message from both the cache CM3 and the cache CM4, the memory MM2 transmits a completion response message to the cache CM1. Cache CM1
When receiving the completion response message, the processor PR
1 is notified that the writing is completed, and the processing is completed. As a result of the above processing, only the cache that has written holds the latest block, and the latest block does not exist in the memory.

As a result of the above processing, the latest block exists only in the cache CM1, and the latest block does not exist in the other caches CMi and memory MM2.

In the above description of the operation for maintaining the data consistency, for example, the memory MM2 receives a read request from the cache CM1 and issues a write-back request to the cache CM3 to write back the block. In the waiting state, the operation when a read request is issued from the cache CM 2 is omitted.

[0015]

The first problem is that when a cache miss occurs due to the reading of the processor, it takes a long time until the data is returned from the cache to the processor.

For example, the cache CM1 and the cache C
Consider the operation when the processor PR1 performs writing and then the processor PR4 performs reading while the block of the memory MM2 exists in M3 and is shared. When the processor PR1 performs the writing, the latest block exists only in the cache CM1 and the latest data does not exist in the memory MM2 either.
Next, when the processor PR4 performs a read operation, a cache miss occurs because there is no block in the cache CM4. As a result, the read request message is transmitted to the memory MM2, but since the latest data does not exist in the memory MM2, the write-back is requested to the cache CM1 holding the latest data. The memory MM2 receives the block write-back from the cache CM1, and then transmits the block to the cache CM4. The cache CM4 receiving the block again evaluates the read performed by the processor PR4, and since the block exists, the data is passed to the processor PR4 and the processing is completed.

Thus, the reason for the above problem is that the latest block no longer exists in memory after the processor has written.

The second problem is that many messages are exchanged between the cache and the memory for the data consistency maintenance control.

The reason is that the latest block no longer exists in memory after the processor has written. That is, after a processor writes,
When a cache miss occurs in another cache, in addition to the read request message to the memory and the block transfer to the cache, the write-back request message to the cache holding the latest data and the write-back of the block from the cache are performed. This is necessary.

An object of the present invention is to provide a data coherency maintenance control method which shortens the time required for the data coherency maintenance control when a cache miss due to a read occurs.

Another object of the present invention is to provide a data consistency control method that prevents an increase in the number of messages generated by the data consistency maintenance control.

[0022]

According to a first data consistency maintenance control method of the present invention, when data is written to a block shared by processors, the data is written to the block of the cache and the memory. Means for performing data coherency maintenance control in the cache and the memory (23 in FIG. 2) in which the block of the other cache is invalidated and the state of the block of the cache in which the writing is performed remains in the shared state. And 44) in FIG.

According to the second data consistency maintenance control method of the present invention, when a block shared by the processors is written, the latest block exists only in the cache and the memory. If the cache of the cache does not hold the latest block, the writing is reflected to the cache and the block of the memory, but the state of the block of the written cache is changed from the shared state to the non-shared state. It has means (23 in FIG. 2 and 44 in FIG. 3) for performing coherency maintenance control in cache and memory.

According to the third data consistency maintenance control method of the present invention, a counter is provided for each block in the memory, the value of the counter is initialized to 0 when the block is newly fetched in the cache, and shared by the processors. When writing to a block, the counter value of that block is incremented, and when writing to a block shared by the processors, the latest block is only written to the cache and memory. If it exists, other cache does not hold the latest block, and the value of the counter is a certain value,
A means for performing data coherency maintenance control in the cache and the memory, which reflects the writing to the block of the cache and the memory, but changes the state of the block of the written cache from the shared state to the non-shared state (Fig. 2 of 23 and 44 of FIG. 3).

The data consistency maintenance control means in the first data consistency maintenance control method of the present invention, when writing to a block shared by the processors,
It is assumed that the latest block exists in the written cache and memory.

The data coherency maintenance control means in the second data coherency maintenance control method of the present invention allows the processor to continuously write to a block actually shared by a plurality of caches, and during other periods. If the cache does not access, the first two writes are reflected in the memory as well, but the shared state of the block is canceled after the second write, and only the cache concerned after the third write. Done.

The data coherency maintenance control means in the third data coherency maintenance control method of the present invention allows the processor to continuously write to a block which is actually shared by a plurality of caches, and during other periods. When the cache is not accessed, the writing of a certain number of times is reflected in the memory, but the subsequent writing is performed only to the cache.

[0028]

Next, the present invention will be described with reference to the drawings.

Referring again to FIG. 1, the multiprocessor system according to the present invention includes a processor PRi that executes instructions and performs memory access, and a cache that is connected to each processor PRi and temporarily holds data accessed by the processor PRi. CMi, a memory MMi that holds data, a cache CMi, and an interconnection network 12 that connects the memories MMi. In the system shown in FIG. 1, the interconnection network 12 has eight ports. Port 0 has a cache CM1, port 1 has a cache CM2, port 2 has a cache CM3, and port 3 has a cache CM2.
Has a cache CM4 and port 4 has a memory MM1
However, the memory MM2 is connected to the port 5, the memory MM3 is connected to the port 6, and the memory MM4 is connected to the port 7.

Here, each cache CMi and memory MMi is provided with a 3-bit device number corresponding to the port number connected to the interconnection network 12. The cache CM1 is' 000 'and the cache CM2 is'. 00
1 ', cache CM3 is'010', cache CM
4 is '011', memory MM1 is '100', memory M
M2 is "101", memory MM3 is "110", and memory MM4 is "111". In addition, each memory MM
i manages an area in which the upper 2 bits of the address match the lower 2 bits of its own device number. Memory MM
2 manages an area in which the upper 2 bits of the address are "01".

Next, referring to FIG. 2, a cache CMi according to the present invention includes a tag memory 22 that holds information about blocks such as tag states, a cache memory 25 that holds data in block units, and a processor P.
A memory access management unit 21 that holds and manages memory access from Ri, a first message receiving unit 26 that receives a message delivered by the interconnection network 12, and a first message transmission unit that transmits a message to the interconnection network 12. The message transmission unit 27, the first data control unit 24 for accessing the cache memory 25, and the memory access management unit 21.
In order to perform the processing for data consistency maintenance control on the memory access held by the first message receiving unit 26 and the message held by the first message receiving unit 26,
A function of reading and writing the information stored in, and a control function of instructing the first data control unit 24 to access the cache memory 25,
The first consistency maintaining controller 23 has a function of instructing the first message transmitter 27 to send a message.

Next, referring to FIG. 3, a memory MMi according to the present invention includes a directory memory 43 for holding information about blocks such as a directory state and a directory map, and a main memory 4 for holding data.
6, a second message receiving unit 41 for receiving the message delivered by the interconnection network 12, and the interconnection network 12
Second message sending unit 42 for sending a message to
Stored in the directory memory 43 in order to perform processing for maintaining data consistency with respect to the first data control unit 24 that accesses the main memory 46 and the message held in the second message receiving unit 41. The function of reading and writing the stored information, and the control function of the main memory 4 with respect to the second data control unit 45.
6 having a function of instructing access of No. 6 and a function of instructing the second message transmitting unit 42 to transmit a message.
It is composed of a consistency maintenance control unit 44.

Next, in the data consistency maintenance control method according to the first embodiment, the tag state held in the tag memory 22 represents the state of the block stored in the cache memory 25. It consists of four states, S, E, and D, and has the following meanings. The I state indicates that the latest block does not exist in the cache memory 25. The S state suggests that the latest block exists in the cache memory 25 and may exist in another cache memory 25, that is, the block may be shared. The E state indicates that the latest block exists in the cache memory 25 and the latest block also exists in the main memory 46, but does not exist in the other cache memories 25. The D state indicates that the latest block exists in the cache memory 25, and neither the other cache memory 25 nor the main memory 46 has the latest block. Also, the cache memory 2
In 5, the initial value of the tag state is I, and the cache memory 25 does not have the latest block.

Further, in the data consistency maintenance control method according to the first embodiment, the directory map held in the directory memory 43 represents the cache CMi holding the corresponding block in the main memory 46. For example, the document (“A New Solution
to Coherency Problems in M
ulticache Systems "LUCIEN
M. CENSIER and PAUL FEAUTRI
ER, IEEE Transactions on C
omputers, p1112-1118, Decem
1978). The full map method is used for each cache CMi
Is provided to indicate whether the cache CMi holds or does not hold a block, and in the system of FIG. 1, the directory map is composed of 4 bits. FIG. 4 shows the relationship between the value of the directory map and which cache CMi holds the block. In FIG. 4, ∘ indicates holding, and x indicates not holding. As is apparent from the figure, when the 0th bit of the directory map is 1, it indicates that the cache CM1 holds the block, and when the 1st bit is 1, the cache CM2 indicates the second
If the bit is 1, the cache CM3 and the third bit are 1
Indicates that the cache CM 4 holds each block. Further, in the directory memory 43, the initial value of the directory map is “0000”, and no cache CMi holds the block.

Further, in the data consistency maintenance control method according to the first embodiment, the directory state stored in the directory memory 43 represents the state of the corresponding block stored in the main memory 46.
It consists of four states of C, M, RMP, and WSP, and has the following meanings. C state is the main memory 46
Indicates that the latest block exists in the cache and the cache CMi indicated by the directory map may hold data. In this state, the directory map can take all 16 types of values shown in FIG. The M state indicates that the latest block may not exist in the main memory 46, and that only one cache CMi indicated by the directory map may hold the latest block. In this state, the directory map is' 000
4'1 ',' 0010 ',' 0100 ',' 1000 '
Only the seed value can be taken. The RMP state receives the RM message described later when in the M state, issues the FR message to only one cache CMi indicated in the directory map, and waits for the FD or ACK message from that cache CMi to arrive. Indicates that you are In this state, the directory map is' 000
4'1 ',' 0010 ',' 0100 ',' 1000 '
Only the seed value can be taken. In the WSP state, an IV message is received for all cache CMi that may receive the data indicated by the directory map, except for the cache CMi that issued the WS message and received the WS message described later in the C state. Issued to represent waiting for the arrival of ACK messages from all of those caches CMi. In this state, the directory map can take only three kinds of values of "0011" or "0010" or "0001". Further, this value does not represent the cache CMi to be held,
'0011' represents waiting for the arrival of 3 ACKs, '0010' represents waiting for the arrival of 2 ACKs, and '0001' represents the arrival of 1 ACK. It means that. The initial value of the directory state in the directory memory 43 is C, and the latest block exists in the main memory 46.

Further, according to the data consistency maintenance control method in the first embodiment, the cache CMi and the memory MM are
Messages exchanged between i include RM, WS,
WB, FR, IV, FD, ACK, SDR, EDR, C
There are 11 types of messages, R and NCR, which have the following meanings.

The RM message is a read request message issued from the cache CMi to the memory MMi when a cache miss occurs. The WS message is a write request message issued from the cache CMi to the memory MMi when write sharing occurs. The data written by the processor is added to this WS message. WB
The message is a write-back message that is issued when the block to be replaced is written back. This W
The block to be replaced is added to the B message. The FR message is a write-back request message issued by the memory MMi receiving the RM message to the cache CMi holding the latest block. The IV message is an invalidation request message issued by the memory MMi receiving the WS message to the cache CMi holding the block. The FD message is the cache CM that received the FR message.
i is a write-back message issued to the memory MMi. This FD message contains a cache CM
The latest block held by i is added. ACK
The message is a response message issued to the memory MMi by the cache CMi that has received the FR or IV message. SDR and EDR messages are
The memory MMi is a response message that notifies the cache CMi that issued the RM message that the processing for the data consistency maintenance control for the RM message has been completed in the memory MMi. This SDR and ED
The latest block is added to the R message. CR
The message is a response message in which the memory MMi notifies the cache CMi that issued the WS message that the processing for the WS message has been completed in the memory MMi. The NCR message is a message notifying the cache CMi that issued the RM or WS message when the RM or WS message cannot be processed in the memory MMi.

The message is composed of a header part and a data part, and includes RM, FR, IV, ACK, CR and NCR.
The six types of messages are composed only of the header part. The WS message is composed of a header part and a data part composed of data written by the processor.
The four types of messages, WB, FD, SDR, and EDR, are composed of a header part and a data part composed of data in block units.

The structure of the message header section will be described with reference to FIG.

The message header is composed of five fields: destination device number, message identifier, address, and request source device number. The destination device number field is a cache CM connected to which port of the interconnection network 12.
i or a message to be delivered to the memory MMi. For example, in the case of "101", the message is delivered to the memory MM2 connected to the port 5. The message identifier field indicates which of the 11 types of messages the message is. Identify 11 types of messages. The address field indicates to which address each message is addressed. The request source device number field indicates by which processor PRi each message originated in the memory access performed by the device number of the cache CMi connected to the processor PRi. For example, if the message originates from the memory access made by the processor PR1, the request source device number of the message is '000'.

Next, in the data consistency maintenance control method according to the first embodiment, the processor PR1 causes the memory MM2 to operate.
Taking the case of accessing the data of 1. as an example, a series of operations for data consistency maintenance control performed by the access will be described with reference to the drawings.

First, when the processor PR1 issues a memory access, the memory access management unit 21 fetches the memory access inside. What is fetched is a memory access command for identifying read access or write access, an address indicating an access target, and data in the case of write access. The command and address are supplied to the first consistency maintenance control unit 23, and the data is supplied to the first data control unit 24.

The first consistency maintenance control unit 23 detects that the memory access management unit 21 has fetched the memory access, and based on the memory address stored in the memory access management unit 21, the tag state of the corresponding block. Is read from the tag memory 22 and what value is to be processed is determined based on the value.

First, the operation when the tag state is "I", that is, when there is a cache miss will be described.

In this case, if there is no free space in the cache memory 25 for fetching the block of the memory accessed address, it is necessary to replace it with another block already existing in the cache memory 25. If the replacement is not necessary, the first consistency maintenance control unit 23 starts from the process of transmitting the RM message to the memory MMi (here, the memory MM2) specified by the address.

If replacement is necessary and the tag state of the block to be replaced is'D ',
Since this block is the only newest block in the system, it is necessary to first perform the write-back process on the memory MMi that manages the block. 6 and 7 show the sequence flow in this case. The figure shows a case where the block to be replaced is a block managed by the memory MM3.

The first consistency maintenance control section 23 first generates the header section of the WB message, and then the first message transmission section 27.
To supply. The destination device number of the message header generated at this time is '110' indicating the memory MM3, the message identifier is the identifier indicating WB, the address is the address of the block to be replaced, and the request source device number is the cache concerned. '000' that represents the device number of CM1
become. Further, the first coherence maintenance control unit 23 instructs the first data control unit 24 to read the block that is the replacement target from the cache memory 25, and the read block is the first message transmission unit. 27 to WB
Supplied as the data part of the message. The first message sending unit 27 sends the message to the mutual connection network 12 together with the header part supplied from the first consistency maintenance control unit 23 and the data part supplied from the first data control unit 24. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the block which is the replacement target to “I”.

The transmitted WB message is delivered by the mutual connection network 12 and taken into the second message receiving unit 41 of the memory MM3. The header part of the fetched message is supplied to the second consistency maintenance control part 44, and the data part is supplied to the second data control part 45.

The second consistency maintenance control unit 44 of the memory MM3
Detects that the WB message has been taken into the second message receiving unit 41, and from the address of the header portion stored in the second message receiving unit 41, the directory state and the directory map of the corresponding block from the directory memory 43. It is read, and what kind of processing is performed is determined according to the value. At this time, the possible values of the directory state are limited to'M 'or'RMP' in the method.

If the directory state is M,
The sequence is shown in FIG. Second consistency maintenance control unit 4
4 writes in the directory memory 43, and updates the directory state to C and the directory map to '0000' indicating that no cache CMi holds the block. Further, the second consistency maintenance control unit 44 causes the second data control unit 45 to write the block added to the WB message to the corresponding block of the main memory 46.

When the directory state is RMP, the sequence is as shown in FIG. The second consistency maintenance control unit 44 only causes the second data control unit 45 to write the block added to the WB message to the corresponding block of the main memory 46, and the directory memory 4
3 is not updated.

The above is the sequence in the case where replacement is necessary and the tag state of the block to be replaced is'D '.

Next, when the replacement is necessary and the tag state of the block that is the replacement target is other than'D ', the first consistency maintenance control unit 23 causes the tag memory 22 to operate.
Is written, and the tag state of the block that has been rewritten is updated to'I '.

When the replacement processing is completed in the first consistency maintenance control unit 23, the first consistency maintenance control unit 23 generates the header part of the RM message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is "10" indicating the memory MM2.
1 ', the message length is the length of the RM message,
The message identifier is an identifier representing RM, the address is an address stored in the memory access management unit 21,
The request source device number is "000" indicating the device number of the cache CM1. The first message transmission unit 27 sends the header portion supplied from the first consistency maintenance control unit 23 as a message to the mutual connection network 12 (FIG. 8, FIG. 9, FIG.
Sequence common to FIGS. 10, 11, and 12).

The RM message sent out is delivered by the mutual connection network 12 and taken into the second message receiving unit 41 of the memory MM2. The header part of the fetched message is supplied to the second consistency maintenance control unit 44.

The second consistency maintenance control unit 44 of the memory MM2
Detects that the RM message has been taken in by the second message receiving unit 41, and from the address of the header portion stored in the second message receiving unit 41, the directory state and the directory map of the corresponding block are read from the directory memory 43. It is read, and what kind of processing is performed is determined according to the value.

The directory state is C, and the value of the directory map is held in a block other than the cache CMi that issued the RM message (identified from the request source device number added to the message, and in this case, the cache CMi). Cache CMi that does not exist (here, the directory map is' 0
The sequence shown in FIG. 8 is obtained (in the case of 000 'or' 0001 ').

The second consistency maintenance control unit 44 first determines the EDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is EDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
To the second data control unit 45, the main memory 46
To read the block specified by the address of the message header section stored in the second message receiving section 41. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data portion of the EDR message. Second message sending unit 42
Sends the message to the mutual connection network 12 by combining the header part supplied from the second consistency maintenance control part 44 and the data part supplied from the second data control part 45. Also,
The second consistency maintenance control unit 44 uses the directory memory 43.
Is written, and the directory state is changed to M and the directory map is changed to '0001'. The value of this directory map is a value obtained as a result of performing the operation of setting the bit corresponding to the cache CM1 that issued the RM message to "1" and setting the other bits to "0".

The sent EDR message is delivered by the mutual connection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44,
The data section is supplied to the first data control section 24.

The first coherency maintenance control unit 23 of the cache CM 1 detects that the EDR message is fetched by the first message receiving unit 26, and the first data control unit 24 sends the EDR message to the cache memory 25. It is instructed to take in the block data added to. In addition, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the corresponding block to “E”.

After that, the first consistency maintenance control unit 23 again evaluates the memory access stored in the memory access management unit 21 and performs the necessary processing for maintaining the data consistency.

Next, the second consistency maintenance control unit 44 of the memory MM2 that has received the RM message reads the directory state and the directory map of the corresponding block of the directory memory 43, and as a result, the directory state is C and the directory is Map value is RM
When it indicates that there is a cache CMi that holds a block other than the cache CMi that issued the message (here, the cache CM1) (here, since the cache CM1 issues the RM message, the directory map is' 0000. The sequence shown in FIG. 9 is obtained in the case other than'or '0001).

The second consistency maintenance control unit 44 first determines the SDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is SDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
To the second data control unit 45, the main memory 46
To read the block specified by the address of the message header section stored in the second message receiving section 41. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data portion of the SDR message. Second message sending unit 42
Sends the message to the mutual connection network 12 by combining the header part supplied from the second consistency maintenance control part 44 and the data part supplied from the second data control part 45. Also,
The second consistency maintenance control unit 44 uses the directory memory 43.
Is written, and the directory state is changed to C and the value of the directory map is changed to “1101”. The value of this directory map is "1" for the bit corresponding to the cache CM1 specified by the request source device number stored in the second message receiving unit 41, with respect to the value of the directory map immediately before receiving the RM message. This is the value obtained as a result of performing the operation.

The sent SDR message is delivered by the mutual connection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44,
The data section is supplied to the first data control section 24.

The first coherency maintenance control unit 23 of the cache CM 1 detects that the SDR message has been taken in by the first message receiving unit 26, and the first data control unit 24 sends the SDR message to the cache memory 25. It is instructed to take in the block data added to. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the corresponding block to'S '.

The first consistency maintenance control unit 23 then evaluates the memory access stored in the memory access management unit 21 again, and performs the necessary processing for maintaining the data consistency.

Next, when the second consistency maintenance control unit 44 of the memory MM2 receiving the RM message reads the directory state and the directory map of the corresponding block of the directory memory 43, and the directory state is M, , Or the sequence shown in FIG. In this case, the directory map uniquely determines the cache CMi holding the latest block. In the example shown in FIG. 10 and FIG. 11, the value of the directory map is “0100”, so it can be confirmed that the cache CM3 holds only the latest data.

The second consistency maintenance control unit 44 first generates the header portion of the FR message and then the second message transmission unit 42.
To supply. The destination device number of the message header generated at this time is the cache CM holding the latest block.
3 becomes '010', the message identifier is an identifier representing FR, the address and the request source device number are the address of the message header part stored in the second message receiving unit 41 and the request source device number (here, "00").
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message. Also, the second
The consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to RMP, but leaves the directory map as it is.

The FR message transmitted is the mutual connection network 1
2 and is received by the first message receiving unit 26 of the cache CM 3. The header part of the fetched message is supplied to the second consistency maintenance control unit 44.

The first consistency maintenance control unit 23 of the cache CM 3 detects that the FR message has been fetched into the first message receiving unit 26, and from the address of the header portion stored in the first message receiving unit 26. , The tag state of the corresponding block is read from the tag memory 22, and what value to perform is determined based on the value. At this time, the value that the tag state can take is'I 'or'E'.
Or it can be'D 'and'S'.

When the tag state is "E" or "D" and the latest block exists, the sequence is as shown in FIG.

The first consistency maintenance control section 23 first generates the header section of the FD message, and then the first message transmission section 27.
To supply. The destination device number of the message header generated at this time is the device number representing the memory MMi specified from the address of the header part stored in the first message receiving unit 26 (here, the memory MM2 is specified from the address and the destination device number is specified). The number is "101"), the message identifier is an identifier representing the FD, the address and the request source device number are the address of the message header part and the request source device number stored in the second message receiving unit 41 (here, " 000 '). In addition, the first consistency maintenance control unit 23 instructs the first data control unit 24 to read the block specified from the address stored in the first message receiving unit 26 from the cache memory 25, and reads the block. The issued block is supplied to the first message transmitting unit 27 as the data portion of the FD message. The first message transmission unit 27 includes a header unit supplied from the first consistency maintenance control unit 23 and the first data control unit 2
The data part supplied from 4 together, the mutual connection network 12
Send a message to. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the corresponding block to'S '.

The transmitted FD message is the mutual connection network 1
2 and is received by the second message receiving unit 41 of the memory MM2. The header part of the fetched message is supplied to the second consistency maintenance control part 44, and the data part is supplied to the second data control part 45.

The second consistency maintenance control unit 44 of the memory MM2
Detects that the FD message has been taken into the second message receiving unit 41, and from the address of the header portion stored in the second message receiving unit 41, the directory state and the directory map of the corresponding block from the directory memory 43. read out. At this time, the value that the directory state can take is limited to'RMP 'in the method.

The second consistency maintenance control unit 44 first determines the SDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is SDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
Causes the second data control unit 45 to write the block added to the FD message to the corresponding block of the main memory 46. The second data control unit 45 performs writing to the main memory 46, and at the same time, supplies the block added to the FD message to the second message transmission unit 42 as the data portion of the SDR message.
The second message transmission unit 42 uses the second consistency maintenance control unit 4
A message is sent to the mutual connection network 12 by combining the header part supplied from No. 4 and the data part supplied from the second data control unit 45. In addition, the second consistency maintenance control unit 44
Writes to the directory memory 43, sets the directory state to C, and sets the value of the directory map to '1.
Transition to 101 '. The value of this directory map is the cache CM1 specified from the request source device number stored in the second message receiving unit 41 with respect to the value of the directory map immediately before receiving the FD message.
It is a value obtained as a result of performing the operation of setting the bit corresponding to to "1".

The sent SDR message is delivered by the mutual connection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the first consistency maintenance control unit 23,
The data section is supplied to the first data control section 24.

When the first consistency maintenance control unit 23 of the cache CM1 detects that the SDR message has been fetched by the first message receiving unit 26, the cache CM1 sends the SDR message in the sequence shown in FIG. It is the same as when you received it.

Next, when the first coherency maintenance control unit 23 of the cache CM3 that has received the FR message reads the tag state of the corresponding block of the tag memory 22 and the tag state is'I ', The sequence is shown in FIG.

The first consistency maintenance control unit 23 first sends an ACK.
Generates a header part of the message and sends the first message sending part 2
7 The destination device number of the message header generated at this time is the device number representing the memory MMi specified from the address of the header part stored in the first message receiving unit 26 (here, from the address to the memory MM2.
Is 101), the message identifier is an identifier indicating ACK, and the address and request source device number are the address and request source of the message header part stored in the second message receiving unit 41. It becomes the device number (here, it is '000'). The first message transmission unit 27 sends the header portion supplied from the first consistency maintenance control unit 23 to the mutual connection network 12 as a message.

The sent ACK message is delivered by the mutual connection network 12 and taken into the second message receiving unit 41 of the memory MM2. The header part of the fetched message is supplied to the second consistency maintenance control unit 44.

The second consistency maintenance control unit 44 of the memory MM2
Detects that the ACK message has been fetched by the second message receiving unit 41, and from the address of the header portion stored in the second message receiving unit 41, the directory state and the directory map of the corresponding block are read from the directory memory 43. read out. At this time, the possible values of the directory state are'WSP 'and'RM
Although limited to P ', here, the case where the directory state is'RMP' is described in the sequence shown in FIG.

The second coherence maintenance control section 44 first determines the EDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is EDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
To the second data control unit 45, the main memory 46
To read the block specified by the address of the message header section stored in the second message receiving section 41. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data portion of the EDR message. Second message sending unit 42
Sends the message to the mutual connection network 12 by combining the header part supplied from the second consistency maintenance control part 44 and the data part supplied from the second data control part 45. Also,
The second consistency maintenance control unit 44 uses the directory memory 43.
Is written, and the directory state is changed to M and the directory map is changed to '0001'. The value of this directory map is the second message receiving unit 41.
Cache CMi specified by the request source device number of the message header section stored in
It is a value obtained as a result of performing the operation of setting the bit corresponding to M1) to "1" and setting the other bits to "0".

The sent EDR message is delivered by the mutual connection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44,
The data section is supplied to the first data control section 24.

The operation when the first consistency maintenance control unit 23 of the cache CM1 detects that the EDR message is captured by the first message receiving unit 26 is the same as the cache CM1 in the sequence shown in FIG. It is the same as when you received it.

Next, the second consistency maintenance control unit 44 of the memory MM2 having received the RM message reads the directory state and the directory map of the corresponding block of the directory memory 43, and as a result, the directory state is'RMP 'or' If it is WSP ′, the sequence is as shown in FIG.

The second consistency maintenance control unit 44 first determines the NCR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is NCR.
Is the second identifier in the address and the request source device number.
The address of the message header portion supplied to the message receiving unit 41 and the request source device number (here, “00”).
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message.

The sent NCR message is delivered by the mutual connection network 12 and taken into the first message receiving unit 26 of the cache CM 1. The header part of the fetched message is supplied to the first consistency maintenance control unit 23.

The first consistency maintenance control unit 23 of the cache CM1 detects that the NCR message has been fetched by the first message receiving unit 26 and evaluates the memory access stored in the memory access management unit 21 again. , Perform necessary processing to maintain data consistency.

The above is the operation for maintaining the data consistency in the case of a cache miss.

Next, it is detected that the memory access is taken into the memory access management unit 21, and the tag state of the corresponding block is read from the tag memory 22 from the access stored in the memory access management unit 21. The operation when the memory access fetched by the memory access management unit 21 is read and the tag state is “S”, “E”, or “D” (in the case of read hit) will be described.

The first consistency maintenance control unit 23 can read the data specified by the address stored in the memory access management unit 21 from the cache memory 25 to the first data control unit 24. The read data is supplied to and fetched by the memory access management unit 21. The data fetched by the memory access management unit 21 is the processor P.
It is supplied to R1. Further, the first consistency maintenance control unit 23 sends a memory access completion response to the processor PR1, causes the processor PR1 to fetch the data supplied by the memory access management unit 21, and completes the read access.

Next, it is detected that the memory access is taken into the memory access management unit 21, and the tag state of the corresponding block is read from the tag memory 22 from the address stored in the memory access management unit 21. The operation when the memory access fetched by the memory access management unit 21 is writing and the tag state is “E” or “D” will be described (in the case of a write hit).

The first coherence maintenance control unit 23 supplies the first data control unit 23 with the data specified by the address output from the memory access management unit 21 of the cache memory 25 by the memory access management unit 21. To rewrite. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state to'D '. Further, the first consistency maintenance control unit 23 sends a memory access completion response to the processor PR1 to complete the write access.

Next, it is detected that the memory access is taken into the memory access management unit 21, and the tag state of the corresponding block is read from the tag memory 22 from the address stored in the memory access management unit 21. The operation when the memory access fetched by the memory address management unit 21 is writing and the tag state is'S 'will be described (in the case of write shared).

The first consistency maintenance control section 23 first generates the header section of the WS message, and then the first message transmission section 27.
To supply. The destination device number of the message header generated at this time is "101" indicating the memory MM2, the message identifier is the identifier indicating WS, the address is the address stored in the memory access management unit 21, and the request source device number is It becomes "000" which represents the device number of the cache CM1. In addition, the first consistency maintenance control unit 23
Causes the first data control unit 24 to rewrite the data specified by the address output by the memory access management unit 21 of the cache memory 25 with the data supplied by the memory access management unit 21. At this time, the first data control unit 2
4 writes the data supplied by the memory access management unit 21 into the cache memory 25 and, at the same time, supplies it to the first message transmission unit 27. First message sending unit 27
Sends the message to the mutual connection network 12 by combining the header section supplied from the first consistency maintenance control section 23 and the data section supplied from the first data control section 24.

The transmitted WS message is the mutual connection network 1
2 and is received by the second message receiving unit 41 of the memory MM2. The header part of the fetched message is supplied to the second consistency maintenance control part 44, and the data part is supplied to the second data control part 45.

The second consistency maintenance control unit 44 of the memory MM2
Detects that the WS message has been taken in by the second message receiving unit 41, and from the address of the header portion stored in the second message receiving unit 41, the directory state and the directory map of the corresponding block are read from the directory memory 43. read out. At this time, the value that the directory state can take is'C 'or'WS due to the method.
Limited to P '. When the directory state is C, the bit of the directory map corresponding to the cache CM1 that issued the WS message is always "1".

A cache CM which holds a block other than the cache CMi whose directory state is'C 'and the value of the directory map issued the WS message.
When i indicates that i does not exist (here, since the cache CM1 issues the WS message, the directory map is "0001"), the sequence is as shown in FIG.

The second consistency maintenance control unit 44 first generates the header portion of the CR message, and then the second message transmission unit 42.
To supply. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier represents CR. In the identifier, the address and the request source device number are the address and the request source device number of the message header part stored in the second message receiving unit 41 (here, “000”).
It becomes). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message. Further, the second consistency maintenance control unit 44 causes the second data control unit 45 to send the data specified by the address output from the second message reception unit 41 of the main memory 46 to the second message reception unit 41.
Rewrite the data supplied by.

The CR message sent is the mutual connection network 1
2 and is received by the first message receiving unit 26 of the cache CM 1. The header part of the fetched message is supplied to the first consistency maintenance control unit 23.

The first coherency maintenance controller 23 of the cache CM1 detects that the CR message has been fetched by the first message receiver 26, sends a memory access completion response to the processor PR1, and executes write access. Let it complete.

Next, the second consistency maintenance control unit 44 of the memory MM2 receiving the WS message reads the directory state and directory map of the corresponding block of the directory memory 43, and as a result, the directory state is C, and When the value of the directory map indicates that there is a cache CMi that holds the block other than the cache CMi that issued the WS message (here, since the cache CM1 issues the WS message, the value of the directory map is 00
The sequence shown in FIG. 14 is the case other than 01 '. In the following, in the example shown in FIG. 14, the case where the value of the directory map when the WS message is received is, for example, “1101” will be described.

The second coherency maintenance control unit 44 first checks whether or not the cache CM1 holds the latest block and is not the cache CMi which issued the WS message. At this time, since the cache CM1 is the cache CMi that has issued the WS message from the request source device number stored in the second message receiving unit 41, nothing is done in this case.

Next, the second consistency maintenance control unit 44 determines that the cache CM2 holds the latest block and WS
It is checked whether it is not the cache CMi that issued the message. At this time, the value of the directory map is '11
From 01 ', since the cache CM2 does not hold the latest data, nothing is done also in this case.

Next, the second consistency maintenance control unit 44 determines that the cache CM3 holds the latest block and WS
It is checked whether it is not the cache CMi that issued the message. At this time, since the cache CM3 holds the latest block and is not the cache CMi that issued the WS message, the following processing is performed. The second consistency maintenance control unit 44 generates the header part of the IV message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is “010” indicating the cache CM3, the message identifier is the identifier indicating IV, and the address and the request source device number are the messages stored in the second message receiving unit 41. The address of the header and the request source device number (here, “000”) are used. Second message sending unit 42
Sends the header part supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message.

Next, the second coherency maintenance control unit 44 determines that the cache CM 4 holds the latest block and WS.
It is checked whether it is not the cache CMi that issued the message. At this time, since the cache CM 4 holds the latest block and is not the cache CMi that issued the WS message, the cache CM 3 described above is used.
The header part of the IV message is generated as in the case of
However, the destination device number is "01" which represents the cache CM4.
1 '.

Finally, the second consistency maintenance control unit 44 causes the second data control unit 45 to send the data specified by the address output from the second message reception unit 41 of the main memory 46 to the second message reception unit. The data supplied by 41 is rewritten. Further, the second consistency maintenance control unit 44 writes the directory memory 43, and changes the directory state to “WSP” and the directory map to “0010”. The value of this directory map represents the number of transmitted IV messages.

The two IV messages sent out are delivered by the mutual interconnection network 12 and cache CM3 respectively.
And the first message receiving unit 26 of the cache CM4. The header part of the fetched message is supplied to the second consistency maintenance control part 44, and the data part is supplied to the first data control part 24.

The first consistency maintenance control unit 23 of the cache CM 3 detects that the IV message has been taken in by the first message receiving unit 26, and from the address of the header unit stored in the first message receiving unit 26. , The tag state of the corresponding block is read from the tag memory 22, and what value to perform is determined based on the value. At this time, the possible values of the tag state are'I 'or'S'.
Is limited to

If the tag state is'I ', the first
The consistency maintenance control unit 23 first generates the header part of the ACK message and supplies it to the first message transmission unit 27. The destination device number of the message header generated at this time is the first
The device number represents the memory MMi specified from the address of the header part stored in the message receiving unit 26 (here, the memory MM2 is specified from the address and the destination device number is '101'), and the message identifier is AC.
In the identifier indicating K, the address and the request source device number are the address and the request source device number (here, “0” in the message header part stored in the second message receiving unit 41).
00 '). The first message sending unit 27
The header portion supplied from the first consistency maintenance control unit 23 is sent to the mutual connection network 12 as a message.

When the tag state is'S ', the first consistency maintenance control section 23 first generates the header section of the ACK message and supplies it to the first message transmission section 27. The destination device number of the message header generated at this time is the device number representing the memory MMi specified from the address of the header part stored in the first message receiving unit 26 (here, the memory MM2 is specified from the address and the destination device number is specified). The number is' 101 '), the message identifier is an identifier indicating ACK, the address and the request source device number are the address of the message header part stored in the second message receiving unit 41 and the request source device number (here,' 000 '). The first message transmission unit 27 sends the header portion supplied from the first consistency maintenance control unit 23 to the mutual connection network 12 as a message. Further, the first consistency maintenance control unit 23 writes the tag memory 22 and updates the tag state of the corresponding block to “I”.

The sent ACK message is delivered by the mutual connection network 12 and taken into the second message receiving unit 41 of the memory MM2. The header part of the fetched message is supplied to the second consistency maintenance control unit 44.

The second consistency maintenance control unit 44 of the memory MM2
Detects that the ACK message has been fetched by the second message receiving unit 41, and from the address of the header portion stored in the second message receiving unit 41, the directory state and the directory map of the corresponding block are read from the directory memory 43. read out. At this time, the possible values of the directory state are'WSP 'and'RM
Although limited to P ', here, the case where the directory state is'WSP' is described in the sequence shown in FIG. At this time, different processing is performed depending on whether the value of the directory map is '0001' or not.

When the directory state is "WSP" and the directory map is not "0001" (here, "0010". In this case, the ACK message issued by the cache CM3 is received in the sequence shown in FIG. ), The second consistency maintenance control unit 44
The directory memory 43 is written and the directory state is set to'WSP 'as it is, but the directory map is updated to a value obtained by decrementing the values of all directory maps (here, it is'0001').

Next, the directory state is'WSP '.
In the case where the value of the directory map is '0001' (when the ACK message issued by the cache CM 4 is received in the sequence shown in FIG. 14), the second
The consistency maintenance control unit 44 first generates the header part of the CR message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is the second
It is the request source device number of the message header part stored in the message receiving unit 41 (in this case, '000'), the message identifier is an identifier representing CR, and the address and the request source device number are the second message receiving unit. 41
The address of the message header and the request source device number (here, “000”) stored in
The second message transmission unit 42 uses the second consistency maintenance control unit 4
The header portion supplied from No. 4 is sent to the interconnection network 12 as a message. In addition, the second consistency maintenance control unit 44
Writes to the directory memory 43 and sets the directory state to M and the directory map to '0.
Transition to 001 '. In the value of this directory map, the bit corresponding to the cache CMi (here, the cache CM1) specified by the request source device number of the header part stored in the second message receiving unit 41 is set to "1", and other values are set. It is a value obtained as a result of the operation of setting the bit to “0”.

The CR message sent is the mutual connection network 1
2 and is received by the first message receiving unit 26 of the cache CM 1. The header part of the fetched message is supplied to the second consistency maintenance control part 44, and the data part is supplied to the first data control part 24.

The operation when the first consistency maintenance control unit 23 of the cache CM1 detects that the CR message is fetched by the first message receiving unit 26 is the same as the operation shown in FIG. It is the same as when you received it.

Next, the second consistency maintenance control unit 44 of the memory MM2 receiving the WS message reads the directory state and directory map of the corresponding block of the directory memory 43, and as a result, the directory state is'WSP '. If so, the sequence is as shown in FIG. At this time, the same block is already accepting a WS message from another cache CMi, and when the WS message is processed, the memory MM2 transmits an IV message to the cache CM1. . As a result, the cache CM1
In, the tag state of the block stored in the tag memory 22 is updated from'S 'to'I'.

The second consistency maintenance control unit 44 first determines the NCR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is NCR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message.

The sent NCR message is delivered by the mutual connection network 12 and taken in by the first message receiving unit 26 of the cache CM1. The header part of the fetched message is supplied to the first consistency maintenance control unit 23.

The operation when the first consistency maintenance control unit 23 of the cache CM1 detects that the NCR message is fetched by the first message receiving unit 26 is the same as the cache CM1 in the sequence shown in FIG. It is the same as when you received it.

Next, the effect of the first embodiment of the present invention will be described.

For example, the cache CM1 and the cache C
Consider the operation when the processor PR1 performs writing and then the processor PR4 performs reading while the block of the memory MM2 exists in M3 and is shared. The writing performed by the processor PR1 is reflected in the cache CM1 and the memory MM2, so that the latest data exists in the cache CM1 and the memory MM2.

Therefore, when the processor PR4 next performs a read operation, a read request message is sent to the memory MM2. However, since the latest data exists in the memory MM2, the memory MM2 immediately updates the cache CM1. You can send a message with the block of. Therefore, in the memory MM2, there is no processing for requesting write-back to the cache CMi that only holds the latest block and receiving the response, and shortening the time until the processor PR4 responds to the read data. You can Further, since it is not necessary to request write back, the number of messages exchanged between the cache and the memory for maintaining the data consistency can be reduced.

Next, in the data consistency maintenance control method according to the second embodiment, the tag states stored in the tag memory 22 are I and S, as in the data consistency maintenance control method according to the first embodiment. , E, and D.
Further, the directory map stored in the directory memory 43 is also configured by the full map method of 4 bits. Also the directory state is C, M, RMP, WS
It consists of 4 states of P.

In the data consistency maintenance control method according to the second embodiment, the message exchanged between the cache CMi and the memory MMi contains the RM of the data consistency maintenance control method according to the first embodiment. , WS, W
B, FR, IV, FD, ACK, SDR, EDR, C
ECR messages are newly added to 11 types of R and NCR messages, and 12 types of messages exist. Like the CR message, the ECR message is a response message that notifies the cache CMi that the memory MMi has issued the WS message that the processing for the WS message has been completed in the memory MMi.

Next, in the data consistency maintaining control method according to the second embodiment, the processor PR1 causes the memory MM2 to operate.
Taking the case of accessing the data described above as an example, a series of operations for maintaining the data consistency performed by the access will be shown only in the points different from the data consistency maintenance control method in the first embodiment.

The operation of the data consistency maintenance control method according to the second embodiment is different from that of the data consistency maintenance control method according to the first embodiment in that the second operation of the memory MM2 receiving the WS message is different. Consistency maintenance control unit 44
As a result of reading the directory state and the directory map of the corresponding block in the directory memory 43, the directory state is C, and the cache CMi that holds the block exists in addition to the cache CMi that issued the WS message. In case of not performing (here, cache CM
1 is issuing the WS message, the value of the directory map is '0001'.). That is, in the data consistency maintenance control method according to the first embodiment, the sequence shown in FIG. 13 is obtained.

In this case, the data consistency maintenance control method according to the second embodiment takes the sequence shown in FIG.

The second coherence maintenance control unit 44 first determines the ECR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is ECR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message. Further, the second consistency maintenance control unit 44 supplies the second data control unit 45 with the data specified by the address output by the second message reception unit 41 of the main memory 46. Rewrite with data. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and changes the directory state to M and the directory map to '0001'. The value of this directory map is a value obtained as a result of performing the operation of setting the bit corresponding to the cache CM1 that issued the RM message to "1" and setting the other bits to "0".

The sent ECR message is delivered by the mutual connection network 12 and taken into the first message receiving unit 26 of the cache CM1. The header part of the captured message is supplied to the second consistency maintenance control unit 44,
The data section is supplied to the first data control section 24.

The first consistency maintenance control unit 23 of the cache CM1 writes the tag memory 22 and updates the tag state of the corresponding block from'S 'to'E'.
In addition, the first consistency maintenance control unit 23 uses the processor PR1.
To the memory access completion response to complete the write access.

Next, the effect of the second embodiment of the present invention will be described.

For example, when the block state of the cache CM1 is the shared state and the latest block exists only in the cache CM1 and the memory MM2, the processor PR is
1 continuously writes, while another processor P
Consider the case where Ri did not access. In this case, in the data consistency maintenance control method according to the first embodiment, a write request message is issued from the cache CM1 to the memory MM2 each time writing is performed, and the number of messages for data consistency maintenance control in this case increases. There is a problem of doing.

In the data consistency maintenance control method according to the second embodiment, in the above case, the write request message is issued from the cache CM1 to the memory MM2 for the first two write operations. Continued 3
No message for data consistency maintenance control is issued for the writing from the second time, and the increase of messages in this case can be prevented.

Next, in the data consistency maintenance control method of the third embodiment, the tag states stored in the tag memory 22 are I and S, as in the data consistency maintenance control method of the second embodiment. , E, and D.
Further, the directory map stored in the directory memory 43 is also configured by the full map method of 4 bits. Also the directory state is C, M, RMP, WS
It consists of 4 states of P.

In the data consistency maintenance control method according to the third embodiment, the update frequency value is held in the directory memory 43 as information about a block in addition to the directory state and the directory map. The update frequency value is the value of the memory MMi when one cache CMi and the memory MMi hold the latest block.
Is a value that counts how many times the WS message is received from the cache CMi that holds the latest block before receiving the RM message from the other cache CMi.

In the data consistency maintenance control method of the third embodiment, the update frequency upper limit value is newly defined as a parameter.

Further, in the data consistency maintenance control method according to the third embodiment, the cache CMi and the memory MMi are used.
The messages exchanged between RM, WS, WB, FR, IV, FD, ACK, S are the same as the messages in the data consistency maintenance control method in the second embodiment.
There are 12 types of messages: DR, EDR, CR, NCR, ECR.

Next, in the data consistency maintaining control method according to the third embodiment, the processor PR1 causes the memory MM2 to operate.
A series of operations for maintaining the data consistency performed by the access will be described by taking the case of accessing the data of FIG.

The operation of the cache CMi in the data coherency maintenance control method of the third embodiment is the same as the operation of the cache CMi in the data coherency maintenance control method of the second embodiment. Then, the explanation is omitted. Hereinafter, the operation of the memory MMi in the data consistency maintenance control method according to the third embodiment will be described with reference to RM, WS,
The description will be made in order when five types of messages of WB, FD, and ACK are received.

The second consistency maintenance control unit 44 of the memory MM2
When detecting that the RM message is captured in the second message receiving unit 41, the directory state and directory map of the corresponding block and the update frequency value are calculated from the address of the header portion stored in the second message receiving unit 41. Read from the directory memory 43,
Depending on the value, what kind of processing should be performed is determined.

The directory state is C, and the value of the directory map is held in a block other than the cache CMi that issued the RM message (identified from the request source device number added to the message, and in this case, the cache CM1). Cache CMi that does not exist (here, the directory map is' 0
000 'or' 0001 '), regardless of the value of the update frequency value, the process shown in FIG. 17 is performed when the memory MM2 receives the RM message from the cache CM1.

The second coherence maintenance control section 44 first determines the EDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is EDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
To the second data control unit 45, the main memory 46
To read the block specified by the address of the message header section stored in the second message receiving section 41. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data portion of the EDR message. Second message sending unit 42
Sends the message to the mutual connection network 12 by combining the header part supplied from the second consistency maintenance control part 44 and the data part supplied from the second data control part 45. Also,
The second consistency maintenance control unit 44 uses the directory memory 43.
Is written, the directory state is updated to M, the directory map is updated to “0001”, and the update frequency value is updated to “0”. The value of this directory map is R
It is a value obtained as a result of the operation of setting the bit corresponding to the cache CM1 that issued the M message to "1" and setting the other bits to "0".

When the directory state is C and the value of the directory map indicates that there is a cache CMi that holds a block other than the cache CMi that issued the RM message (here, cache CM1) (here, cache Since CM1 issues the RM message, the directory map is' 000.
If it is other than 0'or '0001'), regardless of the value of the update frequency value, the process shown in FIG. 18 is performed when the memory MM2 receives the RM message from the cache CM1.

The second consistency maintenance control unit 44 first determines the SDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is SDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
To the second data control unit 45, the main memory 46
To read the block specified by the address of the message header section stored in the second message receiving section 41. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data portion of the SDR message. Second message sending unit 42
Sends the message to the mutual connection network 12 by combining the header part supplied from the second consistency maintenance control part 44 and the data part supplied from the second data control part 45. Also,
The second consistency maintenance control unit 44 uses the directory memory 43.
Is written to update the directory state to C, the value of the directory map to '1101', and the update frequency value to '0'. The value of this directory map is R
The result of performing the operation of setting the bit corresponding to the cache CM1 specified by the request source device number stored in the second message receiving unit 41 to "1" with respect to the value of the directory map immediately before receiving the M message This is the value obtained.

If the directory state is M,
Regardless of the value of the update frequency value, the processing when the memory MM2 receives the RM message from the cache CM1 is performed in the sequence shown in FIGS. 19 and 20. In this case, the cache CMi holding the latest block is uniquely determined from the directory map. 19 and 20.
In the example shown in, the value of the directory map is' 010.
Since it is 0 ′, it can be confirmed that the cache CM 3 holds only the latest data.

The second consistency maintenance control unit 44 first generates the header portion of the FR message and then the second message transmission unit 42.
To supply. The destination device number of the message header generated at this time is the cache CM holding the latest block.
3 becomes '010', the message identifier is an identifier representing FR, the address and the request source device number are the address of the message header part stored in the second message receiving unit 41 and the request source device number (here, "00").
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message. Also, the second
The consistency maintenance control unit 44 writes the directory memory 43 and updates the directory state to RMP and the update frequency value to “0”, but leaves the directory map as it is.

When the directory state is'RMP 'or'WSP', the sequence shown in FIG.
The process when the memory MM2 receives the RM message from the cache CM1 is performed.

The second consistency maintenance control unit 44 first determines the NCR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is NCR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message.

Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the WS message is taken in by the second message receiving unit 41, the header unit stored in the second message receiving unit 41. From the address of, the directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined by the value.

A cache CM holding a block other than the cache CMi in which the directory state is'C 'and the value of the directory map is the WS message.
i does not exist (here, cache CM
1 issues the WS message, the directory map is '0001'.) If the update frequency value does not match the update frequency upper limit value, the memory MM2 causes the cache CM1 to operate in the sequence shown in FIG. From WS
Process when a message is received.

The second consistency maintenance control unit 44 first generates the header portion of the CR message, and then the second message transmission unit 42.
To supply. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'). The message identifier is an identifier representing CR, the address and the request source device number are the address and the request source device number of the message header part stored in the second message receiving unit 41 (here, “000”).
It becomes). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message. Further, the second consistency maintenance control unit 44 causes the second data control unit 45 to send the data specified by the address output from the second message reception unit 41 of the main memory 46 to the second message reception unit 41.
Rewrite the data supplied by. Further, the second consistency maintenance control unit 44 writes to the directory memory 43, leaves the directory state and the directory map as they are, and updates the update frequency value to a value obtained by adding one. In the sequence shown in FIG. 22, the update frequency value is “0”.
Has been updated from '1'.

A cache CM holding a block other than the cache CMi in which the directory state is'C 'and the value of the directory map is the WS message.
i does not exist (here, cache CM
1 has issued the WS message, so the directory map is '0001'.) When the update frequency value matches the update frequency upper limit value, the memory MM2 reads from the cache CM1 in the sequence shown in FIG. Performs processing when a WS message is received. The sequence shown in FIG. 23 is a case where the update frequency upper limit value is set to '2'.

The second consistency maintenance control unit 44 first determines the ECR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is ECR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message. Further, the second consistency maintenance control unit 44 supplies the second data control unit 45 with the data specified by the address output by the second message reception unit 41 of the main memory 46. Rewrite with data. Further, the second consistency maintenance control unit 44 writes in the directory memory 43, updates the directory state to M, the directory map to '0001', and the update frequency value to '0'. The value of this directory map is a value obtained as a result of performing the operation of setting the bit corresponding to the cache CM1 that issued the RM message to "1" and setting the other bits to "0".

A cache CM whose directory state is C and whose directory map value is a block other than the cache CMi which issued the WS message.
If i is present (here, cache C
Since M1 issues the WS message, the value of the directory map is other than '0001'.) Regardless of the update frequency value, the memory MM2 sends the WS message from the cache CM1 in the sequence shown in FIG. Process when received. In the following, in the example shown in FIG. 24, a case where the value of the directory map when the WS message is received is, for example, “1101” will be described.

The second coherency maintenance control unit 44 first checks whether or not the cache CM1 holds the latest block and is not the cache CMi which issued the WS message. At this time, since the cache CM1 is the cache CMi that has issued the WS message from the request source device number stored in the second message receiving unit 41, nothing is done in this case.

Next, the second coherency maintenance control unit 44 determines that the cache CM2 holds the latest block and WS
It is checked whether it is not the cache CMi that issued the message. At this time, the value of the directory map is '11
From 01 ', since the cache CM2 does not hold the latest data, nothing is done also in this case.

Next, the second consistency maintenance control unit 44 determines that the cache CM3 holds the latest block and WS
It is checked whether it is not the cache CMi that issued the message. At this time, since the cache CM3 holds the latest block and is not the cache CMi that issued the WS message, the following processing is performed. The second consistency maintenance control unit 44 generates the header part of the IV message and supplies it to the second message transmission unit 42. The destination device number of the message header generated at this time is “010” indicating the cache CM3, the message identifier is the identifier indicating IV, and the address and the request source device number are the messages stored in the second message receiving unit 41. The address of the header and the request source device number (here, “000”) are used. Second message sending unit 42
Sends the header part supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message.

Next, the second consistency maintenance control unit 44 determines that the cache CM 4 holds the latest block and WS
It is checked whether it is not the cache CMi that issued the message. At this time, since the cache CM 4 holds the latest block and is not the cache CMi that issued the WS message, the cache CM 3 described above is used.
The header part of the IV message is generated as in the case of
However, the destination device number is "01" which represents the cache CM4.
1 '.

Finally, the second consistency maintenance control unit 44 causes the second data control unit 45 to send the data specified by the address output from the second message reception unit 41 of the main memory 46 to the second message reception unit. The data supplied by 41 is rewritten. In addition, the second consistency maintenance control unit 44 writes the directory memory 43, updates the directory state to “WSP”, the directory map to “0010”, and the update frequency value to “0”. The value of this directory map represents the number of transmitted IV messages.

When the directory state is'WSP ', the processing when the memory MM2 receives the WS message from the cache CM1 is performed in the sequence shown in FIG. 25 regardless of the directory map and the update frequency value.

The second consistency maintenance control unit 44 first determines the NCR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is NCR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). The second message transmission unit 42 sends the header portion supplied from the second consistency maintenance control unit 44 to the mutual connection network 12 as a message.

Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the WB message has been taken in by the second message receiving unit 41, the header unit stored in the second message receiving unit 41. From the address of, the directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined by the value. At this time, the possible values of the directory state are limited to'M 'or'RMP' in the method.

When the directory state is'M ', the sequence shown in FIG.
The process when the memory MM3 receives the WB message from the cache CM1 is performed. The second consistency maintenance control unit 44 writes the directory memory 43, sets the directory state to C, the directory map to "0000" indicating that no cache CMi holds a block, and the update frequency value to "0". Update to '. In addition, the second consistency maintenance control unit 44 uses the second data control unit 4
5 causes the block added to the WB message to be written into the corresponding block of the main memory 46.

When the directory state is RMP, the process when the memory MM3 receives the WB message from the cache CM1 is performed in the sequence shown in FIG. 27 regardless of the values of the directory map and the update frequency value. The second consistency maintenance control unit 44 only causes the second data control unit 45 to write the block added to the WB message to the corresponding block of the main memory 46, and does not update the directory memory 43.

Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the FD message is taken in by the second message receiving unit 41, the header unit stored in the second message receiving unit 41. , The directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and the memory MM2 receives the FD message from the cache CM3 in the sequence shown in FIG. 19 regardless of the update frequency value. Do the case. At this time, the value that the directory state can take is limited to'RMP 'in the method.

The second consistency maintenance control unit 44 first determines the SDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is SDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
Causes the second data control unit 45 to write the block added to the FD message to the corresponding block of the main memory 46. The second data control unit 45 performs writing to the main memory 46, and at the same time, supplies the block added to the FD message to the second message transmission unit 42 as the data portion of the SDR message.
The second message transmission unit 42 uses the second consistency maintenance control unit 4
A message is sent to the mutual connection network 12 by combining the header part supplied from No. 4 and the data part supplied from the second data control unit 45. In addition, the second consistency maintenance control unit 44
Writes to the directory memory 43, sets the directory state to C, and sets the value of the directory map to '1.
The update frequency value is updated to 101 'to' 0 '. With respect to the value of this directory map, with respect to the value of the directory map immediately before receiving the FD message, the bit corresponding to the cache CM1 specified by the request source device number stored in the second message receiving unit 41 is set to "1". This is the value obtained as a result of performing the operation.

Next, when the second consistency maintenance control unit 44 of the memory MM2 detects that the ACK message is taken in by the second message receiving unit 41, the header unit stored in the second message receiving unit 41. From the address of, the directory state and directory map of the corresponding block and the update frequency value are read from the directory memory 43, and what kind of processing is to be performed is determined by the value. At this time, the value that the directory state can take is
Methodologically limited to'WSP 'or'RMP'.

When the directory state is'RMP ', the process when the memory MM2 receives the ACK message from the cache CM3 is performed in the sequence shown in FIG. 20 regardless of the update frequency value.

The second consistency maintenance control unit 44 first determines the EDR.
Generates a header part of the message and sends the second message sending part 4
Feed to 2. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier is EDR.
Is the second identifier in the address and the request source device number.
The address of the message header section stored in the message receiving section 41 and the request source device number (here, “00”).
It is 0 '). In addition, the second consistency maintenance control unit 44
To the second data control unit 45, the main memory 46
To read the block specified by the address of the message header section stored in the second message receiving section 41. The second data control unit 45 supplies the read block to the second message transmission unit 42 as the data portion of the EDR message. Second message sending unit 42
Sends the message to the mutual connection network 12 by combining the header part supplied from the second consistency maintenance control part 44 and the data part supplied from the second data control part 45. Also,
The second consistency maintenance control unit 44 uses the directory memory 43.
Is written, the directory state is updated to M, the directory map is updated to “0001”, and the update frequency value is updated to “0”. The value of this directory map is the cache CMi specified by the request source device number of the message header section stored in the second message receiving section 41.
It is a value obtained as a result of the operation of setting the bit corresponding to (here, the cache CM1) to "1" and setting the other bits to "0".

When the directory state is "WSP" and the directory map is not "0001", the memory M is processed in the sequence shown in FIG. 24 regardless of the value of the update frequency value.
M2 performs processing when it receives the ACK message issued by the cache CM3.

The second consistency maintenance control unit 44 writes the directory memory 43 and sets the directory state to "WSP" as it is, but the directory map decrements the value of the previous directory map (here, "0001"). ') And the update frequency value is updated to' 0 '.

Next, the directory state is'WSP '.
Then, when the value of the directory map is '0001', the ACK issued by the cache CM4 by the memory MM2 in the sequence shown in FIG. 24 regardless of the value of the update frequency value.
Process when a message is received.

The second consistency maintenance control unit 44 first generates the header portion of the CR message and then the second message transmission unit 42.
To supply. The destination device number of the message header generated at this time becomes the request source device number of the message header part stored in the second message receiving unit 41 (in this case, '000'), and the message identifier represents CR. In the identifier, the address and the request source device number are the address and the request source device number of the message header part stored in the second message receiving unit 41 (here, “000”).
It becomes). The header portion supplied from the second message transmission unit 42 and the second consistency maintenance control unit 44 is sent to the mutual connection network 12 as a message. Further, the second consistency maintenance control unit 44 writes in the directory memory 43 and updates the directory state to M, the directory map to '0001', and the update frequency value to '0'. In the value of this directory map, the bit corresponding to the cache CMi (here, the cache CM1) specified by the request source device number of the header part stored in the second message receiving unit 1 is set to "1", and the other It is a value obtained as a result of the operation of setting the bit to “0”.

Next, the effect of the third embodiment of the present invention will be described.

For example, when the block state of the cache CM1 is the shared state and the latest block exists only in the cache CM1 and the memory MM2, the processor PR is
1 continuously writes, while another processor P
Consider the case where Ri did not access. In this case, in the data consistency maintenance control method according to the first embodiment, a write request message is issued from the cache CM1 to the memory MM2 each time writing is performed. Therefore, there is a problem that the number of messages for data consistency maintenance control in this case increases. In the data consistency maintenance control method according to the second embodiment, the first two
Writing of the third time is reflected in the memory, but writing of the third time and thereafter is not reflected in the memory. Therefore, substantially the latest block does not exist in the memory MM2 after the second writing. Therefore, when another processor PRi makes an access thereafter, the latest block does not exist in the memory MM2. In this case, therefore, it takes a long time from the occurrence of the cache miss until the data is returned to the processor. Become.

In the data consistency maintenance control method according to the third embodiment, the update frequency upper limit value which is a parameter is set to N.
If set to, memory N is written in the first N + 1 times.
It is also reflected in M2. Therefore, the latest block remains in the memory MM2 until writing is performed N + 1 times. Therefore, in the meantime, another processor PRi
Is accessed, the latest block is the memory MM
2 exists, it is possible to reduce the time required from the occurrence of a cache miss to the response of data to the processor. If there is no access during that time, the writing is not reflected in the memory MM2 from the N + 2th time. Therefore, it is possible to prevent an increase in messages in this case.

[0179]

The first effect is that, when a cache miss occurs due to the reading of the processor, the time taken until the data is responded from the cache to the processor can be shortened.

The reason is that, when writing is performed to the block shared by the processors, the writing is reflected in the memory so that the latest block exists.

The second effect is that it is possible to reduce the message for data coherency maintenance control generated when a cache miss occurs due to the reading of the processor.

The reason is that, when writing is performed to the block shared by the processors, the writing is reflected in the memory so that the latest block exists.

The third effect is that it is possible to suppress an increase in the number of messages generated by writing by the processor.

The reason is that when the processor continuously writes to a block which is actually shared by a plurality of caches and another cache does not access during that time, the write is reflected in the memory. The reason is that it will be terminated midway.

The fourth effect is that it is possible to adjust whether to strengthen the first and second effects or the third effect.

The reason is that if the processor continuously writes to a block which is actually shared by a plurality of caches and another cache does not access during that time, the write is reflected in the memory. This is because it is possible to set the number of times to terminate with a parameter.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a configuration of a multiprocessor system according to the related art and the present invention.

FIG. 2 is an explanatory diagram of a cache configuration according to the present invention.

FIG. 3 is an explanatory diagram of a memory configuration according to the present invention.

FIG. 4 is a diagram showing a relationship between a value of a directory map and a cache held therein.

FIG. 5 is a diagram illustrating a configuration of a message header of a data consistency maintenance control method according to the first embodiment.

FIG. 6 is a sequence flow for writing back a block to be replaced in a memory in the case of a cache miss in the data consistency maintenance control method according to the first embodiment.

FIG. 7 is a sequence flow for writing back a block to be replaced in a memory in the case of a cache miss in the data consistency maintenance control method according to the first embodiment.

FIG. 8 is a sequence flow of a message exchanged between a cache and a memory in the case of a cache miss in the first embodiment.

FIG. 9 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the first embodiment.

FIG. 10 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the first embodiment.

FIG. 11 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the first embodiment.

FIG. 12 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the first embodiment.

FIG. 13 is a sequence flow of messages exchanged between the cache and the memory in the case of the write shared according to the first embodiment.

FIG. 14 is a sequence flow of messages exchanged between the cache and the memory in the case of the write shared according to the first embodiment.

FIG. 15 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing according to the first embodiment.

FIG. 16 is a diagram for explaining the operation of the data consistency maintenance control method according to the second embodiment.

FIG. 17 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the third embodiment.

FIG. 18 is a sequence flow of messages exchanged between a cache and a memory in the case of a cache miss in the third embodiment.

FIG. 19 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the third embodiment.

FIG. 20 is a sequence flow of a message exchanged between the cache and the memory in the case of a cache miss in the third embodiment.

FIG. 21 is a sequence flow of messages exchanged between the cache and the memory in the case of a cache miss in the third embodiment.

FIG. 22 is a sequence flow of a message exchanged between the cache and the memory in the case of the write shared according to the third embodiment.

FIG. 23 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing according to the third embodiment.

FIG. 24 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing according to the third embodiment.

FIG. 25 is a sequence flow of messages exchanged between a cache and a memory in the case of write sharing according to the third embodiment.

FIG. 26 is a sequence flow for writing back the block to be replaced in the memory in the case of a cache miss in the data consistency maintaining method according to the third embodiment.

FIG. 27 is a sequence flow for writing back a block to be replaced in the memory in the case of a cache miss in the data consistency maintaining method according to the third embodiment.

[Explanation of symbols]

 PRi processor CMi cache MMi memory 12 mutual connection network 21 memory access management unit 22 tag memory 23 first consistency maintenance control unit 24 first data control unit 25 cache memory 26 first message receiving unit 27 first message transmitting unit 41 second Message receiving unit 42 Second message transmitting unit 43 Directory memory 44 Second consistency maintenance control unit 45 Second data control unit 46 Main memory

Claims (3)

[Claims] 1. A data consistency maintenance control method in a multiprocessor system in which a plurality of processors have a cache, wherein when one processor writes to a block shared by the plurality of processors, the write is performed. The writing is reflected in the cache and memory blocks of the processor that has performed so that the latest block exists in the cache and memory, and the cache blocks of other processors are invalidated, and the latest block exists. Data coherency maintenance control method characterized in that the state of the block of the cache in which the writing is performed is kept in the shared state. 2. A data coherency maintenance control method in a multiprocessor system in which a plurality of processors have a cache, wherein when one processor writes to a block shared by the plurality of processors, the write operation is performed. If the latest block exists only in the cache and memory of the processor that performed the operation and the cache of another processor does not hold the latest block, write to the cache and memory block of the other processor. Reflecting, the latest block exists in the cache and memory of the processor that wrote the data, and the state of the block of the cache of the processor that wrote the data is transited from the shared state to the non-shared state. Data consistency maintenance control method. 3. A data coherency maintenance control method in a multiprocessor system in which a plurality of processors have a cache, wherein a field indicating an update frequency value is provided for each block in a memory, and a block shared by the plurality of processors is provided. When one processor writes
If the latest block exists only in the cache and memory where the write was performed, another cache does not hold the latest block, and the update frequency value is different from a certain value, the update The frequency value is incremented, otherwise the update frequency value is initialized to 0, and when one processor writes to a block shared by multiple processors, the writing If the latest block exists only in the cache and memory, the cache of another processor does not hold the latest block, and if the update frequency value matches a certain value, the processor that performed the write Write to the other cache and memory blocks, and the latest block Data consistency maintenance control method characterized in that the state of a block of the cache in which data has been written is changed from a shared state to a non-shared state so that it exists in the cache and memory of the server.