JPH09229704A - Route seeking device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a route seeking device in which route seeking up to a destination can be performed in a short time. SOLUTION: A distance calculation unit 33, a junction data management unit 34 and a junction data storage unit 35 independent of CPU 31 are added and operated in parallel, pipeline processing is realized by operating distance calculation for finding an expectation cost out of route retrieval processing using A algorithm and rearrangement of the expectation costs for carrying out for searching a promising route out of the expectation costs on halfway of retrieval in parallel. And a processing time is shortened as the whole seeking.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a route search device, and more particularly, to a route search device which searches a route to be guided at high speed in a navigation system for guiding a route from a departure place to a destination.

[0002]

2. Description of the Related Art In a conventional route search in a navigation system, a search is generally performed using a heuristic method represented by the A ^* algorithm. In this A ^* algorithm, A) a step of extracting a road to be connected at a certain point, B) a step of calculating a traveling cost of the road and an estimated cost of reaching a destination after following the road, C).
The processing is carried out in three steps: a step of deciding a direction to be searched next based on the total estimated cost obtained by adding up the cost spent for moving the road that has been traced so far and the estimated cost to reach the destination.

[0003]

As shown in FIG. 8, the processing time of each step in such an A ^* algorithm consists of a portion for obtaining an estimated cost (hereinafter referred to as a distance calculation part) and a search order. A part that rearranges the data in the order of the total expected cost during the search for determining (hereinafter,
It is called an intermediate data management part. ) Is a large part of the necessary calculation processing. The estimated cost used here is generally the straight line distance from the point of interest (intersection) during the search to the destination, or the distance multiplied by a constant coefficient. The calculation of is usually a lot of calculation time because it includes the sum of squares and the square root calculation. Also, in the intermediate data management part, if the road network is complicated or the section to be searched becomes wide, there is a property that the number of intermediate data waiting to be processed increases and the number of steps required for rearrangement increases, which is also a huge calculation. Need time. However, in the conventional route search device, each step of the A ^* algorithm that requires a lot of time is sequentially and repeatedly processed by a single CPU, so that the route search time to the destination is reduced. It was getting longer.

Therefore, an object of the present invention is to provide a route search device capable of completing a route search to a destination in a short time.

[0005]

According to a first aspect of the present invention, in a route search device for searching an optimal route to a destination using an A ^* algorithm, a predetermined process is independently performed in the optimal route search process. And a control unit that performs a process other than the process performed by this subunit, and the subunit is composed of an estimated cost calculation unit that calculates an estimated cost. According to the invention described in claim 2, in the route search device according to claim 1, the sub-unit further stores a total estimated cost obtained by using a calculation result by the estimated cost calculation means, and holds the total estimated cost. Means, and optimal candidate extraction means for extracting the most promising search candidate from the total expected costs stored in the total estimated cost holding means. In the invention according to claim 3, in the route search device according to claim 1 or 2, the estimated cost calculation means is a table having a predetermined angular resolution, for example, a low-precision table of about several hundreds. , The distance is calculated using the tangent of the trigonometric function. According to a fourth aspect of the present invention, in the route search device according to the second aspect, the optimum candidate extracting means extracts the most promising search candidate by using a hardware comparator.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a route search device of the present invention will be described in detail below with reference to FIGS. FIG. 1 shows the configuration of a route search device. The route search device controls the entire navigation system, and at the same time, controls the extraction of roads connected in route search (extraction of target intersections), the CPU 31, the route search speed-up device 32, the RAM 36, and the storage device 3.
7 is provided. The CPU 31 is for performing processing such as route search and navigation processing according to various programs stored in a ROM (not shown). RAM 36
Is used as a working memory of the CPU 31 and stores various data such as an optimum cost in route search. The storage device 37 is composed of, for example, a mass storage device such as a CDROM,
Stores road data used for route search. The road data includes the intersection number, the coordinate value (latitude, longitude) of the intersection, the presence or absence of a signal, the road number of the road connected to the intersection, the road length of the road, information about one-way traffic and right / left turn. ing.

In the route search speed-up device 32, the distance calculation part and the intermediate data management part in the A ^* algorithm are composed of units that operate independently. That is, the distance calculation unit 33 that specializes in distance calculation
And a rearrangement unit 38. The rearrangement unit 38 temporarily stores the cost at each intersection in the memory and instantly finds the intersection with the minimum cost in the CPU 31.
And an intersection data storage unit 35 for storing data and searching for a minimum cost intersection returned by the intersection data management unit 34. A unit dedicated to the processing of the distance calculation part and the intermediate data management part in the A ^* algorithm is arranged as a unit that operates independently of the CPU.
U and each unit cooperate with each other in search processing to form a pipeline and obtain a minimum cost route. As described above, in the route search device, paying attention to the high independence of the A ^* algorithm for each part, the A ^* algorithm operates independently of the CPU 31 and exclusively performs the processing of the distance calculation part and the intermediate data management part. By arranging the three units 33, 34, 35, the CPU 31 and the respective units 33, 34, 35 cooperate with each other to perform the search process while exchanging data, thereby enabling pipeline processing and shortening the search time. It is the one.

Before explaining the concrete constitution of each unit 33, 34, 35, the contents of the A ^* algorithm will be explained, and then the constitution of each unit 33, 34, 35 and its processing operation will be explained. The A ^* algorithm uses "total expected cost" as the evaluation criterion at the target intersection. This total estimated cost is the actual distance from the departure point to the target intersection via each intersection, and the straight line distance from the target intersection to the destination intersection (the closest intersection to the destination) "Estimated cost"
Then, it is expressed as follows. "Total expected cost" = "Actual cost" + "Estimated cost"

[0009] Here, because of the relation of "predicted cost" ≤ "actual cost from target intersection to destination intersection", the total estimated cost at the departure intersection is the smallest and the actual cost as the search position approaches the destination. Since the number of times of addition of is increased, the value of the total expected cost is also increased. As shown in FIG. 6 as an example of a flowchart showing the processing, the A ^* algorithm starts the search from the search start position (departure intersection), selects all the roads connected to the start intersection, and connects the intersections ( (Hereinafter referred to as target intersection), and the total expected cost for each target intersection is calculated. Then, select the intersection with the smallest total expected cost (minimum total expected cost intersection), obtain the target intersection connected to it, and set it as the destination intersection (the closest intersection to the destination), as in the first process. This is a search method in which processing is repeated until they match.

FIG. 2 shows a road network for route search. In FIG. 2, intersections are represented by circles, searched roads are represented by thick arrows, unsearched roads are represented by dashed arrows, and the straight line distance (estimated cost) from each intersection to the destination intersection is represented by a thin arrow. ing. Each road is marked with a road number along with an arrow, and the passing cost (distance) of the road is shown in parentheses after the road number.
Is described. An intersection number is attached to each intersection, and the actual cost from the departure intersection to the intersection and the expected cost from the intersection to the destination intersection are described in parentheses behind it.

Now, the search is started from the starting point of this road network, and when the intersection 1 is reached, A ^* is taken as an example ^.
The algorithm is explained. It is assumed that an intersection 1 is found by following the road 01 from the intersection 0 during the search. Intersection 1
If is different from the destination, search for an intersection connecting to it and proceed further. The search process here proceeds in the following steps.

Step A: Road 01 at intersection 1
The head of the road connected to (for example, the road 11) is taken out, and if the road is accessible, the following steps B to D are performed.
Is performed. Step B: The moving cost C1 of the road 11 is added to the actual cost (S1) from the starting point at the intersection 1 to obtain the actual cost (S1 + C1) from the starting point to the target intersection 2 connected by the target road 11. Step C: The straight line distance (L2) from the target intersection 2 to the destination intersection is obtained and used as the estimated cost to reach the destination.
If the expected cost at the target intersection 2 has already been calculated, that value is used. Step D: The sum (S1 + C1 + L2) of the actual cost and the estimated cost obtained in Steps A and B is set as the total estimated cost at the target intersection 2, and the total estimated cost is inserted in the search queue so as to be arranged in ascending order. Step E: Take out another road connected to the intersection 1,
The processes of steps A to D are repeated. All roads 11, 1
After processing 2 and 13, go to the next step.

Step F: The intersection with the smallest total expected cost is extracted from the queue as the minimum total estimated cost intersection. Step G: If the extracted minimum total expected cost intersection is not the destination intersection and the optimum cost (actual cost) to reach the destination intersection has not yet been obtained, the process returns to step A. On the other hand, when the optimum cost to the destination is required, the value of the optimum cost is compared with the total estimated cost at the minimum total estimated cost intersection. As described above, the value of the total expected cost increases as the destination intersection is approached. Therefore, if the total estimated cost is larger than the optimum cost, a smaller optimum cost cannot be obtained, so the processing ends. . If the optimum cost is required and the total expected cost is smaller, the optimum cost smaller than the current optimum cost (where Z is Z, the current optimum cost ≧ Z ≧ minimum total predicted cost). Since it is possible to obtain the total expected cost range at the intersection.), The processing from step A onward is repeated. Step H: When the minimum total expected cost intersection extracted in step f is the destination intersection, the total expected cost (= actual cost) is compared with the optimal cost to the destination already obtained, and the smaller one is selected. Save as the optimum cost and move to step F. When the optimum predicted cost is not yet obtained, the total predicted cost at the minimum total predicted cost intersection is stored as the optimum cost.

In the above-mentioned A ^* algorithm, the time required for each processing is largely calculated by the distance calculation in step C and the rearrangement of the queue in step D, and the actual cost and total expected cost calculation in step B, step A Alternatively, the extraction of the connecting road of E ends in a relatively small time. Assuming that the loads of steps A and E are so small that they can be ignored for convenience, the respective processing time ratios are as shown in FIG. Conventional A ^*
In the algorithm, as shown in FIG. 3A, each step is sequentially processed by a single CPU.

On the other hand, in the present embodiment, paying attention to the fact that the processing of each step is highly independent, the processing of each step is shared by the CPU 31 and a specialized processing circuit (path search speed-up device 32). By doing so, for example, if a distance calculation unit 33 specialized in distance calculation is introduced and a distance calculation unit 33 that operates independently of the CPU 31 is introduced,
A pipeline configuration as shown in (b) is possible, and the entire processing time can be shortened (the portion B shows the distance calculation processing). Similarly, by introducing a unit (intersection data management unit 34 and intersection data storage unit 35) which is in charge of processing for rearranging the order in the queue based on the total expected cost at each intersection, FIG. ), The speed can be further increased. The portion represented by the symbol C corresponds to the rearrangement processing, and A'in the figure is an overhead of passing the result of the distance calculation to the rearrangement processing in addition to the total estimated cost. When data is added, the CPU 31 is released when the data is received, and the CPU 31 side rearranges the stored data while performing other processing.
At the time of reading data by the CPU 31, the data of the minimum total expected cost intersection is instantly returned, and the minimum expected cost intersection is searched until the next reading.

Next, the specific configurations of the distance calculation unit 33, the intersection data management unit 34, and the intersection data storage unit 35, which constitute the route search device shown in FIG. 3, will be described. FIG. 4 shows the configuration of the distance calculation unit 33. In the A ^* algorithm, it is not necessary to calculate exactly, the optimum solution is guaranteed within the range that does not exceed the actual distance (actual cost), and the number of search steps is increased if the distance value includes an error. However, since it is known that the search result is not affected, this unit makes it possible to calculate the distance with a small number of tables, such as several hundreds, by setting the calculation error to about several percent. To adopt.

The distance calculation unit 33 comprises an X coordinate register 61 and a Y coordinate register 62 which receive data from the CPU 31, and a distance value register 63 which supplies data to the CPU 31. The X coordinate register 61 is connected to the comparator 64 and the shift register 66a, and the Y coordinate register 62 is connected to the comparator 64 and the shift register 66b via a data bus, respectively. The shift registers 66a and 66b are connected to both the selectors 65a and 65b via a data bus. The comparator 64 is
Shift registers 66a, b and selectors 65a, b
And is connected via a control bus. The selector 65b is connected to the integer divider 67 via the bus line, and the integer divider 67 is connected to the constant table 6 via the control bus.
9 and the constant table 69 is connected to the multiplier 68 via the data bus. The selector 65a is connected to the integer divider 67 and the multiplier 68 via a bus line, and the multiplier 68 is connected to the distance value register 63 via a bus line.

The X coordinate register 61 and the Y coordinate register 62 are registers to which the horizontal and vertical components (relative coordinates) between the two points to be obtained are input, and the difference between the X components of both coordinates of the target intersection and the destination intersection. The difference ΔY between ΔX and the Y component is C
It is supplied from PU1. The distance value register 63 calculates the distance between the two points (between the target intersection and the destination intersection) calculated in the distance calculation unit 33 as the CPU 31.
Is a register for supplying to. The comparator 64 is supplied with Δ from the X coordinate register 61 and the Y coordinate register 62.
The magnitudes of X and ΔY are compared. If ΔY is larger, the control signal “1” is output, and if ΔX is larger, the control signal is “”.
The control signal output from the comparator 64 is supplied to each of the shift registers 66a and b and the selectors 65a and 65b. The shift registers 66a and 66b are output from the comparator 64. When the control signal is supplied, the input data is shifted by a predetermined bit.

The selector 65a outputs the data supplied from the shift register 66b when the control signal "1" is supplied from the comparator 64 (when ΔY> ΔX), and the control signal "0" is supplied. In this case (when ΔY <ΔX), the data supplied from the shift register 66a is output.
On the contrary, the selector 65b outputs the control signal "from the comparator 64".
The data supplied from the shift register 66a is output when 1 "is supplied, and the data supplied from the shift register 66b is output when the control signal" 0 "is supplied. X coordinate register 6
1, the larger data of ΔX and ΔY supplied to the Y coordinate register 62 is output from the selector 65a,
The smaller data is output from the selector 65b.

The integer divider 67 divides the output value of the selector 65b by the output value of the selector 65a to obtain tan θ. Here, tan θ is 0 <tan θ ≦
It is one. In the integer divider 67, the fourth decimal
You may make it output the result which rounded down the value below the place. The constant table 69 is a non-volatile memory and has a tan θ
The value of is used as the address, and 1 /
The value of cos θ is written, and the content of the address specified by the output (tan θ) of the integer grading unit 67 is output. The multiplier 68 outputs the output of the selector 65a (the larger value of ΔX and ΔY) and the constant table 69.
The result of multiplying with the output of is output. This output is supplied to the distance value register 63 as an estimated cost between the target intersection and the destination intersection.

Next, in the distance calculation unit 33 thus constructed, the CPU 31 operates the X coordinate register 6
1 and the Y coordinate register 62 stores the relative coordinates (Δ
The operation from the supply of (X, ΔY) to the supply of the expected cost at the target intersection from the distance value register 63 to the CPU 31 will be described. The relative coordinates at the target intersection are ΔX <ΔY. The relative coordinates input to the X coordinate register 61 and the Y coordinate register 62 are supplied to the distance value registers 63a and 63b and the comparator 64. The comparator 64 compares the supplied ΔX and ΔY in magnitude and outputs the control signal “1” because ΔY is larger. As a result, ΔY is output from the selector 65a,
ΔX is output from the selector 65b. Then, tan θ = ΔX / ΔY is calculated in the integer divider 67,
It becomes an index of the constant table 69. In the constant table 69, using the supplied tan θ as an address, the data (1 / cos θ =
The expected cost L / Y) is supplied to the multiplier 68. Multiplier 6
In 8, the output of the constant table 69 is multiplied by the selector 65a to obtain the expected cost, which is the distance between the target intersection and the destination intersection, and this value is calculated as the distance value register 6
3 is supplied.

Next, a specific structure of the rearrangement unit 38 will be described with reference to FIG. The rearrangement unit 38 corresponds to a portion for selecting the minimum cost intersection in the A ^* algorithm, and corresponds to the intersection data management unit 34.
And an intersection data storage unit 35, which is configured to store data and output a minimum cost intersection at high speed. For the A ^* algorithm, it is important that the minimum cost data is output, and the internal data representation is not important. Therefore, the sorting unit 38 is
In the intersection data management unit 34 that directly exchanges data with the PU 31, a minimum value is selected using a hardware comparison circuit and the minimum value is returned to the CPU 1.

The intersection data management unit 34 is a CPU
A data register 71 for exchanging data with 31 is provided. The data register 71 is connected to the comparator 64c and the selector 65c via a data bus, and is connected to the comparator 64c via a control bus. The selector 65c is further connected to the comparator 64c via a control bus and is connected to the interface register 74 via a data bus. The comparator 64c is further connected to the maximum / minimum value detection circuit 73 via a control bus. The intersection data management unit 34 further includes a data management register 72 and a memory 79c.
c is a data register 71, a comparator 64, a selector 65
c, the maximum / minimum value detection circuit 73, and the interface register 74 are connected via a data bus. The intersection data management unit 34 plays a role of a temporary buffer when communicating with the CPU 31.

The data register 71 stores the intersection data (the intersection number of the intersection, the intersection number of each intersection through which the intersection is reached, the actual cost to reach the intersection, the estimated cost, and the total estimated cost). When writing intersection data from the CPU 31, this is a register for setting the intersection data to be written. In this case, when the control signal "1" is supplied from the comparator 64c, the data register 71 stores the set intersection data in the memory 79c. On the other hand, when the CPU 31 reads the data from the rearrangement unit 38, the intersection data stored in the address on the minimum value side designated by the data management register 72 is set in the data register 71 from the memory 79c. The data management register 72 is a register for holding an address in which the maximum value and the minimum value of the total expected cost are stored among the data stored in the memory 79c.

The comparator 64c compares the total expected costs supplied from the data register 71 and the memory 79c, outputs a control signal "1" when the data register 71 side is large, and outputs "1" when the memory 79c side is large. It outputs 0 ". The total estimated cost supplied from the memory 79c is read from the maximum value side address specified by the data management register 72. Selector 65
The interface c receives the intersection data from the data register 71 when the control signal "1" is supplied from the comparator 64c and the intersection data from the memory 79c when the control signal "0" is supplied. It is adapted to be supplied to the register 74.

The maximum / minimum value detection circuit 73 has a memory 79.
This is a circuit that examines the intersection data stored in c and sets the address, in which the maximum and minimum values of the total expected cost are stored, in the data management register 72. The maximum / minimum value detection circuit 73 reads the intersection data from the CPU 31, and outputs the control signal from the comparator 64.
0 "is supplied and the intersection data from the data register 71 is activated after being stored in the memory 79c. The interface register 74 is provided between the intersection data management unit 34 and the intersection data storage unit 35. This is a register for transmitting and receiving data.When writing data to the intersection data storage unit 35, the data selected by the selector 65c is set, while it is stored in the intersection data storage unit 35 when reading data. The intersection data having the minimum total expected cost is set and stored in the memory 79c.

The memory 79c is a random access memory for storing intersection data. In this memory 79c, among all the intersection data stored in the rearrangement unit 38, N pieces of intersection data having a smallest total expected cost are selected as the intersection data which are likely to be candidates to be extracted in the next step in the A ^* algorithm. It is supposed to be stored. The number N of intersection data stored in the memory 79c can be selected arbitrarily.
For example, 10, 5, 3, 15, 20, etc. are selected.

On the other hand, the intersection data storage unit 35 is
It does not directly exchange data with the CPU 31, but functions as a sub-unit of the intersection data management unit 34. The intersection data storage unit 35 includes an interface register 75, and is connected to the interface register 74 of the intersection data management unit 34 via a data bus. Interface register 7
Reference numeral 5 is connected to a minimum value register 76 and a data writing circuit 77 via a data bus.
Is connected to the minimum value detection circuit 78 via the control bus. The intersection data storage unit 35 further includes a memory 79d, which has a minimum value register 76 and a minimum value detection circuit 78 via a data bus.
Is connected to

The interface register 75 includes an intersection data management unit 34 and an intersection data storage unit 35.
This is a register for exchanging intersection data with and from. At the time of writing, the intersection data to be stored is set from the intersection management unit 34, and at the time of reading, the intersection data in the memory 79d designated by the minimum value register 76 is set. Minimum value register 76
Is a register that holds the address of the memory 79d in which the intersection data with the smallest total expected cost is stored. The data writing circuit 77 investigates whether or not the intersection data having the same number as the intersection number in the intersection data supplied from the interface register 75 exists in the memory 79d. The total estimated costs are compared with each other, and the intersection data having the smaller value is stored at the same address in the memory 79d. If there is no intersection data with the same intersection number, the memory 79
The intersection data supplied from the interface register 75 is written in the empty area of d.

The minimum value detection circuit 78 examines the intersection data having the minimum total estimated cost from the memory 79d and sets the address in the minimum value register 76. The minimum value detection circuit 78 is activated by the interface register 75 after reading the intersection data, and the memory 7
The data writing circuit 77 is activated after the intersection data is written in 9d. Memory 79
d is a random access memory in which intersection data is stored. The sorting unit 3 is included in the memory 79d.
Among all the intersection data stored in 8, the remaining intersection data excluding the N intersection data stored in the memory 79c of the intersection data management unit 34 is stored. Therefore, the intersection data with the smallest total expected cost in the rearrangement unit 38 is the intersection data with the smallest total estimated cost in the intersection data storage unit 35.

Next, the operation of the rearrangement unit 38 thus configured will be described. When the CPU 31 issues a read request for the minimum total expected cost intersection, the intersection data management unit 34 reads the intersection data specified by the address on the minimum value side stored in the data management register 72 from the memory 79c, and the data register 71
And supplies it to the CPU 31 as intersection data of the minimum total expected cost intersection. Thus, at the time of reading data, first, the intersection data of the minimum total expected cost intersection is instantly returned to the CPU 31, and then the next minimum expected cost intersection is searched until the next reading. That is, after reading the data, the intersection data management unit 34 activates the maximum / minimum value detection circuit 73 and sets the maximum value and the minimum value in the data management register 72. At this time, if the intersection data storage unit 35 has intersection data (when the sorting unit 38 as a whole has N + 1 or more intersection data), the intersection data storage unit 35 is requested to read the data. To do.

When there is a data read request, the intersection data storage unit 35 reads the intersection data of the address indicated by the minimum value register 76 from the memory 79d, sets it in the interface register 75, and sets the interface of the intersection data management unit 34. It is supplied to the register 74. When the intersection data is supplied to the interface register 74, the intersection data management unit 34
The supplied intersection data is stored in the memory 79c, and the stored address is set on the maximum value side of the data management register 72.

On the other hand, the intersection data storage unit 35 supplies the intersection data from the interface register 75 to the interface register 74 and then activates the minimum value detection circuit 78. As a result, the minimum value detection circuit 78 searches the memory 79d for the minimum value of the total expected cost, and sets the address at which the intersection data is stored in the minimum value register 76.

Next, writing of intersection data into the rearrangement unit 38 will be described. Sorting unit 3
Among all the intersection data stored in No. 8, N pieces of intersection data from the minimum value of the total estimated cost to the Nth are stored in the intersection data management unit 34, and the total estimated cost is N.
The intersection data larger than + 1st is stored in the intersection data storage unit 35. Therefore, when the intersection data from the CPU 31 is written to the rearrangement unit 38, if the total expected cost of the intersection data set in the data register 71 is larger than the Nth total estimated cost, it is stored in the intersection data storage unit 35, If it is smaller, it is stored in the intersection data management unit 34 and the intersection data having the maximum total estimated cost (N + 1th smallest) is transferred from the memory 79c to the intersection data storage unit 35.

When the intersection data is set in the data register 71 by the CPU 31, the set intersection data and the data management register 72 from the memory 79c are set.
The intersection data of the address designated on the maximum value side of is respectively supplied to the selector 65c. Also, the selector 6
Of the two intersection data supplied to 5c, the value of the total expected cost is compared by the comparator 64c. Comparator 64c
If the total estimated cost on the side of the data register 71 is large as a result of the comparison in (1), it is not necessary to replace it with the intersection data in the memory 79c. That is, the control signal "1" is output from the comparator 64, and the selector 65c receives the intersection data supplied from the data register 71 to the intersection data storage unit 35 via the interface register 74 by the control signal "1". Supply and intersection data management unit 3
The writing process of the intersection data in 4 is ended.

On the other hand, if the total estimated cost on the memory 79c side is large, it is necessary to replace the intersection data supplied from the CPU 31 with the intersection data having the maximum total estimated cost in the memory 79c. That is, the control signal "0" is output from the comparator 64, and the selector 65c supplies the intersection data supplied from the memory 79c to the intersection data storage unit 35 via the interface register 74. Further, the data register 71 stores the intersection data set by the CPU 31 in the memory 79c. After that, the maximum / minimum value detection circuit 73 causes the memory 7
The maximum value and the minimum value of the total expected cost are detected from the N number of intersection data stored in 9c, the address where the intersection data is stored is stored in the data management register 72, and the intersection data management unit 34 Ends the writing process.

On the other hand, when the intersection data management unit 34 supplies the intersection data to the interface register 75 of the intersection data storage unit 35, the data writing circuit 77 stores the intersection data having the same number as the supplied intersection data in the memory. By investigating whether it exists in 79d, it is examined whether another route to the intersection is searched. If the same intersection number exists, the data writing circuit 77 compares the total expected costs in the two intersection data with each other and stores the intersection data with the smaller value in the same address in the memory 79d. If there is no intersection data with the same intersection number, the intersection data supplied from the interface register 75 is written and saved in an empty area of the memory 79d. Memory for intersection data 7
After saving in 9d, the data write circuit 77 activates the minimum value detection circuit 78. The minimum value detection circuit 78 has the minimum total estimated cost (N + in the rearrangement unit 38 as a whole).
The first (smallest) intersection data is examined from the memory 79d, and its address is set in the minimum value register 76,
The process of writing the intersection data by the intersection data storage unit 35 ends.

Next, the operation of the route search processing by the CPU 31 will be described with reference to the flowchart of FIG. At the beginning of the route search process, the CPU 31 sets the input departure place as the minimum total expected cost intersection (step 1
1) From the road data in the storage device 37, check the adjacent intersections that can enter from this minimum total expected cost intersection, and set these as the target intersections (step 12). Then, the number P of these target intersections and necessary road data for each target intersection are stored in a predetermined area of the RAM 36. The road data required here is the intersection number of each target intersection, the road length (distance between intersections), and the coordinate values (latitude, latitude,
(Longitude) etc. are stored. Next, for the P target intersections, Q and R are set to "1" mainly for counting the actual cost calculation process and the total expected cost calculation process (step 14).

Next, the CPU 31 calculates the actual cost from the departure point to the Qth target intersection (representing the target intersection having the Qth smallest intersection number. The same applies hereinafter). That is, the minimum total expected cost is the actual cost at the intersection,
Add the road length to the Qth target intersection (step 1
5). For example, in FIG. 2, when the intersection 1 is the minimum total expected cost intersection and the intersection 2 is the Qth target intersection,
The actual cost at intersection 2 = S1 + C1 is calculated.

Then, the CPU 31 calculates the estimated cost from the Q-th target intersection to the destination intersection (the straight line distance between the two intersections) by the distance calculation unit 33 by Δ.
Calculate X and ΔY. That is, both the coordinates of the Qth target intersection and the destination intersection are read from the RAM 36, the difference ΔX of the X component and the difference ΔY of the Y component of both coordinates are calculated, and the calculated values are stored in the RAM 36 as relative coordinates to the Qth target intersection. (Step 16). When R = 1 (step 17; Y), ΔX and ΔY of the Rth target intersection
Is set in the distance calculation unit 33 (step 1
8). That is, ΔX is set in the X coordinate register 61 and ΔY is set in the Y coordinate register 62.

Next, the CPU 31 controls the distance calculation unit 3
3 determines whether or not the calculation of the estimated cost has been completed (step 19). If the distance calculation unit 33 is calculating the expected cost (step 19; N), whether Q = P,
That is, it is determined whether or not the calculation of the actual costs and the storage in the RAM 36 have been completed for all the target intersections checked in step 12 (step 20). If Q ≠ P (step 20; N), there is a target intersection for which the actual cost has not been calculated yet, so after adding 1 to Q (step 2).
1), shift to step 15. On the other hand, when Q = P (step 20; Y), the calculation of the actual costs for all the target intersections is completed, so the process proceeds to step 16.

In step 19, when the distance calculation unit 33 finishes the calculation of the estimated cost, that is, when the estimated cost is set in the distance value register 63 (Y), the CPU 31 determines the (R + 1) th target intersection. The relative coordinates (ΔX, ΔY) are set in the distance calculation unit 33 (step 22). Then, the total expected cost of the Rth target intersection is calculated (step 23). That is, CP
The U31 reads out the estimated cost from the distance value register 63, reads out the actual cost of the Rth target intersection stored in step 16 from the RAM 36, and adds both of them to calculate the total estimated cost (= actual cost + estimated cost). To do. The CPU 31 sets the intersection data of the Rth target intersection in the data register 71 of the rearrangement unit 38, including the calculated total estimated cost (step 24). As a result, in the rearrangement unit 38, the above-described data writing process is performed in parallel with the process of the CPU 31.

Next, the CPU 31 judges whether the Rth target intersection is the destination intersection or not, and if it is the destination intersection (step 25; Y), further determines whether or not the optimum cost is already stored in the RAM 36. Judge whether or not (Step 2
6). If the optimum cost is not stored (that is, the route to the destination intersection is not yet found) (step 26; N), and the optimum cost is stored (step 26; Y), the R-th target If the total expected cost at the intersection is less than the optimal cost (step 2
7; Y), the CPU 31 updates the value of the optimum cost in the RAM 36 to the total expected cost at the Rth target intersection calculated in step 23 (step 28).

If the Rth target intersection is not the target value intersection (step 25; N) and the total expected cost at the Rth target intersection is larger than the optimum cost, the optimum cost is not updated, or After updating the total expected cost (step 28), the process proceeds to step 29, and it is determined whether R = P. If R ≠ P (step 2
9; N), there is a target intersection for which calculation of the total expected cost has not been completed, so after adding “1” to R (step 3)
0), shift to step 20.

On the other hand, when R = P (step 29;
Y), since the total expected cost calculation for the P-specific target intersection is completed, the CPU 31 requests the rearrangement unit 38 for the intersection data of the next minimum total expected cost intersection (step 31). When the intersection data of the minimum total expected cost intersection is acquired from the data register 71 of the rearrangement unit 38 (step 32; Y), the CPU 31
Stores the intersection data in the RAM 36.

Then, it is judged whether or not the optimum cost is already stored in the RAM 36, and if it is not stored (step 34; N), the process directly proceeds to step 12. On the other hand, when the optimum cost is stored (step 34; Y), the size of the total estimated cost is further compared (step 35). If the total expected cost is less than or equal to the optimum cost, the process proceeds to step 12 to search for a route with another optimum cost B that satisfies the total predicted cost ≦ B <the optimum cost. Minimum total expected cost If the total estimated cost of the intersection is larger than the optimum cost (step 35; Y), the current optimum cost is the smallest, and another route having a smaller optimum cost cannot be found, so the process ends. To do.

As described above, according to the route search apparatus of this embodiment, the distance calculation part and the data sort part in the A ^* algorithm are arranged as the distance calculation unit 33 and the rearrangement unit 38 which operate independently of the CPU 31. Therefore, it becomes possible to pipeline the search processing, and the search is completed in a short time as a whole.

Furthermore, in the distance calculation unit 33, the hardware required for distance calculation can be constructed with a simple configuration, and
^{* It} is possible to calculate the distance with high accuracy and sufficient to apply the algorithm. The distance calculation unit 33 calculates the distance using the tangent of the trigonometric function, and uses a low-precision table that limits the angular resolution of the triangle to about several hundreds, so high-speed distance calculation is possible. become.

Further, in the rearrangement unit 38 in charge of the data sort part, the minimum value is possible with a simple structure, the rearrangement by the software which requires a large amount of calculation is not necessary, and the high speed search is possible.

In the embodiment described above, the distance calculation part and the data sort part, which were conventionally performed by the CPU, are performed by the distance calculation unit 33 and the rearrangement unit 38. However, as shown in FIG. , Data sort C
The calculation may be performed by the PU and only the distance calculation may be performed independently by the distance calculation unit. Further, in the embodiment described above, the operation according to the flowchart shown in FIG. 7 has been described as the processing embodying the A ^* algorithm, but the present invention is not limited to this operation, and the CPU is not limited to this operation.
The A ^* algorithm may be realized by another operation as long as it is based on the pipeline processing between the sub-unit and the sub-unit.

In the embodiment described above, the actual distance (road length) from the destination to the target intersection after passing through the predetermined intersection has been described as the actual cost. You may make it consider the relative distance which considered cheapness in calculation of real cost. For example, in the case of an intersection where a traffic light is installed, the actual cost may be added to the actual distance by a predetermined distance Xm. In addition, the distance that considers conditions such as the width of the road connecting the intersections, the presence or absence of traffic lights and crossings, and the maximum speed may be adjusted.

[0052]

As described above, according to the route search apparatus of the present invention, each process of the A ^* algorithm can be pipelined, so that the route search to the destination can be performed in a short time. You can finish with.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a route search device of the present invention.

FIG. 2 is an explanatory diagram showing a road network for route search in the same as above.

FIG. 3 is a schematic diagram for explaining a breakdown of processing time in the A ^* algorithm.

FIG. 4 is a configuration diagram of a distance calculation unit in the route search device.

FIG. 5 is a configuration diagram of a rearrangement unit in the route search device.

FIG. 6 is a flowchart explaining the processing operation of the A ^* algorithm.

FIG. 7 is a flowchart explaining a processing operation of a CPU in the route search device.

FIG. 8 is a schematic diagram for explaining a breakdown of processing time in a conventional route search device.

[Explanation of symbols]

 31 CPU 32 Route search speedup device 33 Distance calculation unit 34 Intersection data management unit 35 Intersection data storage unit 36 RAM 37 Storage device 61 X coordinate register 62 Y coordinate register 63 Distance value register 64, 64c Comparator 65a, 65b, 65c Selector 66a, 66b Shift register 67 Integer divider 68 Multiplier 69 Constant table 71 Data register 72 Data management register 73 Maximum / minimum value detection circuit 74, 75 Interface register 76 Minimum value register 77 Data writing circuit 78 Minimum value detection circuit 79c , 79d memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Ushiki 2-19-12 Sotokanda, Chiyoda-ku, Tokyo Equus Research Co., Ltd. (72) Inventor Satoshi Kitano 2-19 Sotokanda, Chiyoda-ku, Tokyo No. 12 Stock Company Equus Research

Claims (4)

[Claims] 1. A route search device for searching an optimum route to a destination using an A ^* algorithm, wherein a sub-unit that independently performs a predetermined process in the optimum route search process and a process other than this sub-unit A route search device comprising: a control unit configured to perform the process described above, wherein the subunit includes an estimated cost calculation unit that calculates an estimated cost. 2. The sub-unit further comprises total estimated cost holding means for storing and holding total estimated cost obtained by using the calculation result by the estimated cost calculating means, and total estimated cost stored in the total estimated cost holding means. The route search device according to claim 1, further comprising: an optimal candidate extraction unit that extracts a most promising search candidate in cost. 3. The route search according to claim 1, wherein the estimated cost calculation means calculates a distance by using a tangent of a trigonometric function with a table having a predetermined angular resolution. apparatus. 4. The route search device according to claim 2, wherein the optimum candidate extraction means extracts the most promising search candidate by using a hardware comparator.