JPH09218225A - Peak detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To catch the peak value of a signal varying at high rate and the generating time thereof surely. SOLUTION: A comparator CP1 compares an input signal 20 with a signal 21 obtained by delaying the input signal 20 through a micro time delay circuit DL. Since the output 27 from the comparator CP1 makes a transition from 'L' to 'H' at a positive peak and from 'H' to 'L' at a negative peak, a peak detection signal 27 is obtained. Peak value 26 of the input signal 20 can be obtained surely by operating a wide band sample hold circuit 51 at the transition point. Since a positive peak value can be obtained when a timing control circuit 60 outputs a sample timing signal 74 upon detection of a positive peak value while a negative peak value can be obtained when a sample timing signal 74 is outputted upon detection of a negative peak value, it is also possible to obtain both positive and negative peak values simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak detecting circuit for detecting a peak of an electric signal. Specifically, it is an object of the present invention to provide an improved peak detection circuit capable of surely detecting a positive or negative peak value of an electric signal which changes at a high speed and a timing showing the peak.

[0002]

2. Description of the Related Art A peak detection circuit capable of detecting a peak envelope is a capacitor charging circuit that stores the maximum value or the minimum value of a signal, a switch that discharges the charge of the capacitor, and a value stored in the capacitor charging circuit. And a timing control circuit for switching the operating state of the sample and hold circuit and the state of the switch.

A peak detection circuit capable of detecting a peak time is a voltage divider that slightly divides the voltage of a capacitor charging circuit that stores the maximum value (positive peak value) or minimum value (negative peak value) of a signal. , Was composed of a comparator that compares the voltage of the divided voltage of the capacitor charging circuit.

FIG. 6 shows a detection circuit for detecting the positive peak of the input signal 20. Reference numeral 10 is a signal input terminal for the input signal 20, 16 is a peak envelope output terminal for outputting a peak envelope signal 26, 18 is a peak detection signal output terminal for outputting a peak generation timing as a peak detection signal 28, 4
0 is a peak hold circuit and there is an operational amplifier A
1, a diode D5 and a capacitor C1 are included.

SW1 is a semiconductor switch which is turned on / off by a hold / reset signal 75. 45 is a buffer
At the output of the amplifier, the peak hold signal 71 is obtained. This is the sample hold circuit 52 and the resistor R.
1 and R2 applied to an attenuator. sample·
The hold circuit 52 samples and holds the peak hold signal 71 by the sample timing signal 74 to obtain the peak envelope signal 26.

At the negative input terminal of the comparator CP3,
The input signal 20 is applied. The attenuator consisting of resistors R1 and R2 obtains the reciprocal attenuation ratio of the gain of the buffer amplifier 45. It is configured such that the positive peak value of the input signal 20 and the value of the signal applied to the positive input terminal of the comparator CP3 become substantially equal to or slightly smaller. For example, if the gain is 1, the damping ratio is 1, that is, the peak hold signal 71 is directly applied to the positive input terminal of the comparator CP3. If the gain of the buffer amplifier 45 is 2, the attenuation ratio is 1/2, that is, R1 = R2.

The input signal 20 is also applied to the positive input terminal of the comparator CP2 whose negative input terminal is grounded, which outputs a polarity determination signal 72 indicating the polarity of the input signal 20 and applies it to the timing control circuit 61. doing. In the timing control circuit 61, the sample
A sample timing signal 74 and a hold reset signal 75 necessary for controlling the hold circuit 52 and the switch SW1 are created and output.

The operation of the peak hold circuit 40 will be described. The input signal 20 applied to the signal input terminal 10 is applied to the positive input terminal of the operational amplifier A1. Input signal 2
When 0 goes in the increasing direction, the amplified signal is negatively fed back to the negative input terminal of the operational amplifier A1 while charging the capacitor C1 via the diode D5.

Input signal 2 applied to the positive input terminal
0 is compared with the charging voltage of the capacitor C1 and the input signal 2
When 0 becomes larger than the charging voltage, the signal sufficiently amplified by the operational amplifier A1 charges the capacitor C1 via the diode D5, so that the maximum voltage of the input signal 20 is held in the capacitor C1. When the input signal 20 becomes lower than the charging voltage, the signal amplified by the operational amplifier A1 is cut off by the diode D5, so that the charging voltage of the capacitor C1 does not change and the highest voltage (peak voltage) in the past. Will be held.

FIG. 7 shows the circuit configuration of the sample and hold circuit 52. There are four diodes D1
~ D4 diode bridge and capacitor C
2, there are an operational amplifier A2 and a pulse amplifier A5.
Diodes D1 to D4 forming a diode bridge only for a short period when the sample timing signal 74 is applied
Is on and the peak hold signal 71 is the capacitor C2.
To charge. The charging voltage is output to the peak envelope output terminal 16 as the peak envelope signal 26 via the operational amplifier A2 that is negatively feedback connected and functions as a buffer amplifier.

The sample-and-hold circuit of FIG. 7 is extremely excellent in high-speed response when the value of the capacitor C2 is made small and the stray capacitance of the circuit components is used. This circuit is also used as a sampling gate of a wide band sampling oscilloscope by turning on the diodes D1 to D4 of the diode bridge with an extremely narrow pulse.

FIG. 8 shows the waveform of each part of the circuit shown in FIG. In FIG. 9A, the input signal 20 applied to the signal input terminal 10 is shown, and in FIG.
However, in (c), the sample timing signal 74 is
A hold / reset signal 75 is shown in (d), a peak hold signal 71 is shown in (e), a peak envelope signal 26 is shown in (f), and a peak detection signal 28 is shown in (g). .

Since the input signal 20 of (a) is applied to the positive input terminal of the comparator CP2 and compared with the ground voltage of the negative input terminal, "" is input during the period when the input signal 20 shows a positive value. "H", "L" during the period showing a negative value
A polarity determination signal 72 of (b) is obtained.

At the timing when the polarity determination signal 72 changes from "H" to "L", the timing control circuit 61 generates a sample timing signal 74 shown in (c) with a narrow pulse width and applies it to the sample hold circuit 52. Then, sample and hold is performed there. When this sample and hold is completed, the hold / reset signal 75 of (d)
Is output, the switch SW1 is turned on, and the peak voltage charged in the capacitor C1 of the peak hold circuit 40 is
Reset by discharging the hold voltage.

The manner of this peak hold and reset operation is clearly shown by the peak hold signal 71 shown by the solid line in (e). Here, the broken line shows the waveform of the input signal 20 in (a) to facilitate comparison.
That is, when the input signal 20 rises, the peak hold signal 71 also rises with some operation delay time t _d for charging the capacitor C1, and when the input signal 20 turns from rise to fall, The voltage at the turning point (peak voltage) is held (hold), and the switch SW
When 1 is turned on by the hold / reset signal 75 in (d), the reset operation is repeated.

The operation delay time t _d in this peak hold operation determines the upper limit of the response speed of the peak hold circuit 40. In order to reduce the operation delay time t _d , the operational amplifier A1 having a wide band and a high gain as much as possible.
And a diode D5 having a small forward resistance and a large reverse resistance and capable of high-speed response, and a capacitor C1 having a capacitance as small as possible. Attempting to obtain the preferred requirements for op amp A1 and diode D5 results in high cost.

The capacitor C1 is reset by turning on the switch SW1. The reset time is determined by the time constant of the product of the resistance of the capacitor C1 and the switch SW1 when it is turned on and the operation delay of the switch SW1. Therefore, the use of the switch SW1 having a small operation delay capable of high-speed operation and a small ON resistance causes a high cost.

On the other hand, the value of the electrostatic capacitance of the capacitor C1 does not actually increase the cost. However, it is impossible to adopt a capacitance having a too small value. When the voltage of the input signal 20 becomes slightly lower than the voltage held in the capacitor C1, the voltage difference is amplified by the extremely large gain of the operational amplifier A1 (the ideal operational amplifier has an infinite gain). Then, a large negative voltage is applied to the anode side of the diode D5,
This is because the capacitor C1 cannot be held at a constant value by discharging the capacitor C1 through the reverse resistance.

The peak hold signal 71 shown by the solid line in FIG. 8E is sampled and held at the timing of the sample timing signal 74 in FIG. 6C in the sample and hold circuit 52 in FIG. A value envelope is obtained as the peak envelope signal 26 as shown by the solid line in (f). Here, the broken line in (f) represents the peak hold signal 71 in (e) for easier understanding.

The voltage at the positive input terminal of the comparator CP3 is substantially the same value as the peak voltage (the malfunction due to noise etc.) when the operation delay time t _d is ignored when the input signal 20 shows the peak voltage. The voltage of the resistors R1 and R2 is selected so as to be a voltage slightly lower than the peak voltage in consideration of the avoidance of
When the output starts decreasing, the output of the comparator CP3 is inverted from "L" to "H", and the peak detection signal 28 of (g) is obtained.

The solid line peak hold signal 71 in FIG.
Is lower than the broken line input signal 20, the peak detection signal 28 in (g) is “L”, and while the solid line peak hold signal 71 in (e) is higher than the broken line input signal 20, (g). The peak detection signal 28 in () is “H”. The transition point from “L” to “H” of the peak detection signal 28 in (g) represents the timing of positive peak detection.

Here, paying attention to the peak time t _p 7 in which the input signal 20 in FIG. 8A changes rapidly and shows a peak, immediately before that, when the input signal 20 crosses the level of zero from negative to positive. The peak detection signal 28 in FIG. 9 (g) changes from “H” to “L”, the input signal 20 decreases when the peak time t _p 7 is slightly exceeded, and the peak hold signal 71 in FIG. The peak detection signal 28 in (g) changes from "L" to "H" when the value becomes smaller. Therefore,
When the operation delay time t _d is minute and the waveform of the input signal 20 has a narrow pulse shape, the pulse width of the peak detection signal 28 becomes extremely narrow, and there is a possibility that it cannot be detected at last.

FIG. 9 shows another conventional example for obtaining the peak envelope signal. Here, the same symbols are used for the same constituent elements in FIG. 6, and the different points will be described. In FIG. 6, the polarity determination signal 72 (FIG. 8B) is input to the timing control circuit 61.
And was obtained from the input signal 20. On the other hand, in the case of FIG. 9, the external clock 23 having no relation to the input signal 20 is applied from the external clock terminal 13.

FIG. 10 shows the waveform of each part of the circuit shown in FIG. 9, and corresponds to FIG. FIG. 10B shows an external clock 23, which has a cycle unrelated to the input signal 20 shown in FIG. 10A and is the same as the polarity determination signal 72 (FIG. 8B). Are different. FIG.
(C), (d), (e), (f), and (g) correspond to those in FIG.

In the operation shown in FIG. 10, since the peak times t _p 5 and t _p 7 of the input signal 20 in (a) are within the same period of the sample timing signal 74 in (c), the peak Although the peak value at time t _p 5 is detected by the peak hold signal 71 of (e), it is not detected by the peak envelope signal 26 of (f). The peak detection signal 28 of (g) is at the peak time t _p.
If the peak of No. 5 is detected, it changes from "L" to "H", and this change does not correspond to the peak envelope signal 26 of (f).

Further, in both circuit examples of FIGS. 6 and 9, as shown in the waveform diagrams of FIGS. 8 and 10, the peak detection signal 28 of (g) changes from "L" to "H". And detect the occurrence of the peak,
The peak envelope signal 26 of (f) displays the detected peak value after the application of the sample timing signal 74 of (c), and the time shift of one signal period ( Delay) has occurred. In both circuit examples, the case where a positive peak is detected is shown, but when a negative peak is detected, the peak hold circuit 40 is used.
It is necessary to use a circuit in which the direction of the diode D5 is reversed and to change the timing generated by the timing control circuit 61 accordingly.

[0027]

The problems to be solved in both conventional examples shown in FIGS. 6 and 9 will be listed.

1) Operation delay time t _d mainly caused by the capacitor C1 of the peak hold circuit 40 (see FIGS. 8 and 1).
Since there is a limit to reducing 0 (e)), a signal that changes faster than t _d cannot be tracked, which causes a large error or erroneous detection.

2) The repeating frequency of the discharging operation of the switch SW1 of the capacitor C1 having a capacitance which is not sufficiently small is such that the ON resistance of the switch SW1 is not sufficiently low.
Since there is a time delay for the switch to turn on, it usually stays at about 20 MHz, and in order to make it faster than that, a considerable cost increase was required.

3) Peak envelope signal 26 (FIGS. 8 and 10)
(F)) and the peak detection signal 28 indicating the occurrence of the peak are deviated in timing for one signal cycle.

4) Even if the peak detection signal 28 indicates the occurrence of a peak, the corresponding peak value may be missing from the peak envelope signal 26 (t _p 5 in FIG. 10 (f)).

5) When detecting a negative peak value, it is necessary to use a circuit different from that for detecting a positive peak value (in which the polarity of the diode D5 is reversed).

[0033]

The present invention has been made to solve many problems as described above. The cause of many problems is to determine the peak time and peak value of the input signal 20. It is based on the recognition that the peak-hold circuit 40 lacking high-speed response is used for detection.

The delay means for delaying the input signal by a slight time Δt and the delay means for comparing the input signal and the delay signal are compared with each other to obtain the comparison output as the peak detection signal. That is, the instantaneous value of the input signal is slightly larger (or smaller) than the delayed signal until just before it shows a positive (or negative) peak value, and at the peak value, both signals become substantially equal, and thereafter the input signal Is slightly smaller (or larger) than the delayed signal, the polarity of the peak detection signal is inverted immediately before and after this peak value. Depending on the direction of change during the reversal, it becomes clear whether the peak is positive or negative.

Since the positive (or negative) peak time point of the input signal can be accurately detected, this is used to hold the peak voltage by the sample-hold circuit excellent in high-speed response. Therefore, it was possible to obtain a peak detection circuit having an extremely high-speed response with a simple configuration.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit configuration for showing an embodiment of the present invention. Here, FIG.
The same symbols are given to those corresponding to the constituent elements in FIG.

The input signal 20 applied from the signal input terminal 10 receives the sample / hold circuit 51 and the comparator CP.
The negative input terminal of 1 and the delay circuit DL are applied. In the delay circuit DL, the input signal 20 is delayed by a minute time Δt to obtain a delayed signal 21, which is applied to the positive input terminal of the comparator CP1. The delay circuit DL is a constant impedance line piece or a transmission line piece formed of a lumped constant. The input signal 20 causes only a slight change in a minute time Δt. Attenuation of the delay signal 21 in the delay circuit DL does not cause any problem.

FIG. 2 shows the waveform of each part of the circuit shown in FIG. The input signal 2 shown by the solid line in FIG.
There is a delay signal 21 indicated by 0 and a broken line, and a minute time Δt which is a time difference between the two signals and the positive and negative peak times t _p 1, t _p 2, ... T _p 7 of the input signal 20 are displayed. ing. Description will be made with reference to this figure.

The input signal 20 is E ₀ and the delayed signal 21 is E ₁
Then, since E ₁ is equal to E ₀ at the time point before Δt, it can be expressed as E ₁ (t) = E ₀ (t−Δt) or E ₀ (t) = E ₁ (t + Δt). Further, assuming that the waveform in the period of ΔΔt / 2 is symmetrical with respect to the peak time t _p 1 of the input signal 20, for example, when 0 ≦ t <(t _p 1 + Δt / 2), E ₀ > E ₁ t = T _p 1 + Δt / 2, E ₀ = E ₁ (t _p 1 + Δt / 2) <t <(t _p 2 + Δt / 2), and E ₀ <E ₁ . Similarly, t = t _p 2 + Δt /
In _{2, E 0 = E 1 (} t p 2 + Δt / 2) <t <(t p 3 + Δt / 2) in, in _{E 0> E 1 t = t} p 3 + Δt / 2, E 0 = E 1 (t p 3 + Δt / 2) <t <(t _p 4 + Δt / 2), then E ₀ <E ₁ .

The comparator CP1 compares the input signal 20 and the delayed signal 21, and when the input signal 20 is larger than the delayed signal 21 (E ₀ > E ₁ ), the output peak detection signal 27 becomes "L", When both signals 20 and 21 become equal (E ₀ = E ₁ ), it is detected that a peak has occurred, the peak detection signal 27 is inverted, and the input signal 20 is smaller than the delay signal 21 (E ₀ <E ₁ ). At this time, the peak detection signal 27 becomes "H", so the peak detection signal 27 of FIG. 2B is obtained. The transition from "L" to "H" of the peak detection signal 27 causes the generation of a positive peak, and the transition from "H" to "L" causes the generation of a negative peak. At peak times t _p 1 and t _p 2, ... t _p
It is detected after Δt / 2 of 7.

The peak detection signal 27 of FIG. 2 (b) corresponds to the peak detection signal 28 of FIG. 8 or FIG. 10 (g) showing the prior art, but in the present invention, the peak detection signal 27 is The time point of occurrence of a positive peak is detected by the transition from "L" to "H", and the time point of occurrence of a negative peak is detected by the transition from "H" to "L".

On the other hand, the conventional peak detection signal 2
In No. 8, the detection is made only by the transition from "L" to "H" at the time of occurrence of the positive peak, and in order to detect the time of occurrence of the negative peak, the diode D5 (Fig. 6 or 9) is used.
Requires a separate peak detection circuit with the orientation reversed.

Further, in the peak detection signal 28 of the conventional example ((g) of FIG. 8 or FIG. 10), the pulse width becomes narrow at the peak time t _p 7 of the signal which changes abruptly, so that stable detection becomes impossible. However, the peak detection signal 27 (FIG. 5B) in the present invention does not have such a possibility.

Therefore, there is a very significant difference from the conventional example. The peak detection signal 27 (FIG. 2B) thus obtained from the comparator CP1 is applied to the timing control circuit 60 and the sample and hold circuit 50,
In the timing control circuit 60, the sample timing signal 74 for detecting the positive peak envelope (FIG. 2 (c))
Is generated and applied to the sample and hold circuit 51.

The structure of the sample and hold circuit 51 is shown in FIG.
Is the same as that shown in FIG. 2, in which the peak hold signal 71 is replaced with the input signal 20. Then
Since sample holding is performed at each positive peak of the input signal 20 shown by the broken line in FIG. 2D (strictly, at a point slightly delayed by Δt / 2),
The peak envelope signal 26 shown by the solid line in (d) is obtained.

[0046]

【Example】

Embodiment 1 In the configuration shown in FIG. 1, the sample and hold circuit 51 performs the sample and hold at the time when it is delayed by Δt / 2 from each positive peak of the input signal 20. When the delay of the sample hold of Δt / 2 becomes a problem, the signal input terminal 10 and the sample hold circuit 51 are connected.
If a signal delay circuit for delaying the input signal 20 by Δt / 2 is provided between the two, the sample-hold delay of Δt / 2 does not occur.

Embodiment 2 The sample timing signal 74 of FIG. 2 (c) is generated at the time of transition from "L" to "H" when the positive peak of the peak detection signal 27 of FIG. 2 (b) is detected. Therefore, the peak envelope signal 26 in FIG. 7D represents the positive peak value of the input signal 20. Therefore, this (c)
The sample timing signal 74 of the peak detection signal 27
If the one generated at the time of transition from “H” to “L” when the negative peak of is detected is used, it represents the negative peak value of the input signal 20 (values at peak times t _p 2 and t _p 4). It can be easily understood from the above description that the peak envelope signal can be obtained.

Embodiment 3 FIG. 3 shows an operation when the sample timing signal 74B of FIG. 1 is used in place of the sample timing signal 74 in the circuit configuration of FIG. FIG.
At each transition point of the peak detection signal 27 of
Each peak time t _p 1, t _p 2, of the input signal 20 of (a)
The sampling timing signal 74 is output from the timing control circuit 60 at t _p 7. Since the sample-hold circuit 51 samples and holds the input signal 20 of (a) at the timing of the sample timing signal 74 of (c), the peak envelope signal 26B of (d) is output to the peak envelope output terminal 16. You will get it. That is,
The peak envelope signal 26B shown by the solid line in (d) represents both the positive peak value and the negative peak value of the input signal 20 shown by the broken line.

Embodiment 4 FIG. 4 shows an embodiment different from the circuit configuration shown in FIG. Components corresponding to those in FIG. 1 are designated by the same reference numerals. Here, the difference from the circuit configuration of FIG. 1 is that a sample and hold circuit 50 is added. In FIG. 1, the sample of FIG.
Sample and hold circuit 5 using timing signal 74
The peak value is sampled and held at 1B. Therefore, in the case where the input signal 20 changes during the pulse width of the sample timing signal 74, FIG.
With this configuration, the peak value cannot be sampled and held accurately. The circuit configuration of FIG. 4 can thus accurately capture the peak value of the input signal 20 that changes at high speed.

Fifth Embodiment In the configuration shown in FIG. 4, the sample and hold circuit 50 performs sample and hold at a point of time that is delayed by Δt / 2 from each positive peak of the input signal 20. When the delay of the sample hold of Δt / 2 becomes a problem, the signal input terminal 10 and the sample hold circuit 50 are connected.
If a signal delay circuit for delaying the input signal 20 by Δt / 2 is provided between the two, the sample-hold delay of Δt / 2 does not occur.

FIG. 5 shows the waveform of each part of the circuit configuration of FIG. The difference from FIG. 2 is that the sample-and-hold signal 22 of (d) is added. sample·
The circuit configuration of the hold circuit 50 is basically the same as that shown in FIG. There, a peak hold signal 71 is applied to the input signal 20 and a sample timing signal 74 is applied.
Is replaced by the peak detection signal 27 and the peak envelope signal 26 is replaced by the sample and hold signal 22. And
Four diodes D1 to D1 which form a diode bridge in the period when the peak detection signal 27 of FIG.
The positive and negative output terminals of pulse amplifier A5 are interchanged so that D4 is off and on during the "L" period.

The sample and hold circuit 50 is shown in FIG.
During the “L” period of the peak detection signal 27 in (b), the waveform of the input signal 20 is output as it is as the sample and hold signal 22 because the diode bridge is on, but it becomes “H”. At the moment, that is, after Δt / 2 when the input signal 20 shows a positive peak, the diode bridge is turned off, and the positive peak voltage is held. When the peak detection signal 27 becomes "L" again, the waveform of the input signal 20 is output as it is as the sample and hold signal 22. Therefore, FIG. 5 (d)
The sample-and-hold signal 22 is obtained.

Here, the peak detection signal 27 of FIG.
Is "L" and the diode bridge of the sample and hold circuit 50 is on, the sample and hold signal 22 shown by the solid line in (d) follows the input signal 20 shown by the broken line. Therefore, the positive peak value of the input signal 20 can be reliably captured at the moment when the diode bridge is turned off. Therefore, even if the input signal 20 includes a signal that changes at high speed, peak detection can be performed.

The case of detecting the positive peak of the input signal 20 has been described, but in the case of detecting the negative peak,
Since the diode bridge may be turned on when the peak detection signal 27 of (b) is "H" and turned off when the peak detection signal 27 is "L", the positive and negative outputs of the pulse amplifier A5 in FIG. Connection will be good.

When the sample-hold signal 22 shown in FIG. 5D is obtained in this way, it is sampled and held in the sample-hold circuit 51B using the sample timing signal 74 shown in (c). The peak envelope signal 26 shown by the solid line in e) can be obtained at the peak envelope output terminal 16.

[0056]

As is apparent from the above description, the present invention has many advantages listed below.

1) The positive and negative peak times of the input signal can be accurately detected with a very small delay Δt / 2 and a simple configuration. As in Examples 1 and 5, the minute time Δt
When the input signal is delayed by 1/2 and applied to the sample-hold circuit, the peak amplitude of the input signal can be accurately detected.

2) Since the positive and negative peak times of the input signal can be accurately detected, the peak hold circuit is unnecessary, the operation delay time associated therewith is eliminated, and the peak is surely changed even in the fast-changing signal. Detection is possible.

3) Since the positive and negative peak times of the input signal can be accurately detected, it is possible to operate the sample and hold circuit having a wide band characteristic at that timing to sample and hold the peak value of the input signal. This enabled the peak detection of high frequency signals.

4) It has become possible to obtain a peak envelope signal indicating the peak value of an input signal without a timing delay after a minute time Δt / 2 from the time when the peak occurs.

5) Since it is possible to reliably detect the peak occurrence of the input signal, the phenomenon that the peak value is missing from the peak envelope does not occur.

6) The positive and negative peak values of the input signal can be obtained in time series with the same circuit configuration if necessary.

As described above, since the present invention has many advantages, it has a wide range of applications such as determining the presence or absence of a PCM or TV signal loss. Therefore, the effect of the present invention is extremely large.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing waveforms of respective parts when a positive peak is obtained with the configuration of FIG.

FIG. 3 is a waveform diagram showing waveforms of respective portions when positive and negative peaks are obtained with the configuration of FIG.

FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 5 is a waveform diagram showing waveforms of respective parts of FIG.

FIG. 6 is a circuit configuration diagram showing a conventional example.

7 is a circuit configuration diagram of a sample and hold circuit which is a component of FIG.

FIG. 8 is a waveform diagram showing waveforms at various portions in FIG.

FIG. 9 is a circuit configuration diagram showing another conventional example.

FIG. 10 is a waveform diagram showing waveforms at various portions in FIG.

[Explanation of symbols]

10 signal input terminal 13 external clock terminal 16 peak envelope output terminal 18 peak detection signal output terminal 20 input signal 21 delayed signal 22 sample hold signal 23 external clock 26 peak envelope signal 27, 28 peak detection signal 40 peak hold circuit 45 buffer amplifier 50 to 52 sample and hold circuit 60, 61 timing control circuit 71 peak and hold signal 72 polarity determination signal 74 sample timing signal A1, A2 operational amplifier A5 pulse amplifier C1, C2 capacitor CP1 to CP3 comparator D1 ~ D5 diode DL delay circuit R1, R2 resistance SW1 switch t _d operation delay time t _p peak time Δt minute time

Claims (9)

[Claims] 1. A delay means (DL) for delaying an input signal (20) by a very short time to obtain a delayed signal (21), and a size of the input signal (20) and the delayed signal (21). When the input signal (20) is larger than the input signal (20) and then the delayed signal (21) is larger than the input signal (20), the inverted time is the positive peak of the input signal (20). If the delayed signal (21) is larger and then inverted and the input signal (20) becomes larger, the time point of this inversion is determined to be the negative peak time of the input signal (20). Peak detection circuit including comparator means (CP1) for obtaining the peak detection signal (27). 2. The peak detection signal (27) represents at least one of positive and negative peak times (7).
4. A peak detection circuit according to claim 1, including sample and hold means (51) for sampling and holding said input signal (20) at 4, 74B) to obtain a peak envelope signal (26, 26B). 3. To obtain a peak envelope signal (26) representing a positive peak by sampling and holding the input signal (20) at a positive peak time (74) represented by the peak detection signal (27). Sample and hold means (5
The peak detection circuit of claim 1 including 1). 4. A sample and hold means for sampling and holding the input signal (20) at a negative peak time point represented by the peak detection signal (27) to obtain a peak envelope signal representing a negative peak ( 51. The peak detection circuit of claim 1 including 51). 5. A peak envelope representing positive and negative peaks by sampling and holding the input signal (20) at a positive peak time and a negative peak time (74B) represented by the peak detection signal (27). A peak detection circuit according to claim 1, including sample and hold means (51) for obtaining a signal (26B). 6. The sample of the input signal (20)
When applied to the holding means (51), the sample and hold means (51) is passed through a signal delay means for delaying the input signal (20) by a half of the minute time delayed by the delay means (DL). The peak detection circuit according to claim 2, 3, 4, or 5, wherein 7. Receiving the peak detection signal (27),
The input signal (20) in one of a first period from the positive peak to the negative peak and a second period from the negative peak to the next positive peak.
To hold the peak of the input signal (20) at the inverted time of the positive and negative peaks of the input signal (20) in the other period to obtain the hold signal (22). The peak detection circuit of claim 1 including means (50). 8. The sampling and holding means (51B) for sampling and holding the hold signal (22) obtained by the holding means (50) to obtain a peak envelope signal (26). Peak detection circuit. 9. When applying the input signal (20) to the holding means (50), the input signal (20) is delayed by a half of the minute time delayed by the delay means (DL). 8. The peak detecting circuit according to claim 7, wherein the peak detecting circuit is applied to the holding means (50) through a signal delaying means.