JPH09205140A - Element isolated semiconductor substrate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buried element-isolating technique using an organic silicon CVD method or the like such that the generation of crystal defects in an element forming region is restrained. SOLUTION: A buried element isolated substrate is formed by selectively forming a groove portion 6 at a predetermined position of a semiconductor substrate 5, and embedding an oxide film formed by an organic silicon CVD method into the groove portion 6 as a buried oxide film 7. This buried oxide film 7 is heat-treated at 1100-1350 deg.C before or after flattening of the semiconductor substrate 5. By heat-treatment, at least five membered ring or structure and at most four-membered ring structure in the buried oxide film 7 are constituted at a predetermined ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit substrate such as an LSI and a method for manufacturing the same, and more particularly to an element isolation technique for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In order to form an LSI, one element formation region and another element formation region are electrically formed around an element formation region for forming an active element such as a transistor or a passive element such as a resistor or a capacitor. It is necessary to form an element isolation region that is electrically isolated. In the development of MOS / LSI technology and bipolar LSI technology, the element isolation technology for forming this element isolation region has always been one of the important technical issues, but it is expected that its importance will continue to increase in the future. To be One of the developments that marked the era in the history of this element isolation technology is LOCOS (LOCal Oxidation), which can divide the element formation region and the element isolation region in a self-aligned manner.
It can be said that it was the development of the technology of no. As shown in FIG. 15, the LOCOS technique (LOCOS method) performs selective oxidation by using a nitride film (Si ₃ N ₄ film) 88 as a mask, and an oxide film (a film formed on the Si surface in a place where there is no Si ₃ N ₄ film). The SiO ₂ film) 82 is used as an insulating layer in the element isolation region. It is no exaggeration to say that this element isolation technology and polysilicon wiring technology have combined to bring about the prosperity of today's LSI industry. However, in the era of fine processing from submicron to deep submicron, this LOCOS technology is finally approaching its limit. The biggest problems are the erosion of the element formation region (active region) due to the presence of so-called bird's beaks and the occurrence of crystal defects due to the local stress generation at the time of forming the field oxide film. In particular, bird's beak is an obstacle to high integration for VLSI or ULSI,
In order to reduce the erosion due to bird's beak and miniaturize it, the thickness of the oxide film 82 must be reduced. However, reducing the thickness of the oxide film 82 causes a problem that the breakdown voltage between elements is lowered. LO to overcome this
Various improvements have been proposed for the COS method and new separation techniques. For example, as an improved element isolation technique based on the LOCOS method, an improved coplanar method, a direct nitride film mask method, or a SWAMI (Side WAll Masked) method is used.
Isolation) and the like, and a selective epitaxial method, a U-groove method, etc. have also been proposed. In addition to these element isolation technologies, BOX (Buried OXi
de) method, which is a method of burying an oxide film as shown in FIG.
It is drawing attention as an element isolation technology in LSI and the like.
This is an element isolation technique in which a U groove is formed in the silicon substrate 5 and then an insulating material 77 such as SiO ₂ is deposited so as to fill the U groove.

The insulating film deposition technique used in the BOX method is required to have various requirements such as uniformity, flatness, step coverage (step coverage), film quality, and low process temperature. Among these, the step coverage and the lowering of the process temperature are particularly important. Gigascale integrated circuit (GSI), etc.
In the manufacture of semiconductor integrated circuits, which are becoming more highly integrated, a good insulating film at low temperature is required. To meet this requirement, LTO (Low Temperature O), which is a CVD technique using monosilane (SiH ₄ ) and N ₂ O, etc., which can be conventionally formed at a relatively low temperature (300 to 450 ° C.).
XTO) is known, but LTO generally has poor step coverage and poor film quality depending on the forming conditions. In particular, the oxide film formed by the atmospheric pressure CVD method or the low pressure CVD method has a drawback that it exhibits tensile stress and its crack resistance is weak.

In view of these requirements, the CVD technique using an organic silicon material typified by TEOS (tetraethyl orthosilicate: Si (OC ₂ H ₅ ) ₄ ) has recently been actively researched. For example, the reaction of TEOS and O ₃ makes it possible to form an insulating film at a low temperature of 450 ° C. or lower,
In addition, the step coverage is good.

[0005]

[Problems to be Solved by the Invention] The BOX shown in FIG.
Among the methods, those having a relatively shallow groove depth are advantageous for miniaturization, and shallow trench isolation (Shallow Tre
nch Isolation; STI) method. However, this STI method is more advantageous than the LOCOS method in miniaturizing the element, but is a semiconductor substrate such as silicon to be an active element region (element formation region) and an insulator (for example, silicon Oxide) has a different coefficient of thermal expansion, so stress is generated in the semiconductor substrate during the thermal process during the formation of the element isolation region or during the LSI manufacturing process after the formation of the element isolation region, as shown by the thick solid line in FIG. There is a problem in that crystal defects such as dislocation 12 are generated. In particular, when an organic silicon source is used as a raw material for the formation of silicon oxide, the problem of impurities caused by the raw material refining technology of the organic silicon source has been highlighted. That is, since it is difficult to obtain a high-purity organic silicon source at present, impurities (eg, H ₂ O, organic matter, etc.) other than silicon oxide (SiO ₂ ) remain or are adsorbed in SiO ₂ immediately after deposition. doing. Therefore, the subsequent 800-1000 ℃
The thermal process of causes various problems due to the dissociation of these impurities. Moisture as an impurity in the organic silicon source material is usually contained in an amount of 100 to 20 ppm. Therefore, for example, in a silicon device, the coefficient of thermal expansion differs between the silicon substrate and the embedded SiO ₂ (buried oxide film), and the film shrinkage is added due to the dissociation of water in the buried oxide film. There is a problem that excessive compressive stress is applied to. Further, the conventional STI structure shown in FIG. 16 has a drawback that crystal defects are easily introduced into the substrate during the formation of the element isolation region or the subsequent heat process accompanying the element manufacturing process.
That is, the conventional element isolation technique by the STI method using an organic silicon source has a primary problem that crystal defects such as dislocations 12 are easily generated, propagated and propagated on the surface layer of the substrate, and these problems are accompanied. The secondary problem is that these crystal defects easily trap metal impurities and electrical defects such as junction leaks tend to occur because many crystal defects occur in the element formation region (active region). .

In particular, in the actual LSI manufacturing process, in addition to the stress caused by the existence of the element isolation region itself, the stress caused by the damage due to the ion implantation, and also various stresses such as electrodes and interlayer insulating films having different properties. Stress and the like accompanying the formation of the multilayer film are generated, and crystal defects are likely to occur. There is also a synergistic effect of crystal defects caused by the STI structure itself and crystal defects caused by other factors. The crystal defects generated in the substrate tend to capture metal impurities and the like. Therefore, in the conventional STI method, there is a problem in that the presence of crystal defects in the active layer (element formation region) causes an electrical failure such as an increase in junction leakage or a dielectric breakdown of the gate oxide film. there were. Therefore, the development of an element isolation technique that does not cause crystal defects in the element formation region is an important issue to be solved in the future miniaturized LSI manufacturing.

That is, the miniaturized GSI, ULSI,
In element isolation technology such as VLSI, conditions such as the absence of bird's beaks, a flat surface, and the absence of crystal defects are required. S
Although there is no problem of bird's beak in the TI method, the flatness of the surface and the suppression of the occurrence of crystal defects are important problems to be solved.

In view of the above-mentioned problems, the present invention provides ST
Provided is a semiconductor device using a buried element isolation method similar to the I method or the STI method, which is a semiconductor substrate for a high integration density semiconductor in which crystal defects generated in an element formation region due to stress of SiO ₂ are reduced. The purpose is to do.

Another object of the present invention is to provide a method of manufacturing a semiconductor substrate which can reduce crystal defects caused by stress of SiO ₂ and suppress a pn junction leak current in an element forming region, and at the same time enable high integration density. Is to provide.

Still another object of the present invention is to provide a method of manufacturing a semiconductor substrate which can bury a good quality oxide film having an etching rate equivalent to that of a thermal oxide film in an element isolation region at a low temperature. Is.

[0011]

In order to achieve the above object, the first feature of the present invention is as shown in FIGS.
As shown in (f), FIG. 9 (g) and FIG. 14 (e), a plurality of groove portions 6 formed in a part of the surface of the semiconductor substrate.
And a buried oxide film 71 formed inside the groove portion 6 and an element forming region between the groove portion 6 and the groove portion 6, wherein the buried oxide film 71 is an organic silicon-based C
VD method, so-called SOG (Spin-on-glass)
s) method, which is either a resin glass coating method or an anodizing method, and thereafter 1100 to 13
That is, the oxide film is heat-treated at a temperature of 50 ° C.
Here, "a plurality of groove portions" means that a plurality of grooves are observed in a cross section when observed on a predetermined cut surface, and does not limit the shape on the plane pattern. That is, in a fixed case, these groove portions may continuously form one groove portion as a plane pattern. For example, although the corresponding plan view of FIG. 1 is omitted, the plurality of groove portions 6 shown in FIG.
N ⁺ source region 91 as shown in the center of FIG.
n ⁺ drain region 92 is to be construed as can be understood as being integrally formed as a region that round enclosed around the element formation region MOS transistor or the like is formed having a. Alternatively, as shown in FIG. 12, the buried oxide film 71 may be arranged in an island shape around the element formation region and may not be completely surrounded. In any case, when there are two or more groove portions so as to sandwich the element formation region when observed with a constant cross section, it corresponds to the “plurality of groove portions” in the present invention. The object of the present invention can be achieved even if the oxide film is heat-treated at a temperature of 1350 ° C. or higher.
Since it becomes difficult to configure a reaction tube for heat treatment, an apparatus such as a furnace, and contamination of the semiconductor substrate from the furnace poses a problem, it is not realistic considering the current technology. It will be apparent to those skilled in the art that the temperature cannot be higher than the melting point of the oxide film.

Preferably, in the first feature, it is defined by the ratio of the depth d of these groove portions 6 formed on the surface of the semiconductor substrate and the width l ₁ of the openings of these groove portions 6. That is, the aspect ratio d / l ₁ is 10 or less.
As shown in FIG. 10, the first feature of the present invention is that the defect density observed in the element formation region is reduced when the aspect ratio is 10 or less, and the stress of the buried oxide film 71 is not sufficiently reduced when the aspect ratio is 10 or more. This is because it is experimentally revealed that the defect density due to this stress is not reduced. Further, preferably, in a line-and-space repeating pattern in a predetermined direction in which the groove width l ₁ is the minimum space width and the element formation region width l ₂ is the minimum line width, l defined in the predetermined direction is defined. Ratio of ₁ to l ₂
That is, ₁ / l ₂ is 1.5 or less. As shown in FIG. 13, when l ₁ / l ₂ is 1.5 or more, 1100 ° C. to 135
Even by heat treatment at 0 ° C., the stress of the oxide film cannot be reduced, and crystal defects occur. It should be noted that this l ₁ / l ₂ is defined for a certain direction, and this line and
A portion in a direction orthogonal to the repeating direction of the space pattern, that is, a pattern in a direction orthogonal to the cutting plane XX in FIG. 11B, which does not have the minimum line width or the minimum space width. The pattern size ratio may be 1.5 or more. FIG. 12 shows the case where the line and space pattern exists in two directions. In FIG. 12, the ratio 1 in the XX direction
_1x / l _2x is defined and the ratio is 1 _1y / l _2y in the Y-Y direction.
Is defined. In such cases, at least
The ratio may be 1.5 or less in either direction. For example, if l _1x / l _2x ≦ 1.5 (1) l _1y / l _2y > 1.5 (2), the formula (1) may be adopted. In the opposite case (2)
A formula may be adopted. Of course the ratio l _1x / in both directions
Both l _2x and l _1y / l _2y may be 1.5 or less. The "ratio between 1 ₁ and l ₂ defined in a predetermined direction" in the present invention is defined in any one direction as described above, and the ratio l ₁ / l ₂ in the defined direction is 1.5
The following should be understood to mean that the other directions do not matter.

The second feature of the present invention is similar to the first feature shown in FIG. 1 (e), FIG. 7 (f), FIG. 9 (g) and FIG.
In the element isolation semiconductor substrate having the shape as illustrated in (e), the buried oxide films 25 and 71 include a ring structure having a 5-membered ring or more and a ring structure having a 4-membered ring or less at a predetermined ratio. It is a crystalline silicon oxide film.

Here, the predetermined ratio is shown in FIGS. 4 (a) and 4 (b) obtained from the measurement of Raman scattering spectrum.
In the sense that the ratio of the integrated intensity of the Raman shifts corresponding to the multi-membered ring structure of three-membered ring, four-membered ring, and five-membered ring or more as shown in is there. That is, FIGS. 4 (a) and 4B.
As shown in (b), it means the ratio of the integrated intensity of each Raman shift in the case where the spectrum region having a wave number of 300 to 700 cm ⁻¹ is set as the whole. Here, the integrated intensity of each Raman shift is defined within a predetermined spectral range including the corresponding peak.

That is, as shown in FIG. 5, (i) the integrated intensity ratio of the Ramin ft corresponding to a 5-membered ring or more is substantially 85% or more of the total, and (ii) the Raman corresponding to a 4-membered ring or a 3-membered ring. The buried oxide film 2 is made by the amorphous silicon oxide film (SiO ₂ film) satisfying one of the two conditions that the integrated intensity ratio of shift is substantially 15% or less of the whole.
The stress in 5 and 71 and the stress in the interfaces between the buried oxide films 25 and 71 and the semiconductor substrates 5, 16 and 23 are alleviated, and the generation of dislocations in the element formation region is suppressed. Here, “substantially 85% or more” means that about 80% or more is allowed, as indicated by an error bar in FIG. Further, "substantially 15% or less" means that about 20% or less is allowed. When both the 3-membered ring and the 4-membered ring are contained, the sum of the 3-membered ring and the 4-membered ring may be substantially 15% or less. That is, 85% or more and 15% as referred to in the present invention.
The following should be understood to mean the relationships shown in FIG.
In addition, it goes without saying that the background component is removed in the calculation of the integrated intensity ratio in the second feature of the present invention. With the structure of the second characteristic of the present invention, the leakage current of the pn junction formed in the element formation region is reduced, and a high density integrated circuit having good characteristics can be realized.
The etching rate (etching rate) of the oxide film containing at least 85% of the 5-membered ring or more and substantially not more than 15% of the 4-membered ring or the 3-membered ring of the present invention is N as shown in FIG.
The etching rate by H ₄ F is 130 nn / min or less, which is almost equal to the corresponding etching rate of the thermal oxide film. Therefore, the etching rate may be examined as a simple verification of the composition of the 5-membered ring or more and the 4-membered ring.

The third feature of the present invention is shown in FIGS.
(E) or FIGS. 7 (d) to 7 (f), at least the following steps are included. That is, (a)
As shown in FIG. 1A or FIG. 7D, the semiconductor substrate 5,
A first step of forming a plurality of groove portions 6 on a part of the surface of 16,
(B) As shown in FIG. 1 (b), (c) or FIG. 7 (e), an oxide film 7, 71 is formed in the groove 6 by an organic silicon based CVD method.
And a third step of (c) heat-treating the oxide film 71 at a substrate temperature of 1100 ° C. to 1350 ° C. As described above, the "plurality of grooves" is a concept when viewed in a constant cross section. What is the organic silicon-based CVD method? TEOS (Tet
raethylthosilicate; Si (O
C ₂ H ₅ ) ₄ ), TMOS (Tetramethoxy)
silane; Si (OCH ₃ ) ₄ ), TPOS (Te
trapropoxysilane; Si (OC
₃ H ₇ ) ₄ ) or DADBS (Diacetox)
yditertiarybutyoxysilane;
It refers to CVD using an organic silicon source such as (C ₄ H ₉ O) ₂ Si- (OCOCH ₃ ) ₂ ) as a raw material.

Preferably, the organic silicon-based CVD method in the second step is any one of an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method, a photo CVD method and a liquid phase CVD method. The atmospheric pressure CVD method may be a so-called ozone-based atmospheric pressure CVD method that uses ozone (O ₃ ) formed by introducing O ₂ into an ozonizer and discharging it. The low pressure CVD method (LPCVD) refers to a CVD method in which the reaction of TEOS-O ₃ is performed at a reduced pressure of 6.7 kPa or the like. 13.56MH _z or 150KH the plasma CVD
_It may be performed using a gas source of TEOS, O ₂ , He or the like by using a plasma discharge of about _z . Photo CVD method is Ar
F (193 nm), KrF (249 nm), XeCl
(308 nm), XeF (350 nm), excimer laser light, a high-pressure mercury lamp, a mercury-xenon lamp, or the like may be used as a photoreaction mainly using light energy of ultraviolet light. The liquid-phase CVD method is, for example, O ₂ excited by RF discharge and TMS (Tetramethy).
lsilane; Si (CH ₃ ) ₄ -40 ° C.
CVD, etc.

Preferably, the oxide film formed by the organosilicon CVD method is a reducing gas such as H ₂ or He, Ne, Ar or K.
It is carried out in an inert gas such as r, Xe, etc., O ₂ , N ₂ , HCl, CO or CO ₂ , or a mixed gas composed of two or more gases selected from these.

In the formation of the buried oxide film in the second step, specifically, as shown in FIG. 1 (b), the oxide film 7 is deposited thicker than the groove portion, and then as shown in FIG. 1 (c). It is preferable to include the step of planarizing the surface of the semiconductor substrate 5 until the surface is substantially exposed. Here, "the surface of the semiconductor substrate is substantially exposed" means that the semiconductor substrate 5 is completely exposed.
It is not always necessary to etch back until the
For example, if required in the subsequent process, 50n
Meaning that "substantially exposed" is obtained even if the surface of the semiconductor substrate is flattened by etching back so that an extremely thin oxide film of about m to 100 nm or about 300 nm remains on the surface of the semiconductor substrate 5. Is. Further, either the flattening step or the heat treatment step may be performed first. Therefore, contrary to the above, in the second step, the organic silicon-based CV is used.
Alternatively, only the step of forming an oxide film thicker than the depth of the groove portion in D may be performed, and after the heat treatment of the third step, a surface flattening step may be performed as the fourth step.

An important point in the third feature of the present invention is the heat treatment temperature (annealing temperature). FIG. 2 shows that after the organic silicon-based CVD method, 50
The results are shown in the case where a heat treatment is performed at intervals of ° C to fabricate a device isolation semiconductor substrate structure as a prototype. That is, after forming this element isolation region, an element isolation semiconductor substrate after forming an element such as a MOS transistor in the element formation region (SDG region) having a width of 0.3 μm between trenches to form a MOS integrated circuit, It is the result of surface SEM observation. As shown in FIG. 2, it can be seen that dislocations frequently occur at the low temperature side heat treatment temperature of 1100 ° C. or lower. This is a dislocation similar to the dislocation 12 in the conventional STI substrate shown by the thick solid line in FIG.

The data shown in FIG. 2 is obtained by observing dislocation pits by a selective etching method and performing SEM observation.
This is the result of measuring the dislocation density in the m-square region at five points in the plane and averaging those values. 1000 ° C ~ 1100
At the heat treatment temperature up to ℃, about 10 dislocations 12 / μm ² similar to the thick solid line in FIG. 16 (prior art) are generated.
It can be seen that the heat treatment temperature is higher than that, that is, the temperature range of the present invention is reduced. Further, a MOS transistor is formed in the SDG region where the above element isolation is performed, and n ⁺ − corresponding to the pn junction structure in this MOS transistor is formed.
The result of measuring the junction leakage characteristic of the p-diode is shown in FIG. It can be seen that the leakage current is reduced in the substrate that has been heat-treated at 1100 ° C. or higher. This result reflects that the dislocation in the n ⁺ -p well junction, which is the cause of the leakage current, was suppressed, and the stress control of the buried oxide film according to the present invention is effective in suppressing the dislocation and reducing the leakage current. It means that. Similar results are apparent when used for device isolation of the bipolar integrated circuit shown in FIG.
The temperature range of the present invention (1
In the case of heat treatment at 100 ° C to 1350 ° C,
It can be seen that the stress of SiO ₂ is relaxed and the junction leakage current is reduced.

A fourth feature of the present invention is: (a) preparing a first semiconductor substrate having first and second main surfaces,
9A, the direct bonding oxide film 24 is formed on the first main surface of the semiconductor substrate 23 by an organic silicon-based CVD method, and the first heat treatment is performed at a substrate temperature of 1100 ° C. to 1350 ° C. Then, the first step of flattening the surface as shown in FIG. 9B, or the first step of performing the first heat treatment at a substrate temperature of 1100 ° C. to 1350 ° C. after the flattening, ) As shown in FIG. 9B, the first surface is planarized through the direct-bonding oxide film 25.
Semiconductor substrate 23 and a second semiconductor substrate 26 different from the first semiconductor substrate 23 are directly bonded to each other, so-called SOI
A second step of forming a (Silicon-On-Insulator) substrate, and then adjusting the back surface of the first semiconductor substrate 23 to a predetermined thickness by grinding, polishing etching, etc., as shown in FIG. 9C. C) A third step of forming a plurality of groove portions 6 on a part of the second main surface of the first semiconductor substrate 23, which is located on the side not facing the second semiconductor substrate 26, as shown in FIG. 9D. (FIG. 9 (d) is reversed in front and back from FIG. 9 (c)), (d) Embedded in each of the plurality of groove portions 6 by the organic silicon based CVD method as shown in FIG. 9 (e). Fourth step of forming oxide film 7, and (e)
Substrate temperature 1100 ° C to 1350 ° C for the buried oxide film 7
And a fifth step of performing the second heat treatment. Here, the first semiconductor substrate 23 and the second semiconductor substrate 23
The semiconductor substrate 26 is not necessarily the same kind of semiconductor substrate, and may be a combination of different kinds of semiconductors such as Si and SiC. That is, group IV, group III-V, group II-VI semiconductors other than Si and amorphous materials can be selected as the first and second semiconductor substrates. The first heat treatment in the first step may be omitted, and the heat treatment at 1100 ° C to 1350 ° C under the same conditions as the first heat treatment may be performed during the direct bonding in the second step. Alternatively, the first heat treatment may be omitted and the first heat treatment may be substituted by the second heat treatment in the fifth step.

According to the structure of the fourth feature of the present invention, the stress of the buried oxide film 71 and the direct bonding oxide film 25 is reduced, and the generation of crystal defects such as dislocations in the element formation region is suppressed.

A fifth feature of the present invention is that (a) a first semiconductor substrate having first and second main surfaces is prepared, and FIG.
4 (a), a first step of forming a plurality of grooves in a part of the first main surface of the first semiconductor substrate 23, (b) a first semiconductor as shown in FIG. 14 (a) An oxide film 25 for direct bonding is formed on the first main surface of the substrate by an organic silicon-based CVD method, and a heat treatment is performed at a substrate temperature of 1100 ° C. to 1350 ° C., and then the first semiconductor as shown in FIG. Second step of flattening oxide film 25 on the first main surface of substrate 23, or oxide film 25 on the first main surface of first semiconductor substrate 23 as shown in FIG. 14B. Second step of performing heat treatment at a substrate temperature of 1100 ° C. to 1350 ° C. after planarization, and (c) oxide film 25 for direct bonding
14C, the first semiconductor substrate 23 and the second semiconductor substrate 26, which is different from the first semiconductor substrate, are directly bonded to each other, and then the thickness of the first semiconductor substrate 23 is increased. Is thinned until a part of the direct bonding oxide film 25 is exposed, and the first semiconductor substrate 23 is formed as shown in FIG.
And a third step of forming an element formation region surrounded by the direct bonding oxide film 25 on the second main surface of. Here, the first semiconductor substrate 23 and the second semiconductor substrate 26 do not have to be the same type of semiconductor substrate, and may be a combination of different types of semiconductors such as Si and SiC. That is, group IV, group III-V, group II-VI semiconductors other than Si and amorphous materials can be selected as the first and second semiconductor substrates.

According to the fifth feature of the present invention, the buried oxide film 25 and the direct bonding oxide film 25 can be simultaneously formed by one-time organic silicon-based CVD method. The number decreases. That is, the direct bonding oxide film 25 exposed on the surface of the first semiconductor substrate 23 also functions as a buried oxide film. Further, the number of heat treatment steps is smaller than that of the fourth feature, which contributes to lowering the temperature of the process.

According to the structure of the fifth feature of the present invention, the stress of the buried oxide film 25 and the direct bonding oxide film 25 is reduced, and the generation of crystal defects such as dislocations in the element formation region is suppressed.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. It is to be understood that the following drawings are schematic representations rather than representations of accurate dimensions, although it is general in terms of representations of semiconductor device drawings. In particular, it should be noted that the relative relationship of the thickness of each layer is different from the actual ratio.

(First Embodiment) FIG. 1E shows a buried element isolation semiconductor substrate (shallow / trench element isolation (S) for a MOS integrated circuit according to a first embodiment of the present invention.
(TI) semiconductor substrate), and FIG.
2A to 2E are process cross-sectional views showing the manufacturing method up to FIG. In the element isolation semiconductor substrate according to the first embodiment of the present invention, as shown in FIG. 1E, a buried oxide film 71 is formed inside the groove formed from the surface of the semiconductor substrate 5,
The n ⁺ source region 91 and the n ⁺ drain region 9 are provided between the buried oxide film 71 and the device formation region between the buried oxide films 71.
2, gate oxide film 8, polysilicon gate electrode 98, source electrode 93, drain electrode 94, and interlayer insulating film 7
A MOS transistor composed of 9 is formed.

In the MOS integrated circuit formed on the element isolation semiconductor substrate according to the first embodiment of the present invention, the buried oxide film 71 is used.
Is relaxed by the heat treatment as described below, so that the dislocations 12 as shown in FIG. 16 described in the prior art do not occur in the element formation region. Therefore, the pn junction leakage current due to the dislocation is also reduced.

The element isolation semiconductor substrate according to the first embodiment of the present invention can be manufactured by the following steps.

(A) First, for example, a silicon oxide film 1 of 100 nm is formed on the surface of a mirror-finished silicon substrate having a plane orientation (100).
7 is formed by a steam oxidation method (wet oxidation method) or the like,
A photoresist (not shown) is applied to the surface of the oxide film 17, and the oxide film 17 is etched by the photolithography method using the photoresist as a mask. By this etching, a silicon etching mask pattern made of the oxide film 17 is formed, and the other surface of the silicon substrate 5 is exposed. Then, after removing the photoresist used for etching the oxide film, the exposed portion of the silicon substrate 5 is RIEed by RIE using the oxide film 17 as a mask, as shown in FIG. 1A, with a width of 0.3 μm and a depth of 1 μm. To form. The RIE of the silicon substrate 5 may be performed, for example, by applying a mixed gas of CF ₄ and H ₂ at a pressure of 1.3 Pa and applying a high frequency power of 13.56 MHz at 0.22 W / cm ² . Alternatively, RIE with a mixed gas of SF ₆ and O ₂ or CCl ₄ etc.
May be performed.

(B) Next, after cleaning the substrate, as shown in FIG. 1B, an organic silicon source such as TEOS (Si
The oxide film 7 is formed by the CVD method using (OC ₂ H ₅ ) ₄ ). Before depositing this oxide film, a thermal oxide film or Si
₃ N ₄ may be thinly formed. Since the oxide film 7 completely fills the groove, it is more than the depth of the groove, for example,
It is formed with a thickness of 1 μm on the entire surface of the Si substrate. As a material for filling the groove, an organic silicon source to which an oxidizing agent such as N ₂ O, O ₂ or O ₃ is added may be used. In addition, an organic silicon source, a silicon hydrogen compound such as SiH ₄ , a silicon chloride such as SiCl ₄ may be used alone or as a raw material by mixing two or more of these raw materials.
You can also fill the groove with a silicon oxide film by the method,
An oxide may be added to each raw material.

(C) Then, as shown in FIG. 1C, the silicon substrate 5 in the portion other than the portion buried in the groove is exposed to the outside and flattened by etching back by, for example, the CDE method.

(D) Since the buried oxide film 71 formed of an organic silicon source contains a large amount of impurities other than SiO ₂ , for example, water, 1100 as shown in FIG.
Heat treatment is performed at ˜1350 ° C. As shown in FIG. 1D, a slight curve (recess) is generated by the heat treatment. This treatment may be, for example, a heat treatment in N ₂ for about 2 hours, but the same result can be obtained when the atmosphere gas for the heat treatment is O ₂ , HCl, a reducing gas, or an inert gas. The case where the heat treatment is performed after removing the oxide film on the substrate other than the element isolation region and planarizing has been described. However, after performing the heat treatment first, the oxide film 7 on the substrate other than the element isolation region is removed. Then, the same effect can be obtained by flattening.

(E) Finally, as shown in FIG. 1E, an element formation region between trenches, that is, SDG
A MOS transistor is formed in the region (width 0.3 μm). The MOS transistor may be formed by a standard MOS process in which the n ⁺ drain region 92 is formed in a self-aligned manner using the polysilicon gate 78, and a description thereof will be omitted here.

After the MOS transistor is formed in the element formation region as shown in FIG. 1E, the dislocation density in the element formation region is 1 dislocation / μm ² or less as shown in FIG.
The measurement result of the dislocation density in FIG. 2 is data about an average of 5 points in a 1 mm × 1 mm square area after SEM observation after selective etching of the sample.

FIG. 3 shows a leak current of a pn junction diode having a TEG pattern corresponding to the structure of the MOS transistor. That is, the n ⁺ source region 91 and the p well 5
FIG. 3 shows the leak current of the n ⁺ p junction formed between them, and the leak current is reduced to 15 pA or less. TEG
Since the diode area of the pattern is 350 μm × 240 μm, this means that the leakage current density could be reduced to 1.7 × 10 ⁻⁸ A / cm ² or less. The results of FIG. 3 show that the first embodiment of the present invention suppressed the dislocations at the n ⁺ p junction, which is the cause of the leakage current.

FIGS. 4A, 4B and 5 show the structure of the oxide film according to the first embodiment of the present invention which enables reduction of the dislocation density and leakage current described above. It is the result of investigation using Raman scattering. That is, first, an oxide film was uniformly formed in-plane on a silicon substrate by the above-described method for forming a buried insulating film, and the structure of the oxide film (SiO ₂ ) subjected to the above-mentioned heat treatment was examined by Raman scattering spectroscopy. The result. SiO ₂ is small in Raman scattering cross-section, the peak of the Raman scattering by vibrations from the Si substrate becomes dominant in the measurement, SiO from the spectrum of the silicon substrate Raman scattering shift of SiO ₂ is formed on the surface By subtracting the Raman scattering shift spectrum of the Si substrate on which the _two films are not formed, the Raman scattering spectrum of SiO ₂ having a plurality of peaks as shown in FIG. 4A is obtained. Moreover, when this peak is separated by simulation, as shown in FIG.
It can be separated into a member ring and a multi-membered ring having 5 or more members. The method for separating the ring structure is described in C.I. J. Brainer e
t al. . J. Non-Cryst. Solids
82 (1986) 177 and the like.
In FIG. 4A, annealing 1 is heat treatment at 1000 ° C. for 1 hour, and annealing 2 is heat treatment at 1150 ° C. for 1 hour. Further, both annealing 1 and annealing 2 are N
Heat treatment in a ₂ gas atmosphere.

FIG. 5 shows the integrated intensity of the spectrum of each Raman shift for each heat treatment temperature, and the ratio to the integrated intensity of the whole (hereinafter referred to as the integrated intensity ratio). The total integrated intensity is the integrated intensity of the spectrum at a wave number of 300 to 700 cm ^−1, and is a value obtained by subtracting (excluding) the background value from the Si substrate. It can be seen that from 1100 ° C. at which the occurrence of dislocations is reduced, the integrated intensity ratio of the 3- and 4-membered rings is decreased, and the integrated intensity ratio of the multi-membered ring having 5 or more members is increased. That is, in the ring structure of SiO ₂ , the integrated intensity ratio of a 4-membered ring or less is substantially 15% or less of the whole, or the integrated intensity ratio of a multi-membered ring having a 5-membered ring or more is substantially 8% of the whole.
It can be seen that if it is 5% or more, the stress of the embedding material, which is the cause of the dislocation, is relaxed, and the dislocation can be suppressed. Considering the error of Raman scattering measurement, as shown in FIG. 6, about 20% or less for 4-membered rings or less and about 8% for 5-membered rings or more.
It can be said that the effect of the present invention can be obtained if it is 0% or more.

FIG. 6 shows the etching rate (etching rate) of the oxide film according to the first embodiment of the present invention. The heat treatment temperature of the present invention, that is, the etching rate of the oxide film heat-treated at 1100 ° C. to 1350 ° C. by the NH ₄ F (ammonium fluoride) solution is 130 nm / min or less, and the etching of the thermal oxide film shown on the left side of FIG. 6 is performed. It is almost equal to the rate. An oxide film deposited by an organic silicon-based CVD method and not heat-treated, a so-called "as-devo" oxide film has an N-rate at an etching rate of about 650 nm / min.
Etched with H ₄ F. Therefore, it can be seen that the high-temperature annealing of the present invention reduces the etching rate of the oxide film to 80% for a 5-membered ring or more and reduces the etching rate of the oxide film. It can be said that the etching rates of the oxide film and the content rates of SiO ₂ of the 5-membered ring and the 3-membered ring measured by Raman scattering correspond to each other.

Although the oxide film 7 is formed by the CVD method using the organic silicon source such as TEOS in the step (b) in the first embodiment of the present invention, the oxide film forming method is as follows. A method other than the organic silicon-based CVD may be used. For example, a so-called SOG (Spin-on-glass) method may be used.
In the SOG method, resin glass in which polysiloxane or the like is dissolved in a solvent such as acetone or xylene is applied using a spinner or the like, and the solvent is removed by prebaking at 80 ° C to 100 ° C.
This is a method of forming a SiO ₂ film. SiO _{2 by} SOG method
After forming the film, heat treatment at 1100 to 1200 ° C. provides the same effect as above. That is, also in the case of the SOG method, the integrated intensity ratio of a 5-membered ring or more multimembered ring obtained from the Raman scattering spectrum is substantially 85% or more of the total, 3 or more.
When the integrated intensity ratio of the member ring or the 4-membered ring is substantially 15% or less of the whole, dislocations are suppressed and the leak current is reduced. For resin glass, Japanese Patent Publication Sho 58-51422
No. 3985597, 400404
No. 4, for example. These resin glasses are commercially available, for example Allied Signal-Accuspin 418/7.
20, Allied Signal-Accuglass T-11 / T-14, Dow-Corning 8
05, Owens-Illinois650, General Electric SR125 / SR124
Etc. may be used. After prebaking at 80 ° C-100 ° C,
Perform low temperature annealing at about 600 ° C, then 1100
You may make it perform high temperature annealing of (degreeC) -1350 degreeC.

(Second Embodiment) FIG. 7 (f) is a sectional view showing the structure of an element isolation semiconductor substrate for a bipolar integrated circuit according to a second embodiment of the present invention. 7
7E is a schematic cross-sectional view showing the manufacturing method up to the structure of FIG. The manufacturing method of the element isolation semiconductor substrate for the bipolar integrated circuit according to the second embodiment of the present invention is as follows: (a) First, as shown in FIG. 7A, the surface of the p-type silicon substrate 13 is oxidized by steam. A SiO ₂ film 14 of _{200 to} 350 nm is formed.

(B) Next, this SiO ₂ film 14 is patterned by photolithography using a photoresist as a mask as shown in FIG. 7B to expose a part of the surface of the silicon substrate 13. The diffusion mask 14 is formed. Then, using this diffusion mask 14, Sb (antimony) is thermally diffused to obtain an impurity density of 3 × 10 ²⁰ cm ⁻³ , n.
^{+ A} buried layer 15 is formed.

(C) After removing the oxide film, as shown in FIG. 7 (c), a silane compound such as SiH ₄ or SiH ₂ Cl ₂ and a phosphorus compound such as PH ₃ as a doping gas are caused to flow in an H ₂ carrier gas. While decomposing at high temperature, film thickness of 2.5 on the substrate
An n layer 16 of μm is epitaxially grown.

(D) Next, an oxide film 17 having a thickness of 0.3 μm is formed on the n layer 16 and a photoresist pattern is formed on the oxide film 17 by photolithography.
Open a window in the oxide film 17 using the photoresist as a mask,
An etching mask 17 is formed. After that, the photoresist is removed, and the n layer 16 is selectively etched using the oxide film 17 as a mask layer. As shown in FIG.
A groove having a depth of about 3 μm is formed in the layer 16. Since this selective etching has anisotropy, CCl ₄ or C
_The RIE method using ₂ Br ₂ F ₄ is used. When the groove has a large aspect ratio, low temperature microwave plasma etching using SF ₆ gas plasma is preferable. For example, plasma etching may be performed by cooling the substrate temperature to −80 ° C. to −150 ° C.

(E) Further, similar to the case of the first embodiment of the present invention, the groove is filled with the CVD method using the organic silicon source such as TEOS, TMOS, TPOS as the raw material as shown in FIG. 7 (e).

(F) Finally, after flattening the surface as shown in FIG. 8 (f), it is heat-treated at a high temperature of 1100 to 1350 ° C. for 2 hours in an N ₂ atmosphere. The atmosphere for this heat treatment may be O ₂ , HCl, reducing gas, or inert gas other than N ₂ gas. Note that the order is changed from the above description, and 1100 ° C to 1350 ° C immediately after CVD.
The same effect can be obtained by first performing the heat treatment of (1) and then performing etch back, that is, flattening. Using this groove as an element isolation region, an n ⁺ collector extraction region 20, ap ⁺ base region 21, and an n ⁺ emitter region 22 are formed between them, as shown in FIG.
A bipolar transistor is completed as shown in (f). FIG. 7 (f) shows an emitter metal electrode for simplification.
Although illustration of a collector metal electrode, an interlayer insulating film, etc. is omitted, it is a standard bipolar IC structure, and these metal electrodes and insulating films are naturally provided.

FIG. 8 shows n according to the second embodiment of the present invention.
It is the result of investigating the device characteristics of the pn bipolar transistor about the leak current using the TEG pattern. p
⁺ P ⁺ between the base region 21 and the n collector region 16
The leak current of the TEG pattern corresponding to the -n junction was measured and plotted against each heat treatment temperature. The diode area of the TEG pattern is 350 × 240 μm.
In the temperature range of the present invention (1100 ° C to 1350 ° C), the leak current of the p ⁺ -n junction is 1.7 × 10 ^-8 A / cm ^2.
It is found to be lower than that, and it can be seen that the dislocations that cause the leakage current are suppressed.

(Third Embodiment) FIG. 9G is a sectional view of an element isolation semiconductor substrate according to a third embodiment of the present invention, and FIGS. 9A to 9F are FIG. It is a typical sectional view showing a manufacturing method up to g). In the third embodiment of the present invention, the case of application to a BiCMOS integrated circuit will be described, but it goes without saying that it can also be applied to a MOS integrated circuit, a bipolar integrated circuit, a static induction transistor (SIT) integrated circuit and the like. A method for manufacturing a semiconductor substrate for a BiCMOS integrated circuit according to a third embodiment of the present invention is as follows: (a) First, as shown in FIG. 9A, a first main surface having a predetermined plane orientation such as a (100) plane. N-type silicon substrate (semiconductor substrate) 23 having a front surface (front surface) and a second main surface (back surface) 23
Prepare A SiO ₂ film 56 having a thickness of 1 μm is formed on the surface (first main surface) of the n-type silicon substrate 23 by the CVD method.
To form CVD is TEOS, HMDS (Hexam
ethidisiloxane; Si ₂ O (C
H ₃ ) ₆ ), OMCTS (Octametylcyc
lotetrasiloxane; c (OSi (C
An organic silicon source such as H ₃ ) ₂ ) ₄ ) may be used.

(B) Next, the SiO ₂ CVD n-type silicon substrate 23 shown in FIG. 9A is placed at 1100 ° C. to 1200 ° C.
Hold for 2 hours in N ₂ atmosphere and heat-treat. After that, mechanical and chemical polishing (CM
P) method or the like is used to flatten the oxide film to a thickness of 0.3 μm, and an oxide film 25 for direct bonding (hereinafter referred to as “SDB”) is formed as shown in FIG. 9B.

(C) Next, a silicon substrate 26 having a mirror-polished surface is separately prepared, and the n-type silicon substrate 23 and the silicon substrate 26 are interposed via the SDB oxide film 25 as shown in FIG. 9C. Are bonded to each other and heat-treated at 1100 ° C. for 1 to 2 hours to form an SDB substrate. At this time, a voltage may be applied for heat treatment. Then n
The back surface (second main surface) of the type silicon substrate 23 is polished so that the thickness of the n type silicon substrate 23 is adjusted to 1 μm. In addition, the bonding of the silicon substrate is 1
If it is performed at 100 ° C. or higher, the same effect as the heat treatment of (ii) can be obtained, so that the heat treatment of (ii) can be omitted and the heat treatment at the time of bonding can also be used. . Also, the heat treatment at the time of bonding is set to 1200 ° C, or the heat treatment at the time of bonding is set to 1100 ° C.
It is also possible to perform it in two steps of 1,200 ° C.

(D) Next, the state of FIG. 9C is turned upside down, and the back surface (second main surface) of the n-type silicon substrate 23 is turned up, as shown in FIG. 9D. 300 nm is formed on the second main surface of the n-type silicon substrate 23 formed by the SDB method.
Of the thermal oxide film 17 is formed by photolithography using a photoresist as a mask to remove a part of the thermal oxide film 17 into a predetermined pattern by etching, and the photoresist used as an etching mask for the thermal oxide film 17 is removed. Remove. Using the thermal oxide film 17 thus obtained as a mask, RIE using CCl ₄ , SF ₆ or the like is performed, and as shown in FIG.
As shown in FIG.
Etching to a depth of 1 μm until the oxide film 25 for
The U groove 6 is formed.

(E) Next, as shown in FIG.
OS, TMCTS (1,3,5,7-tetramet
hylcyclotetratrasiloxane; c (O
SiHCH ₃ ) ₄ or TES (Triethylsil)
ane; SiH (C ₂ H ₅ ) ₃ ) or the like by a low pressure CVD method (LPCVD method) using an organic silicon source or the like.
An iO ₂ film 7 is deposited in a thickness of 1.1 to 1.5 μm. LPCVD
ECR plasma CVD method or ICP-CVD instead of the method
The method may be used. As a material for filling the U groove 6,
An oxidizer such as N ₂ O, O ₂ , O _{3 is} added to the organic silicon source.
It may be a combination of the above. Also, an organic silicon source,
The U groove 6 can be formed into a silicon oxide film 7 by a CVD method using a silicon hydride compound such as SiH ₄ or a silicon chloride such as SiCl ₄ alone or a mixture of two or more of any of these materials. It is also possible to bury it in, and to add an oxide to each raw material.

(F) Then, CVD by the CDE method or the like
By etching back the SiO ₂ film 7, the surface of the n-type silicon substrate 23 other than the portion embedded in the U groove 6 is exposed to the outside and flattened as shown in FIG.

(G) Since the buried oxide film 71 formed by the CVD method using the organic silicon source in the state shown in FIG. 9 (f) contains a large amount of impurities other than SiO ₂ , such as water, at 1100 to 1350 ° C. Perform heat treatment.
This heat treatment may be carried out, for example, in N ₂ for about 2 hours, but the same results can be obtained when the atmosphere gas at this time is O ₂ , HCl, a reducing gas, an inert gas or CO, CO ₂ .
After this heat treatment, in the element formation region made of the n-type silicon substrate 23 surrounded by the buried oxide film 71, a well-known MOS process and a bipolar process are used to form CMOSs.
When the circuit and the bipolar circuit are constructed, a BiCMOS integrated circuit as shown in FIG. 9 (g) is completed. It should be noted that the heat treatment at 1100 ° C. to 1200 ° C. in the step (b) above is omitted, and 1100 ° C. to 1 ° C. in the step (g) above is omitted.
Even if the heat treatment at 350 ° C. is substituted, the object of the present invention can be almost achieved. In this case, there is an advantage that the process is simplified.

As described above, a CV made of an organic silicon source such as TEOS as a raw material is used as an element isolation insulating film.
In the case of using the insulating material by the D method, the stress is reduced by performing the heat treatment of the third embodiment of the present invention,
It is possible to reduce the generation and multiplication of dislocations during the formation of the element isolation region or the subsequent heat treatment in the element manufacturing process. Therefore, according to the third embodiment of the present invention, the leakage current value of the pn junction formed in the element formation region can be reduced to 1.7 × 10 ⁻⁸ A / cm ² or less, and the BiCMOS Higher performance of the integrated circuit can be realized.

The aspect ratio d / l of the U groove depth d with respect to the U groove width l _{1 in the first} to third embodiments.
₁ is an example, and need not be limited to the aspect ratio described above. As shown in FIG. 10, the aspect ratio d / l ₁
If the oxide film embedded in the U-groove of 10 or less is heat-treated under the heat treatment conditions (1100 ° C. to 1350 ° C.) of the present invention, the defect density decreases, so if the aspect ratio d / l ₁ is 10 or less, it is appropriate. You may choose. As shown in FIG. 10, it is understood that when the heat treatment conditions of the present invention such as 1000 ° C. and 1050 ° C. are out of the range, the defect density is not reduced even when the aspect ratio d / l ₁ is 10 or less.

[0058] Figure 13 is a case of changing the width l ₁ of the isolation trench in the repetitive pattern of unidirectional line and space, the ratio l ₁ / l ₂ of the width l ₂ of the element formation region,
It is the result of examining the defect density (dislocation pit density) in the element formation region. That is, in the line-and-space pattern arranged as in FIG. 11 the U-groove 6 of the isolation region, the ratio of the width l ₂ of width l ₁ and the element formation region of the element isolation region of 0.003 to 10 The measurement was performed by making the buried element isolation substrate by changing it between intervals and making the dislocation pits in the element forming region selectively etched to make it visible. FIG. 11A is a sectional view taken along line XX of FIG. 11B. In this case, CV made from organic silicon source
An oxide film is buried in the U groove by the D method,
FIG. 13 shows the comparison result obtained by performing heat treatment at 0, 1100, 1200 and 1350 ° C. for 2 hours. As shown in FIG. 13, the defects increase when l ₁ / l ₂ is 1.5 or more. Therefore, the present invention is effective when the width l ₁ of the element isolation region is 1.5 times or less the width l ₂ of the element formation region, and within this range, l ₁ / in the _first to third embodiments Values other than l ₂ may be arbitrarily selected and used. l ₁ / l ₂ ≤
The condition of 1.5 is defined by a line and space pattern in a fixed direction. Figure 1
As shown in 2, when there is a line-and-space pattern in the XX direction and a line-and-space direction in the YY direction, it is defined in either direction.
_At least one of the values _1x / l _2x or l _1y / l _2y is 1.5
The following may be sufficient. The pattern shown in Fig. 12 is MOS.
This is a typical pattern in DRAM and the like.

(Fourth Embodiment) FIG. 14 (e) is a sectional view of an element isolation semiconductor substrate according to a fourth embodiment of the present invention, and FIGS. 14 (a) to 14 (d) show FIG. It is a typical sectional view showing a manufacturing method up to e). Fourth Embodiment of the Present Invention
In the embodiment of the present invention, the case of applying to a CMOS integrated circuit will be described, but other M such as nMOS (integrated circuit)
Of course, it can be applied to an OS integrated circuit, a bipolar integrated circuit, a BiCMOS integrated circuit, a SIT integrated circuit and the like. A method of manufacturing a semiconductor substrate for a CMOS integrated circuit according to a fourth embodiment of the present invention is as follows: (a) First, as shown in FIG. 14A, a first main surface (front surface) and a second main surface An n-type (100) plane silicon substrate 23 having a (rear surface) is prepared, and a V groove having a depth of 1.2 to 1.5 μm is formed at a predetermined location on the first main surface thereof. The predetermined location means a location that will eventually become an element isolation region. The V groove is formed by a well-known method, for example, a thermal oxide film of 150 to 300 nm is formed on the surface (first main surface) of the n-type silicon substrate 23, and a predetermined portion of the thermal oxide film is formed by photolithography. Is removed by etching, and the n-type silicon substrate 23 may be anisotropically etched using KOH or ethylenediaminepyrocatechol (EDP) with this thermal oxide film as a mask.
The V groove is an example, and may be a U groove as in the first to third embodiments of the present invention. In case of U groove, CCl ₄ , S
RIE and ECR using iCl ₄ , PCl ₃ , SF ₆ etc.
It may be formed by ion etching so as to have a depth of 1.2 to 1.5 μm. In either case of the U groove or the V groove, it is preferable that the ratio l ₁ / l ₂ of the width l _{1 of the} separation groove and the width l ₂ of the element formation region is 1.5 or less. Next TEO
An oxide film having a thickness of about 1.7 to 2 μm is formed by the LPCVD method using an organic silicon source such as S, DADBS, OMCTS, TMS, and HMD. The thickness of 1.7 to 2 μm means the thickness of the flat portion where the groove is not formed. Instead of the organic silicon CVD method, coated glass (SOG) may be coated with a spinner or the like.

(B) Next, SiO ₂ CVD shown in FIG.
The n-type silicon substrate 23 thus prepared is heat-treated by holding it at 1200 ° C. in an N ₂ atmosphere for 2 hours. Then, the oxide film is flattened to a thickness of 0.3 μm by the CMP method or the like while fixing the back surface (second main surface) by suction, and the SDB oxide film 2 is formed.
5 is formed as shown in FIG. At this time, similar results can be obtained even if the atmosphere gas is O ₂ , HCl, reducing gas, inert gas or CO, CO ₂ .

(C) Next, a silicon substrate 26 having a mirror-polished surface is separately prepared, and the n-type silicon substrate 23 and the silicon substrate 26 are interposed via the SDB oxide film 25 as shown in FIG. 14 (c). Are pasted together and 1100 ° C-1
By heat treatment at 150 ° C for 60 minutes to 2 hours, SD
Form a B substrate. At this time, the heat treatment may be performed by applying a pulse voltage in a reduced pressure (vacuum) state. For example, 0.
The pressure may be reduced to 1 Pa and a pulse voltage of ± 350 V may be applied at 800 ° C. for about 10 minutes.

(D) Next, the back surface (second main surface) of the n-type silicon substrate 23 is polished so that the thickness of the n-type silicon substrate 23 becomes 1 μm.
A part of the SDB oxide film 25 is exposed on the back surface of the. FIG.
FIG. 14D is a sectional view of the substrate in this state.
The vertical relationship is reversed from that of (c), and the n-type silicon substrate 23 is positioned on the upper side. Therefore, by this step, the element formation region 23 surrounded by the buried oxide film 25 is completed on the second main surface of the n-type silicon substrate.

(E) Next, p is formed inside the element formation region 23 by using a well-known MOS process as shown in FIG.
Well 31 is formed, and n ⁺ is formed inside p well 31.
Source / drain regions 32 and 33, and p ⁺ source / drain regions 34 and 35 are formed in the portions of the element formation region 23 where the p well is not formed, and gate oxide films and polysilicon gate electrodes 98 and 98 are formed on the surfaces thereof. , If the metal wiring is formed, the CMOS according to the fourth embodiment of the present invention
The integrated circuit is completed.

In the fourth embodiment of the present invention, S is applied by one-time organosilicon CVD method (or SOG application).
A DB oxide film and a buried oxide film can be formed simultaneously, as shown in FIG.
The number of steps is smaller than that of the third embodiment shown in (a) to (g), and the productivity is increased accordingly. Further, as compared with the third embodiment, the number of heat treatment steps is reduced, so that a semiconductor device can be manufactured with less heat history, and it is easy to reduce crystal defects and realize a fine structure.

Further, the organic silicon-based CVD method has excellent step coverage and, moreover, a thick oxide film can be formed at a lower temperature and in a shorter time than the SDB oxide film is formed by thermal oxidation.
Oxidation induced defects (OSF) as in the case of thermal oxidation do not occur. Therefore, there are few crystal defects in the element formation region, and as a result, the leak current in the CMOS circuit is reduced. In addition, since the step coverage is excellent,
Not limited to the case as shown in (a), an SOI substrate can be formed using a substrate having various uneven shapes without being affected by the flatness.

Although it has been described above that the U groove may be used in the fourth embodiment of the present invention, the aspect ratio in that case is 1
Needless to say, it is preferably 0 or less. Also in the case of the V groove, the ratio d _v / l _{v1 of} the depth d _v and the opening width l _v1 on the surface side of the V groove is preferably 10 or less.

As described above, in the CMOS integrated circuit, when the insulating material by CVD using the organic silicon source such as TEOS as the raw material is used as the element isolation insulating film, the heat treatment of the fourth embodiment of the present invention is performed. As a result, stress can be reduced, and generation or multiplication of dislocations can be reduced during the formation of the element isolation region or the subsequent heat treatment in the element manufacturing process. Therefore, according to the fourth embodiment of the present invention, the value of the leak current of the pn junction formed in the element formation region is 1.7 × 10 ⁻⁸ A / cm ^2.
It can be reduced to the following, and high performance of CMOS / LSI can be realized.

[0068] Incidentally, in the first to fourth embodiments of the present invention has been described depositing a silicon oxide film by atmospheric pressure CVD or LPCVD method (SiO ₂ film), a SiO ₂ CVD Can also be performed by a liquid phase CVD method. In this case, the O ₂ gas is subjected to microwave discharge and T
The temperature of the substrate is kept below the boiling point of the deposited particles by reacting with MS-4.
The silicon oxide film may be deposited at 0 ° C. Liquid phase C
After VD, if the heat treatment is performed in the same manner as in the first to fourth embodiments of the present invention, the same effect as in the above-described embodiment can be obtained.
Furthermore, a SiO ₂ film may be formed in the U groove by anodic oxidation using ethylene glycol or N-methylacetamide as a solvent and a small amount of potassium nitrate as a solvent and using a silicon substrate as an anode and platinum as a counter electrode. Also in this case, the same effect can be obtained by performing the heat treatment at 1100 ° C. to 1350 ° C. similar to the above-mentioned respective embodiments. Also, plasma C
It is also possible to fill the U groove with a SiO ₂ film formed by the VD method.

[0069]

As described above in detail, the MOS integrated circuit, the bipolar integrated circuit, the BiCMO on the silicon semiconductor substrate.
In the S integrated circuit or the SIT integrated circuit, when an organic silicon source, for example, an insulating material by a CVD method using TEOS as a raw material is used as the element isolation insulating film, the heat treatment of the present invention reduces stress to reduce the element isolation region. It is possible to reduce the occurrence and multiplication of dislocations during formation or during heat treatment in the element manufacturing process thereafter. Therefore, according to the present invention, the leakage current value of the pn junction formed in the element formation region is 1.7 × 10 ⁻⁸ A /
It can be reduced to cm ² or less, and high performance of integrated circuits such as MOS LSI and bipolar LSI can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of an embedded element isolation semiconductor substrate for a MOS integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a heat treatment temperature of a buried oxide film and a crystal defect density generated in an element formation region.

FIG. 3 is a diagram showing a relationship between a heat treatment temperature of a buried oxide film and a leak current of a pn junction formed in an element formation region.

[Fig. 4] When heat treatment is performed (annealing 1, annealing 2)
FIG. 4 is a Raman scattering spectrum diagram by an oxide film in the case of not and.

FIG. 5 is a diagram showing the heat treatment temperature dependence of the oxide film of the integrated intensity ratio of each peak of Raman scattering.

FIG. 6 is a diagram showing a change in etching rate due to heat treatment.

FIG. 7 is a diagram showing a step of manufacturing a buried element isolation semiconductor substrate for a bipolar integrated circuit according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a relationship between a heat treatment temperature of a buried oxide film and a leak current of a pn junction formed in an element formation region.

FIG. 9 is a BiCMOS according to a third embodiment of the present invention.
It is a figure which shows the manufacturing process of the embedded element isolation semiconductor substrate for integrated circuits.

FIG. 10 is a diagram showing a relationship between an aspect ratio of a groove and a defect density.

FIG. 11 is a diagram showing the relationship between the width of a groove and the width of an element formation layer.

FIG. 12 is a plan view showing a case where line and space patterns exist in two directions.

FIG. 13 is l ₁ / l shown in FIG. 11 (or FIG. 12)
FIG. 3 is a diagram showing the relationship between ₂ and the defect density.

FIG. 14 is a diagram showing a step of manufacturing a buried element isolation semiconductor substrate for a CMOS integrated circuit according to a fourth embodiment of the invention.

FIG. 15 is a diagram showing a structure of an element isolation semiconductor substrate by a typical LOCOS method as a conventional technique.

FIG. 16 is a diagram showing generation of dislocations in a conventional buried element isolation technique.

[Explanation of symbols]

5,13 p-type silicon substrate 6 U-groove 7,71,77 buried oxide film 8 gate oxide film 12 dislocation 14,17 oxide film 15 n ⁺ buried region 16 n epitaxial growth layer 20 n ⁺ collector electrode extraction region 21 p base region 22 n ⁺ emitter region 23, 81 silicon substrate 24, 25 SDB oxide film 26 n-type silicon substrate 78, 79 interlayer insulating film 82 oxide film 83 element forming region 88 nitride film 91 n ⁺ source region 92 n ⁺ drain region 93 source electrode 94 drain electrode 98,99 polysilicon gate electrode

Front page continuation (72) Inventor Hiroyuki Kamijo 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa, Ltd. Inside Toshiba Corporation Yokohama office Research and Development Center (72) Inventor Tsunehiro Kita 1 Komukai Toshiba-cho 1 Sachi-ku, Kawasaki-shi, Kanagawa Stock Company Toshiba Tamagawa factory

Claims (23)

[Claims] 1. A plurality of trenches formed on a part of the surface of a semiconductor substrate, and a buried oxide film formed inside the trenches.
An element isolation semiconductor substrate comprising a groove portion and an element forming region formed between the groove portion, wherein the buried oxide film is formed by an organic silicon-based CVD method, a coating glass coating method, or an anodizing method. An element isolation semiconductor substrate, which is an oxide film formed by the method of 1) and heat-treated at a temperature of 1100 to 1350 ° C. 2. An aspect ratio d / l defined by the ratio of the depth d of the groove and the dimension of the width l ₁ of the opening of the groove.
The element isolation semiconductor substrate according to claim 1, wherein ₁ is 10 or less. 3. A line-and-space repeating pattern in a predetermined direction, wherein a width l ₁ of an opening of the groove is a minimum space width, and a width l ₂ of the element forming region is a minimum line width. L ₁ and l defined by the direction of
Isolation semiconductor substrate according to claim 1, wherein the ratio l ₁ / l ₂ and ₂ is 1.5 or less. 4. A plurality of groove portions formed in a part of the surface of the semiconductor substrate, and a buried oxide film formed inside the groove portions,
A device isolation semiconductor substrate comprising a groove portion and an element forming region formed between the groove portion, wherein the buried oxide film has a ring structure of a 5-membered ring or more and a ring structure of a 4-membered ring or less, respectively. An element isolation semiconductor substrate, which is an amorphous silicon oxide film containing a certain ratio. 5. The predetermined ratio of the ring structure is determined by the ratio of the integrated intensity of Raman shift corresponding to each of the ring structures to the total integrated intensity, and the 5-membered ring or more is substantially 85% or more of the total. , And 15% or less of 4 members
The element isolation semiconductor substrate according to claim 4, wherein the element isolation semiconductor substrate has a structure satisfying one or both of the following conditions. 6. The buried oxide film is an organic silicon based CVD.
5. The element isolation semiconductor substrate according to claim 4, which is an oxide film formed by any one of a coating method, a coating glass coating method, and an anodic oxidation method, and which is heat-treated at a temperature of 1100 to 1350 ° C. 6. 7. The aspect ratio d / l defined by the ratio of the depth d of the groove and the dimension of the width l ₁ of the opening of the groove.
The element isolation semiconductor substrate according to claim 4, wherein ₁ is 10 or less. 8. A line-and-space repeating pattern in a predetermined direction, wherein a width l ₁ of an opening of the groove is a minimum space width, and a width l ₂ of the element forming region is a minimum line width. L ₁ and l defined by the direction of
Isolation semiconductor substrate according to claim 4, wherein the ₂ ratio of l ₁ / l ₂ is 1.5 or less. 9. A method of manufacturing an element isolation semiconductor substrate, which comprises at least the following steps. (A) First step of forming a plurality of grooves on a part of the surface of a semiconductor substrate (b) Second step of filling an oxide film in the grooves by an organic silicon based CVD method (c) Substrate temperature of the oxide film is 1100 ° C. Third step of heat treatment at ˜1350 ° C. 10. The organic silicon-based CVD method in the second step is a normal pressure CVD method, a low pressure CVD method, a plasma CV method.
10. The method for manufacturing an element isolation semiconductor substrate according to claim 9, which is one of a D method, a photo CVD method and a liquid phase CVD method. 11. The heat treatment in the third step includes any one of reducing gas such as H ₂ , inert gas such as He, Ne, Ar, Kr, and Xe, O ₂ , N ₂ , HCl, CO, and CO ₂ . 10. The method for manufacturing an element isolation semiconductor substrate according to claim 9, wherein the method is performed in a mixed gas composed of two or more kinds of gases selected from the above. 12. The second step is characterized in that an oxide film is deposited thicker than a groove and then the surface of the semiconductor substrate is planarized until the surface is substantially exposed.
A method for manufacturing the element isolation semiconductor substrate described. 13. The second step is a step of depositing an oxide film thicker than a groove portion, and the step of flattening a surface of the semiconductor substrate after the third step until the surface of the semiconductor substrate is substantially exposed. 10. The method for manufacturing an element isolation semiconductor substrate according to claim 9, further comprising four steps. 14. An aspect ratio d defined by the ratio of the depth d of the groove and the dimension of the groove width l ₁ of the opening of the groove.
/ L ₁ is 10 or less, The manufacturing method of the element isolation semiconductor substrate of Claim 9 characterized by the above-mentioned. 15. A line-and-space repeating pattern in a predetermined direction in which the width l ₁ of the groove portion is a minimum space width and the width l ₂ of the element forming region is a minimum line width, and manufacturing method of the element isolation semiconductor substrate according to claim 9, wherein the ratio l ₁ / l ₂ between l ₁ and l ₂ is defined is 1.5 or less. 16. A method for manufacturing an element isolation semiconductor substrate, comprising at least the following steps. (A) A first semiconductor substrate having first and second main surfaces is prepared, and an oxide film for direct bonding is provided on the first main surface with an organic silicon C
Formed by VD method, substrate temperature 1100 ° C to 1350 ° C
In the first step of flattening the first main surface after performing the first heat treatment in, or after the first main surface of the first semiconductor substrate is flattened at a substrate temperature of 1100 ° C to 1350 ° C. 1. First step of performing heat treatment of (1) The first semiconductor substrate and a second semiconductor substrate different from the first semiconductor substrate are directly bonded via the direct bonding oxide film, and then A second step of adjusting the first semiconductor substrate to have a predetermined thickness (c) a third step of forming a plurality of grooves on a part of the second main surface of the first semiconductor substrate (d) Fourth step of forming a buried oxide film in a plurality of trenches by an organic silicon-based CVD method (e) A substrate temperature of 1100 ° C. to 13 ° C. for the buried oxide film
Fifth step of performing the second heat treatment at 50 ° C 17. The organic silicon-based CVD method in the first and fourth steps is any one of an atmospheric pressure CVD method, a low pressure CVD method, a plasma CV method D, an optical CVD method and a liquid phase CVD method. 17. The method for manufacturing an element isolation semiconductor substrate according to claim 16, which is characterized in that. 18. The first and second heat treatments include reducing gas such as H ₂ , inert gas such as He, Ne, Ar, Kr, and Xe, O ₂ , N ₂ , HCl, CO, and CO ₂ . 17. The method for manufacturing an element isolation semiconductor substrate according to claim 16, wherein the method is performed in any one of the above or in a mixed gas consisting of two or more kinds of gases selected from these. 19. The fourth step is characterized in that an oxide film is deposited thicker than a groove portion, and then the surface is planarized until the second main surface of the first semiconductor substrate is substantially exposed. 17. The method for manufacturing an element isolation semiconductor substrate according to claim 16. 20. The fourth step is a step of depositing an oxide film thicker than a groove portion, and after the fifth step, until the second surface of the first semiconductor substrate is substantially exposed. 17. The method for manufacturing an element isolation semiconductor substrate according to claim 16, further comprising a sixth step of flattening the surface. 21. An aspect ratio d defined by the ratio of the depth d of the groove and the dimension of the groove width l ₁ of the opening of the groove.
/ L ₁ is 10 or less, The manufacturing method of the element isolation semiconductor substrate of Claim 16 characterized by the above-mentioned. 22. In a line-and-space repeating pattern in a predetermined direction in which the width l ₁ of the groove portion is the minimum space width and the width l ₂ of the element forming region is the minimum line width, manufacturing method of the element isolation semiconductor substrate according to claim 16, wherein the ratio l ₁ / l ₂ between l ₁ and l ₂ is defined is 1.5 or less. 23. A method of manufacturing an element isolation semiconductor substrate, comprising at least the following steps. (A) A first step of preparing a first semiconductor substrate having first and second main surfaces and forming a plurality of grooves in a part of the first main surface (b) the first main surface An oxide film for direct bonding is formed on the substrate by organosilicon CVD, and the substrate temperature is 1100 ° C. to 135 °
A second step of flattening the first main surface after heat treatment at 0 ° C., or a substrate temperature of 1100 ° C. to 1 after flattening the first main surface
Second step of performing heat treatment at 350 ° C. (c) Directly bonding the first semiconductor substrate and a second semiconductor substrate different from the first semiconductor substrate through the direct bonding oxide film, Then, the thickness of the first semiconductor substrate is reduced until a part of the direct bonding oxide film is exposed, and the second main surface of the first semiconductor substrate is surrounded by the direct bonding oxide film. Third step of forming element formation region