JPH09204293A - Parallel data transmitting system and majority judging circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax restriction as against the number of output lines by inverting the code ('1' or '0') of input data when a majority logical level forming parallel data is changed. SOLUTION: A transmission side 1 compares transmission data and input data which are one digit-delayed by a data change detecting part 13, it is detected that the number of bits detecting the change is the majority of the number of codes forming parallel data by a simultaneous change number detecting part 14, input data is inverted by the output of the simultaneous change detecting part 14 so as to transmit it when the number of the bits detecting change is the mojority of the number of the codes forming parallel data, input data is transmitted without inversion by the output of the simultaneous change detecting part 14 when the number of the bits detecting change is equal to below the half of the number of the codes forming parallel data and the output of the simultaneous change detecting part 14 is transmitted as a flag displaying presence or absence of inversion. In the meantime, at a reception side, reception data is inverted so as to be adopted as reproduction data when the flag indicates inversion and reception data is adopted as reproduction data unless the flag indicates inversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data transmission system, and more particularly to a parallel data transmission system, and more particularly to a parallel data transmission system capable of simultaneously transmitting multiple bits.

In a large-scale integrated circuit, when the logic output levels of a large number of output buffers change at the same time, a transient current at the time of the change causes a switching noise to flow on the power supply line and the ground line of the large-scale integrated circuit. For this reason, the voltage of the power supply line and the voltage of the ground line, which should be originally constant, are changed, which causes malfunction of the circuit forming the large-scale integrated circuit. Therefore, in order to prevent such a malfunction, the area sandwiched between the output ground lines is defined as one group, and the maximum number of output lines from the output buffer that can be arranged in the group is restricted.

Therefore, when the number of codes forming the parallel data is large, the codes forming the parallel data cannot be accommodated in the same group, and the propagation delay time of the codes forming the parallel data in the large scale integrated circuit is reduced. You will not be able to match. The only way to compensate for this is by using the wiring pattern on the printed circuit board, but since the electrical characteristics of the wiring in the large-scale integrated circuit and the wiring on the printed circuit board are not the same, compensation on the printed circuit board is not possible. Nearly impossible.
In the worst case, due to the above restrictions, it may not be possible to arrange all the required signal lines even if the number of pins in the package of the large-scale integrated circuit is large.

Further, when a large-scale integrated circuit is operated at high speed, it is necessary to terminate with a resistor in order to match the characteristic impedance of the wiring between the large-scale integrated circuits and the impedance looking into the large-scale integrated circuit. Since the current flowing through the terminating resistor is supplied from the output buffer of the large scale integrated circuit, the power consumption of the large scale integrated circuit is increased by the termination. Then, when the codes forming the parallel data are all "1" or all "0", the increase in power consumption of the large-scale integrated circuit is maximized. Therefore, the number of output signal lines from the large-scale integrated circuit is limited, and even if the number of pins of the package of the large-scale integrated circuit is large, it is impossible to accommodate all necessary functions.

Therefore, it is desired to realize a parallel data transmission system capable of relaxing restrictions on the number of output lines in the same group and the number of output lines per package.

[0006]

2. Description of the Related Art Conventionally, the number of output lines in the same group is
Either limiting the number of changes allowed for the codes forming the parallel data or reducing the number of codes changing at the same time by providing a phase difference between the codes forming the parallel data.

Further, the number of output lines of the package has been determined in consideration of the increase in power consumption due to the provision of the terminating resistor.

[0008]

If the number of output lines in the same group is limited to the number of changes allowed for the codes forming the parallel data, the propagation delay time for the codes forming the parallel data varies and the phase Margin is reduced. On the other hand, if a phase difference is provided between the codes forming the parallel data, the transient current when the codes change simultaneously can be reduced, but this is also realized at the expense of the phase margin.

Further, determining the number of output lines of the package in consideration of the increase in power consumption due to the provision of the terminating resistor is equivalent to giving up the densification of the large scale integrated circuit. The present invention, in order to solve such a problem, a parallel data transmission system that suppresses the number of changes in codes forming parallel data,
Another object of the present invention is to provide a parallel data transmission method that suppresses the number of specific codes among the codes forming the parallel data, thereby relaxing the constraint on the number of output lines in a large scale integrated circuit.

[0010]

The first means of the present invention is as follows:
By comparing the input data at a certain timing and the transmission data corresponding to the input data one digit before the input data,
When the logic level of a majority of the number of codes forming the parallel data changes, the sign of the input data is inverted, and a flag indicating that the sign of the input data is inverted is added and transmitted and received. It is a parallel data transmission method in which data is inverted by the flag.

According to the first means, the input data at a certain timing is compared with the transmission data corresponding to the input data one digit before the input data, and the logical level of the majority of the codes forming the parallel data is set. , The sign of the input data is inverted, so that the transmission data corresponding to the input data one digit before and the transmission data corresponding to the input data have the same logical level of the sign of the majority. That is, the number of codes that change between the transmission data corresponding to the input data one digit before and the transmission data corresponding to the input data is suppressed to less than half. Then, since the flag is added and transmitted, the original parallel data can be restored on the receiving side.

The input data and the transmission data corresponding to the input data which is preceded by one digit from the input data are compared, and when the logic level of the majority of the codes forming the parallel data changes, the code of the input data is changed. The inversion means that the allowable number of simultaneous changes is p bits when the number of bits of the parallel data is an odd number 2p + 1 and when the number of bits of the parallel data is an odd number 2p. That is,
If no action is taken, the number of bits forming the group is p. On the other hand, when the logic level of the majority of the number of codes forming the parallel data changes, the sign of the input data is inverted, and continuous 2p + 1 bits or 2p
The number of bits that change simultaneously between bit transmission data is p
The number of bits forming the group is 2 since
It becomes possible to increase to p + 1 bits or 2p bits. As a result, the restrictions on the pin arrangement of the large-scale integrated circuit and the pattern design on the wiring board on which the large-scale integrated circuit is mounted are alleviated.

This also applies to all of the following fourth means. The second means of the present invention is the number of changes from "1" to "0" and "0" between the input data at a certain timing and the transmission data corresponding to the input data one digit before the input data. If the difference in the number of changes from "1" to "1" is the majority of the number of codes forming the parallel data, the sign of the input data is inverted and a flag indicating that the sign of the input data is inverted Is a parallel data transmission method in which data is added and transmitted, and received data is inverted by the flag.

The transient current due to the change from "1" to "0" and the transient current due to the change from "0" to "1" are almost opposite to each other. Therefore, malfunction due to transient current is "1".
It can be considered to be caused by the difference between the number of changes from "0" to "0" and the number of changes from "0" to "1". According to the second means, the number of changes from "1" to "0" and "0" between the input data at a certain timing and the transmission data corresponding to the input data one digit before the input data. To “1”
When the difference in the number of changes to is a majority of the number of codes forming the parallel data, the sign of the input data is inverted,
The difference between the number of changes from “1” to “0” and the number of changes from “0” to “1” between the transmission data corresponding to the input data one digit before and the transmission data corresponding to the input data is It is suppressed to less than half the number of codes forming the parallel data.
Then, since the flag is added and transmitted, the original parallel data can be restored on the receiving side.

The third means of the present invention is that when the number of specific codes ("1" or "0") in the input data at a certain timing is a majority of the number of codes forming the parallel data, the input data is input. This is a parallel data transmission method in which the sign of data is inverted, a flag indicating that the sign of the input data is inverted is added and transmitted, and the received data is inverted by the flag.

According to the third means, when the number of specific codes in the input data at a certain timing is a majority of the number of codes forming the parallel data, the code of the input data is inverted, so that the transmission data is transmitted. The number of specific codes in is always less than half of the number of codes forming the parallel data. In addition, since the number of specific codes in the transmission data is always less than half of the number of codes forming the parallel data, the "between the transmission data corresponding to the input data one digit before and the transmission data corresponding to the input data". The difference between the number of changes from "1" to "0" and the number of changes from "0" to "1" is suppressed to less than half the number of codes forming parallel data. Then, since the flag is added and transmitted, the original parallel data can be restored on the receiving side.

In the fourth means of the present invention, the difference between the number of specific codes in the input data at a certain timing and the number of specific codes in the transmission data corresponding to the input data one digit before forms parallel data. When the number of codes is a majority, it is a parallel data transmission method in which the input data is inverted, a flag indicating that the input data is inverted is transmitted, and the received data is inverted by the flag.

According to the fourth means, the difference between the number of the specific code in the input data at a certain timing and the number of the specific code in the transmission data corresponding to the input data one digit before forms the parallel data. If it is a majority of the number, the input data is inverted, so that the number of the specific code in the transmission data corresponding to the input data at a certain timing and the specific code in the transmission data corresponding to the input data one digit before. The difference from the number is suppressed to less than half the number of codes forming the parallel data. Therefore, the number of changes from “1” to “0” and the number of changes from “0” to “1” between the transmission data corresponding to the input data one digit before and the transmission data corresponding to the input data are The difference is suppressed to less than half the number of codes forming the parallel data. Then, since the flag is added and transmitted, the original parallel data can be restored on the receiving side.

A fifth means of the present invention is, on the receiving side of the parallel data transmission system provided by the first means of the present invention,
This is a parallel data transmission method in which an alarm is generated when it is detected that the number of codes that simultaneously change between consecutive two digit parallel data is a majority of the number of codes forming the parallel data.

Since the transmission data is formed such that the number of codes that simultaneously change between consecutive two-digit parallel data is less than half of the number of codes forming the parallel data, the consecutive two-digit parallel data is formed. It is obvious that an error has occurred in the transmission path if the number of codes that simultaneously change between the two is a majority of the number of codes forming the parallel data.

A sixth means of the present invention is, on the receiving side of the parallel data transmission system provided by the second means of the present invention,
An alarm is generated when it is detected that the difference between the number of changes from "1" to "0" and the number of changes from "0" to "1" is a majority between consecutive 2 digit parallel data. It is a parallel data transmission method.

In the transmission data, the difference between the number of changes from "1" to "0" and the number of changes from "0" to "1" between continuous two-digit parallel data is the number of codes forming the parallel data. Since the conversion is performed so as to be less than half, the difference between the number of changes from "1" to "0" and the number of changes from "0" to "1" should be the majority of the number of codes forming the parallel data. For example, it is clear that the transmission line has received an error.

The seventh means of the present invention is, on the receiving side of the parallel data transmission system provided by the third means of the present invention,
This is a parallel data transmission system in which an alarm is generated when it is detected that the number of specific codes in the received data is a majority of the number of codes forming the parallel data.

Since the transmission data is converted so that the number of specific codes among the codes forming the parallel data is less than half, the number of the specific codes in the reception data is equal to the number of codes forming the parallel data. When the majority is detected, it is clear that the transmission line has received an error.

The eighth means of the present invention is, on the receiving side of the parallel data transmission system provided by the fourth means of the present invention,
This is a parallel data transmission system in which an alarm is generated when it is detected that the difference in the number of specific codes between consecutive two-digit parallel data is a majority of the number of codes forming the parallel data.

Since the transmission data has been converted such that the difference in the number of specific codes between consecutive two-digit parallel data is less than half the number of codes forming the parallel data,
When it is detected that the difference in the number of specific codes between consecutive two-digit parallel data is a majority of the number of codes forming the parallel data, it is obvious that an error has occurred in the transmission path.

[0027]

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, 11 is an inversion unit, 12 is a delay unit, 13 is a data change detection unit, and 14 is a simultaneous change number detection unit, which is provided in the large scale integrated circuit on the transmission side. Reference numeral 21 denotes an inverting unit, which is provided in the large-scale integrated circuit on the receiving side.

In the configuration of FIG. 1, the transmission side compares the transmission data delayed by one digit and the input data in the data change detecting section, and the code in which the number of bits detected by the data change detecting section forms parallel data. If the simultaneous change number detection unit detects that the number is a majority of the numbers, and the number of bits at which the data change detection unit detects a change is the majority of the number of codes forming the parallel data, the output of the simultaneous change detection unit Inverts the input data and transmits it, and when the number of bits in which the data change detection unit detects the change is less than half the number of codes forming the parallel data, the input data is inverted depending on the output of the simultaneous change detection unit. The output of the simultaneous change number detection unit is transmitted as a flag indicating the presence or absence of inversion. On the other hand, the receiving side inverts the received data as reproduction data when the flag indicates inversion, and sets the reception data as reproduction data when the flag does not indicate inversion.

FIG. 2 shows an example of data conversion on the transmitting side in the configuration of FIG. In the case of FIG. 2, since the parallel data is 6 bits, the data is inverted when 4 bits or more simultaneously change between consecutive 2 digits, and when inverted, "1" is added as a flag and when not inverted. To "0"
Is added as a flag. In this case, the original parallel data 6
Among the bits, the number of bits that change simultaneously with two consecutive digits is suppressed within 3 bits.

FIG. 3 shows a second embodiment of the present invention. In FIG. 3, 11 is an inversion unit, 12-1 and 12-.
Reference numeral 2 is a delay unit, 13 is a data change detection unit, and 15 is a change number difference detection unit, which is provided in the large-scale integrated circuit on the transmission side. or,
Reference numeral 21 denotes an inverting unit, which is provided in the large-scale integrated circuit on the receiving side.

In the configuration of FIG. 3, the transmission side compares the transmission data delayed by one digit and the input data in the data change detection section, and the change direction detected by the data change detection section in the change number difference detection section is " Is it from "1" to "0"?
"1" to "0" after judging from "0" to "1"
The difference between the number of changes to "0" and the number of changes from "0" to "1",
When the difference in the number of changes is the majority of the number of codes forming the parallel data, the input data is inverted and transmitted by the output of the number of change detecting section, and the difference in the number of changes forms the number of codes forming the parallel data. If it is a majority, the input data is transmitted without being inverted depending on the output of the change number detecting section, and the output of the change number difference detecting section is transmitted as a flag indicating the presence or absence of inversion. On the other hand, the receiving side inverts the received data as reproduction data when the flag indicates inversion, and sets the reception data as reproduction data when the flag does not indicate inversion.

FIG. 4 shows an example of data conversion on the transmitting side in the configuration of FIG. In the case of FIG. 4, since the parallel data has 6 bits, the difference in the number of changes is 4 between two consecutive digits.
Inverts the data when it is more than a bit, adds "1" as a flag when inverted, and "0" when not inverted
Is added as a flag. In this case, the original parallel data 6
Among the bits, the difference in the number of changes between two consecutive digits is suppressed within 3 bits. Also, for example, between (2) and (3), the number of simultaneous changes is 6 bits, but "1"
Since the number of changes from "0" to "0" and from "0" to "1" are equal,
(3) is transmitted without being inverted. Since the inversion is performed when the difference in the number of changes is a majority, the number of cases of inversion is smaller than that in the case of FIG. Therefore, it is advantageous in a large scale integrated circuit of the type that consumes power when the sign is inverted, such as CMOS.

FIG. 5 shows a third embodiment of the present invention. In FIG. 5, 11 is an inversion unit, and 16 is a code number detection unit, which is provided in the large-scale integrated circuit on the transmission side. Reference numeral 21 denotes an inverting unit, which is provided in the large-scale integrated circuit on the receiving side.

In the configuration of FIG. 5, when the number of specific codes in the input data is the majority of the number of codes forming the parallel data, the transmitting side inverts the input data by the output of the code number detecting section and transmits it. However, when the number of specific codes in the input data is less than half of the number of codes forming the parallel data, the input data is transmitted without being inverted depending on the output of the code number detecting unit, and the number of codes is The output of the detection unit is added as a flag indicating the presence or absence of inversion and transmitted. On the other hand, the receiving side inverts the received data as reproduction data when the flag indicates inversion, and sets the reception data as reproduction data when the flag does not indicate inversion.

FIG. 6 is an example of data conversion on the transmitting side in the configuration of FIG. In the case of FIG. 6, since the number of codes forming the parallel data is 6 bits, the input data is inverted and transmitted when the number of specific codes in the input data is 4 bits or more. Here, it is shown that the specific code is "1" and the input data is inverted when the number of "1" is 4 bits or more. In this case, the number of “1” is 3 bits or less in the part other than the flag of the transmission data.

FIG. 7 shows a fourth embodiment of the present invention. In FIG. 7, 11 is an inversion unit, 12 is a delay unit, and 17
Is a code number difference detection unit, which is provided in the large-scale integrated circuit on the transmission side. Reference numeral 21 denotes an inverting unit, which is provided in the large-scale integrated circuit on the receiving side.

In the configuration of FIG. 7, when the difference in the specific code number between two consecutive digits of the input data is the majority of the code numbers forming the parallel data, the transmitting side inputs the output by the code number difference detecting section. When the data is inverted and transmitted, and the difference in the specific code number between two consecutive digits of the input data is less than half of the code numbers forming the parallel data, the input data may be output depending on the output of the code number difference detection unit. The data is transmitted without being inverted, and the output of the code number difference detection unit is added as a flag indicating the presence or absence of inversion and transmitted. On the other hand, the receiving side inverts the received data as reproduction data when the flag indicates inversion, and sets the reception data as reproduction data when the flag does not indicate inversion.

FIG. 8 shows an example of data conversion on the transmitting side in the configuration of FIG. In the case of FIG. 6, since the number of codes forming the parallel data is 6 bits, two consecutive input data
When the difference in the number of specific codes of digits is 4 bits or more, the input data is inverted and transmitted. Here, it is illustrated that the specific code is "1" and the input data is inverted when the difference in the number of "1" is 4 bits or more. In this case, in the part other than the flag of the transmission data, the difference in the number of "1" s in two consecutive digits is within 3 bits and the number of changes from "1" to "0" in two consecutive digits. And the number of changes from "0" to "1" is also within 3 bits.

FIG. 9 shows a fifth embodiment of the present invention. In FIG. 9, 21 is an inversion unit, 22 is a delay unit, and 23.
Is a data change detector, and 24 is a simultaneous change number detector.

In the configuration of FIG. 9, when the flag indicates inversion, the sign of the received data is inverted to obtain the reproduction data,
When the flag does not indicate inversion, the received data is the reproduced data. By the way, the received data is formed by two consecutive digits so that the number of simultaneous changes of the code is less than half of the number of codes forming the parallel data. Utilizing this property, the data change detecting unit compares the codes forming continuous 2-digit parallel data bit by bit, and outputs a specific code to the bit whose code has changed, and the simultaneous change number detecting unit outputs the specific code. An alarm is generated when the number of specific codes is a majority of the number of codes forming parallel data.

FIG. 10 shows a sixth embodiment of the present invention. In FIG. 10, 21 is an inversion unit, 22 is a delay unit, 2
Reference numeral 3 is a data change detection unit, and 25 is a change number difference detection unit.

In the configuration of FIG. 10, when the flag indicates inversion, the sign of the received data is inverted to be reproduction data, and when the flag does not indicate inversion, the reception data is reproduction data. By the way, the received data consists of two consecutive digits, the number of changes from "1" to "0" and "0" to "1".
Is formed so that the difference in the number of changes to the number of the codes is less than half the number of codes forming the parallel data. Utilizing this property,
The data change detecting unit compares and outputs the codes forming the continuous 2-digit parallel data bit by bit, and the change number difference detecting unit outputs the bit by bit from the data change detecting unit from "1" to "0". An alarm is generated when the difference between the number changing to "1" and the number changing from "0" to "1" is a majority of the number of codes forming the parallel data.

FIG. 11 shows a seventh embodiment of the present invention. In FIG. 11, 21 is an inversion unit and 26 is a code number detection unit. In the configuration of FIG. 11, when the flag indicates inversion, the sign of the received data is inverted to be reproduction data,
When the flag does not indicate inversion, the received data is the reproduced data. By the way, the received data is formed such that the number of specific codes in each digit is less than half the number of codes forming the parallel data. Utilizing this property, an alarm is generated when the code number detecting unit detects that the majority of the codes forming the parallel data are specific codes.

FIG. 12 shows the eighth embodiment of the present invention. In FIG. 12, 21 is an inversion unit, 22 is a delay unit, and 2
Reference numeral 7 is a code number difference detection unit.

In the configuration of FIG. 12, when the flag indicates inversion, the sign of the received data is inverted to be reproduction data, and when the flag does not indicate inversion, the reception data is reproduction data. By the way, the received data is formed such that the difference between the specific code numbers of continuous two digits is less than half of the code numbers forming the parallel data. Utilizing this property, an alarm is generated when the difference between the specific code numbers of two consecutive digits is detected by the code number difference detection unit to be a majority of the code numbers forming the parallel data.

The description of the basic embodiments of the present invention is completed above, and the configuration of blocks in each embodiment will be described below. First, the inverting section is provided with an exclusive OR circuit equal to the number of codes forming the parallel data, and each bit of the input data is input to one input terminal of each exclusive OR circuit. The output signal of the simultaneous change number detection unit may be supplied to the other input terminal.

The delay unit can be composed of flip-flops or delay lines equal in number of codes forming parallel data, but flip-flops which can be delayed by a clock synchronized with input data are advantageous. .

The data change detection unit is provided with an exclusive OR circuit equal to the number of codes forming the parallel data, and each bit of the input data is supplied to one exclusive input terminal of each exclusive OR circuit. Each bit of the output of the delay unit may be supplied to the other input terminal of the OR circuit in the same order as the input data.

FIG. 13 shows a circuit (No. 1) of the simultaneous change number detecting section in FIG. 1, showing a circuit for detecting a simultaneous change of 4 bits or more assuming that parallel data is 6 bits.

In FIG. 13, 141-1 to 141-
Reference numeral 9 is a 2: 1 selector, 142-1 to 142-7 are 2-input AND circuits, and 143 is a 4-input AND circuit.
Here, the "1" input terminals (the input terminals selected when the selection signal is "1") of the 2: 1 selectors 141-1 to 141-5 are referred to as the data change detection units. The 1st to 5th bits of the output are supplied,
The "0" input terminals of the 2: 1 selectors 141-1 to 141-5 (the input terminals that are selected when the selection signal is "0" are referred to as follows) have two outputs of the data change detection unit. Bits 6 to 6 are supplied. or,
The 1st bit of the output of the data change detection section is supplied as the selection signal of the 2: 1 selector 141-1, and the 2nd bit of the output of the data change detection section and 2: 1 as the selection signal of the 2: 1 selector 141-2. The logical product of the selection signals of the selector 141-1 is supplied, and the logical product of the third bit of the output of the data change detector and the selection signal of the 2: 1 selector 141-2 is supplied as the selection signal of the 2: 1 selector 141-3. Similarly, the logical product of the 5th bit of the output of the data change detector and the selection signal of the 2: 1 selector 141-4 is supplied as the selection signal of the 2: 1 selector 141-5. or,
The outputs of the 2: 1 selectors 141-1 to 141-4 are supplied to the "1" input terminals of the 2: 1 selectors 141-6 to 141-9, and the 2: 1 selector 14 is supplied to the "0" input terminals.
The outputs 1-2 to 141-5 are supplied. And
The output of the 2: 1 selector 141-1 is supplied as the selection signal of the 2: 1 selector 141-6, and the 2: 1 selector 14
The logical product of the output of the 2: 1 selector 141-2 and the selection signal of the 2: 1 selector 141-6 is supplied as the selection signal of 1-7, and thereafter, similarly as the selection signal of the 2: 1 selector 141-9. 2: 1 output of selector 141-4 and 2:
The logical product of the selection signals of the 1-selector 141-8 is supplied. Further, the outputs of the 2: 1 selectors 141-6 to 141-9 are supplied to the logical product circuit 143, and the output of the logical product circuit becomes a detection signal of the number of simultaneous changes.

Here, the input data is "100111".
The operation of the configuration shown in FIG. First, since the selection signal of the 2: 1 selector 141-1 is "1", the 2: 1 selector 141-1 selects and outputs the "1" input terminal. Therefore, the 2: 1 selector 141-1
Output is "1". Next, the 2: 1 selector 141-
The selection signal No. 2 is a logical product of the second bit "0" of the output of the data change detection unit and the selection signal "1" of the 2: 1 selector 141-1. The selector 141-2 selects and outputs the third bit "0" of the output of the data change detection unit. Similarly, the 2: 1 selector 141-3 selects the fourth bit "1" of the output of the data change detection unit, and the 2: 1 selector 141-4 selects the fifth bit "1" of the output of the data change detection unit. Select "2: 1
The selector 141-5 selects and outputs the 6th bit "1" of the output of the data change detection unit. Similarly to this, 2:
The 1 selector 141-6 selects the output of the 2: 1 selector 141-1, the 2: 1 selector 141-7 selects the output of the 2: 1 selector 141-3, and the 2: 1 selector 141-.
8 selects the output of the 2: 1 selector 141-4 and selects 2: 1.
The selector 141-9 selects and outputs the output of the 2: 1 selector 141-5. Therefore, "1" is supplied to all the input terminals of the logical product circuit 143, and the logical product circuit outputs "1".

That is, according to the configuration of FIG. 13, “1111” obtained by removing “0” from the output “100111” of the data change detection unit is supplied to the AND circuit 143. if,
If the output of the data change detection unit is “100011”, 2
The two “0” s of the bit and the third bit are removed and “101”
Since "1" is output, the output of the AND circuit 143 becomes "0". That is, the configuration of FIG. 13 has a function of detecting that the majority of 6-bit inputs is "1". , To detect that the majority of 6-bit inputs is "0", select signal terminals of all 2: 1 selectors are inverting terminals, and all 2-input AND circuits are 2-input logical sum circuits. All the input terminals of the 4-input AND circuit may be inverting terminals, or the 4-input AND circuit may be replaced with a logical OR circuit of 4-input inverting output, so that the configuration of FIG. It is possible to detect that the number of simultaneous changes is a majority of the number of codes forming the parallel data.
Moreover, FIG. 13 is a circuit for detecting that "1" is a majority, and its modification is a circuit for detecting that "0" is a majority, so that the logical sum can be expressed by negation and logical product. Considering the basic theorem of Boolean algebra,
Both are equivalent.

FIG. 14 shows the structure (No. 2) of the simultaneous change number detecting section in FIG. In FIG. 14, 144 is a read-only memory (denoted as ROM in the figure),
Reference numeral 145 is a comparison circuit.

In the configuration shown in FIG. 14, the read-only memory uses all combinations of codes that can be output by the data change detection unit as addresses, and sets the number of specific codes in all combinations of codes that can be output by the data change detection unit as data. I remember as. The output of the data change detector supplies it as an address. Therefore, it is the number of specific codes in the output of the data change detection unit that is read from the read-only memory. If the number of the specific code is supplied to one input terminal of the comparison circuit and the reference number which is the majority of the number of codes forming the parallel data is input to the other input terminal of the comparison circuit and compared, It can be detected that the number of specific codes in the output of the data change detection unit is a majority of the number of codes forming the parallel data.

In the read-only memory, "1" is set when the specific code number is the majority of the code numbers forming the parallel data in the combination of the codes output by the data change detecting section.
If "0" is stored when the specific code number is the majority of the code numbers forming the parallel data in the combination of codes output by the data change detection unit, the comparison circuit can be omitted.

By the way, since the configurations of FIGS. 13 and 14 are essentially a majority detection circuit, they can also be used as the code number detection section of FIGS. 5 and 11. And, of course, it can also be used as the simultaneous change number detection unit in FIG.

FIG. 15 shows the configuration of the change number difference detection unit in FIG. In FIG. 15, 151-1 to 151-
Reference numeral 3 is a rising differentiating circuit, 152-1 to 152-3 are falling differentiating circuits, and 153-1 and 153-2 are read-only memories (denoted as ROM in the figure), 1
Reference numeral 54 is a subtraction circuit, and 155 is a comparison circuit.

In the configuration of FIG. 15, each bit of the output of the data change detecting section is supplied to a pair of rising differential circuit and falling differential circuit. Then, all the outputs of the rising differentiating circuit are supplied to the address terminals of the read-only memory 153-1, and all the outputs of the falling differentiating circuit are supplied to the address terminals of the read-only memory 153-2. Each read-only memory stores the specific code number in the output pattern of the differentiating circuit with all the output patterns of the differentiating circuit as addresses. Therefore, the output of the subtraction circuit is the number of codes changed from "0" to "1" in the detection signal of the data change detection unit and the number of codes changed from "1" to "0" in the detection signal of the data change detection unit. It makes a difference. This is the difference between the code number changed from "0" to "1" and the code number changed from "1" to "0" in the continuous 2-digit input data in the configuration of FIG.

Of course, the configuration of FIG. 15 can also be used for the change number difference detection unit in FIG. FIG. 16 shows the configuration (No. 1) of the code number difference detection unit in FIG. In FIG. 16, 171-1 and 171-2 are read-only memories (denoted as ROM in the figure), 172 is a subtraction circuit, and 173 is a comparison circuit.

In the configuration of FIG. 16, the read-only memory uses the combination of codes of input data as an address and stores the number of specific codes in the combination of codes of input data. Then, input data is input to the address terminal of the read-only memory 171-1 and read-only memory 171-2.
Since the output data of the delay unit is supplied to the address terminal of, the number of specific codes in the input data is read from the read-only memory 171-1 and the output data of the delay unit is read from the read-only memory 171-2. The number of the specific code in is read. If the difference between the numbers read out from the two read-only memories is calculated and compared with a reference number that is the majority of the numbers of codes forming the parallel data, the difference between the numbers of consecutive two-digit specific codes is found. It can be determined whether or not it is a majority of the number of codes forming the parallel data.

FIG. 17 shows the configuration (part 2) of the code number difference detection unit in FIG. In FIG. 17, 174-1 and 174-2 are addition circuits, 172 is a subtraction circuit, and 173 is a comparison circuit.

In the configuration of FIG. 17, input data and output data of the delay unit are supplied to each adder circuit. Each adder circuit sets “0” of input data to 0,
Since "1" is added as 1, the number of "1" in the input data is output from each adder circuit. Therefore, if the difference between the numbers output by the two adder circuits is calculated and compared with a reference number that is the majority of the numbers of codes forming the parallel data, the difference between the numbers of consecutive two-digit specific codes is calculated. It can be determined whether or not it is a majority of the number of codes forming

Of course, the configuration of FIGS. 16 and 17 is similar to that of FIG.
It is also possible to use it as a change number difference detector in. This is the end of the description of the configuration of each block in the first to eighth embodiments of the present invention, and hereinafter, the first to eighth embodiments of the present invention will be described. , The main ones will be described as modified examples and those with expanded functions.

FIG. 18 is a modification (1) of the configuration of FIG. In FIG. 18, 11 is an inversion unit, 12-1 and 1
2-2 is a delay unit, 13 is a data change detection unit, and 14 is a simultaneous change number detection unit, which is provided on the transmission side. Reference numeral 21 denotes an inverting unit, which is provided on the receiving side.

In the configuration of FIG. 18, since the data inverted on the transmitting side is output through the delay section, the flag is also delayed to match the phase. Therefore, the output of the transmission unit is delayed by one digit from the configuration of FIG. 1 and is functionally the same as that of FIG.

The use of such a delay section can be similarly applied to other configurations for detecting a change between two consecutive digits. FIG. 19 is a modification (2) of the configuration of FIG.

In FIG. 19, 11a is an inverting section, 12 is a delay section, 13 is a data change detecting section, and 14 is a simultaneous change number detecting section, which are provided on the transmitting side. Reference numeral 21 denotes an inverting unit, which is provided on the receiving side.

The configuration of FIG. 19 differs from that of FIG. 1 in that
When "0" is input to the inversion unit in addition to the input data and the number of simultaneous changes in the code of two consecutive digits of the input data is the majority of the numbers of codes forming the parallel data, the "0" is also included. Is inverted and output, and the inversion of "0" is used as a flag.

The method of generating such a flag can be similarly applied to other configurations.
FIG. 20 is an extension (part 1) of the configuration of FIG.

In FIG. 20, 11 is an inversion unit, 12-1
And 12-2 are delay units, 13a is a data change detection unit, 1
Reference numeral 4a is a simultaneous change number detection unit, which is provided on the transmission side. 21
Is a reversing unit and is provided on the receiving side.

The configuration of FIG. 20 differs from that of FIG. 1 in that
Comparison of the data in which "0" is added to the input data and the data in which a flag is added to the transmission data, and the majority of the number obtained by adding 1 to the number of codes forming parallel data between the two has changed at the same time. If the input data is detected, the input data is inverted and the number of codes forming parallel data between the two is 1
The point is that a signal that detects that a majority of the numbers obtained by adding is simultaneously changed is transmitted as a flag.

FIG. 21 is an example of data conversion in the transmitting section having the configuration of FIG. In FIG. 21, the data is 6 bits, and “0” below the solid line “before conversion” is an added “0”. For the sake of convenience, if the sign changes at the same time in a majority of 7 bits, that is, in 4 bits or more, the sign is inverted and transmitted. Therefore, since the code is inverted when the majority of all the codes including the flag change at the same time, the number of the codes simultaneously changing in the transmission data can be less than half of all the codes including the flag. For example, between (3) and (4) of "after conversion" in FIG. 2, 4 bits are changed at the same time when the flag is included, but (3) and (4) of "after conversion" in FIG. In the period, even if the flag is included, the simultaneous change of 3 bits is stopped. Therefore, it can be said that the configuration of FIG. 20 is a more complete version of the configuration of FIG.

FIG. 22 is an extension (part 2) of the configuration of FIG. In FIG. 22, 12 is a delay unit, and 18 is a read-only memory (denoted as ROM in the figure), which is provided on the transmission side. 22 is a read-only memory (R in the figure
It is labeled as OM. ) Is provided on the receiving side.

In the configuration of FIG. 22, all bits of the input data and the transmission data delayed by one digit in the delay section are used as addresses in the read-only memory 18 and the input data and the transmission data delayed by one digit in the delay section are simultaneously used. If the number of changing bits is the majority of the number of codes forming parallel data, the input data is inverted to "1".
If the number of bits that change simultaneously between the input data and the data delayed by one digit in the delay unit is less than half the number of codes forming the parallel data, the input data and “0” are stored. In other words, if the number of bits that simultaneously change between the input data and the transmission data delayed by one digit in the delay unit from the read-only memory 18 becomes the majority of the number of codes forming the parallel data, the input data is inverted. The read data and "1" are read, and when the number of bits that change simultaneously between the input data and the data delayed by one digit in the delay unit is less than half the number of codes forming the parallel data, 0 "is read and transmitted. On the receiving side, the stored data may be read using the received data and the flag as an address. In this sense, the configuration of FIG. 22 is the same as the configuration of FIG.

However, the structure of FIG. 22 is characterized in that not only the sign inversion but also the degree of freedom of data conversion can be increased. That is, all bits of the transmission data delayed by one digit in the input data and the delay unit are used as addresses, and the number of bits that change simultaneously between the input data and the transmission data delayed by one digit in the delay unit is the number of codes forming the parallel data. In the case of a majority, the input data is converted into data such that the number of simultaneous changes with the transmission data delayed by one digit in the delay unit is less than half the number of codes forming the parallel data and "1" is stored. If the number of bits that change simultaneously between the input data and the transmission data delayed by one digit in the delay unit is less than half the number of codes forming the parallel data, the input data and "0" are stored. . And
It is easy to understand that such a conversion is possible.
Now, the reason will be described assuming that the number of codes forming the parallel data is an even number 2n (n is a positive integer). The fact that the number of bits that change simultaneously between the input data and the transmission data delayed by one digit in the delay unit is the majority of the number of codes forming the parallel data means that (n + 1) bits or more of 2n bits change at the same time. Is. The number in the case of such a change is the number obtained by adding all the numbers in the case of selecting (n + 1) bits or more in 2n bits. On the other hand, the number of converted data candidates is n out of 2n bits.
It is the sum of the numbers when selecting less than or equal to bits. By the way, the theory of combination is that the sum of the numbers when selecting (n + 1) bits or more in 2n bits is equal to the sum of the numbers when selecting (n-1) bits or less from 2n bits. I am teaching. Therefore, in this case, since the number of combinations in the data after the data conversion is larger than the number of combinations in the data before the data conversion, bits that change simultaneously between the input data and the transmission data delayed by one digit in the delay unit. It is possible to transform the input data so that the number is less than half the number of codes forming the parallel data. If the same thing is verified for the case where the number of codes forming the parallel data is odd, the number of bits that change at the same time between the input data and the transmission data delayed by one digit in the delay unit forms the parallel data even when the number of codes is odd. It is understood that it is possible to convert the input data so that the number of codes becomes less than half. That is, the above data conversion is generally possible. That is, it can be said that the configuration of FIG. 22 is an extension of the function of the configuration of FIG.

FIG. 23 shows an example of data conversion on the transmitting side of FIG. For example, the data “010101” of (3) in “before conversion” is “101000” in “after conversion”.
And the flag "1" is added, which is "101010" in (2) of "after conversion" and "0" before conversion.
This is the result of reading "101000" and "1" stored at the address by combining 10101 "as the address.

In the configuration of FIG. 22, the difference between the number of changes in stored contents from "1" to "0" and the number of changes from "0" to "1" is half the number of codes forming parallel data. If the converted data and flags are used as described below, the configuration of FIG. 3 can be expanded, and the difference between the specific code numbers of consecutive two digits of the stored content is less than half of the code numbers forming the parallel data. If the data and the flag are converted into, the configuration of FIG. 7 can be expanded.

FIG. 24 is an extension of the configuration of FIG. FIG.
In FIG. 4, 18 is a read-only memory provided on the transmitting side, and 28 is a read-only memory provided on the receiving side.

In the configuration shown in FIG. 24, when the number of specific codes in the input data is the majority of the number of codes forming the parallel data, the input data is inverted in the read-only memory 18 with the input data as an address. Data and "1"
If the number of specific codes in the input data is less than half of the number of codes forming the parallel data, the input data and “0” are stored, the same function as the configuration of FIG. 5 is stored. Can be realized. In this sense, the configuration of FIG. 24 is the same as the configuration of FIG.

However, the configuration of FIG. 24 is characterized in that not only the sign inversion but also the degree of freedom of data conversion can be increased. That is, when the number of specific codes in the input data is a majority of the number of codes forming the parallel data, a code and a flag "that the number of specific codes is less than half of the number of codes forming the parallel data" If 1 ”is stored and the number of specific codes in the input data is less than half of the number of codes forming the parallel data, the input data and the flag = 0” are stored, the data conversion is performed. That the data conversion is possible can be proved in the same manner as the description in the description of Fig. 22. That is, the configuration of Fig. 24 is an extension of the function of the configuration of Fig. 5. You can say that.

FIG. 25 is an extension of the configuration of FIG. FIG.
In FIG. 5, 22 is a delay unit, 23 is a data change detection unit,
Reference numeral 24 is a simultaneous change number detection unit, and 28 is a read-only memory.

The fact that FIG. 25 is an extension of the configuration of FIG.
Since it has been clarified in the explanation already given, duplicate explanation will not be given. Note that it has already been described that the configuration of FIG. 25 can be expanded from the configurations of FIGS. 10 and 12 by changing the stored contents of the read-only memory.

FIG. 26 is an extension of the configuration of FIG. In FIG. 26, reference numeral 26 is a code number detection unit, and 28 is a read-only memory. The fact that the configuration of FIG. 26 is an extension of the configuration of FIG. 11 has been clarified in the description already given, and therefore duplicated description will not be given.

With the above, the description of the modifications and extensions of the basic embodiment of the present invention is completed, and the basic embodiments of the present invention which have already been described are not completely independent, and are used in combination with each other. Explain what you can do.

FIG. 27 shows a combination (part 1) of the configuration of FIG. 1 and the configuration of FIG. 22, in which the configuration of FIG. 22 is used for the transmitting side and the configuration of FIG. 1 is used for the receiving side. Shows. In the configuration of FIG. 22, when the number of simultaneous changes between the input data and the transmission data delayed by one digit in the read-only memory on the transmission side is the majority of the codes forming the parallel data, the inversion of the input data and the flag are performed. Since the reproduced data can be obtained by inverting the received data by the flag on the receiving side, the configuration shown in FIG. 27 can be applied.

FIG. 28 shows a combination (part 2) of the configuration of FIG. 1 and the configuration of FIG. 22, in which the configuration of FIG. 1 is used for the transmitting side and the configuration of FIG. 22 is used for the receiving side. . In the configuration of FIG. 22, in the read-only memory on the receiving side, the input data and the flag are used as addresses, the inverted data of the input data is stored when the flag is “1”, and the read data is stored when the flag is “0”. If input data is stored,
Can be configured.

FIG. 29 shows a combination of the configurations of FIGS. 3 and 22, in which the configuration of FIG. 3 is applied to the transmitting side and the configuration of FIG. 22 is applied to the receiving side. The reason why FIG. 29 is effective is
Since it can be easily inferred from the description of FIG. 28, further description is omitted here. The configuration in which the transmitting side of FIG. 22 and the receiving side of FIG. 3 are combined has the same shape as that of FIG.

FIG. 30 shows a combination (part 1) of the configuration of FIG. 5 and the configuration of FIG. 24, which is a combination of the transmitting side of FIG. 24 and the receiving side of FIG. 31 is a combination (part 2) of the configuration of FIG. 5 and the configuration of FIG. 24.
It is a combination of four receiving sides.

The reason why FIGS. 30 and 31 are effective is also shown in FIG.
Since it can be more easily inferred from the explanation above, further explanation is omitted here.

[0090]

As described above in detail, according to the present invention, a parallel data transmission method that suppresses the number of changes in codes forming parallel data, and the number of specific codes in the codes forming parallel data are suppressed. A parallel data transmission system can be realized.

As a result, in the parallel data transmission system in which the upper limit is set for the number of changes in the codes forming the parallel data and the number of the specific codes in the codes forming the parallel data, the number of codes forming the parallel data is It is possible to make the number of changes and the number of specific codes approximately twice the upper limit. This greatly improves the degree of freedom in designing a large-scale integrated circuit and a printed board on which the large-scale integrated circuit is mounted.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 is an example of data conversion on the transmission side in FIG.

FIG. 3 is a second embodiment of the present invention.

FIG. 4 is an example of data conversion on the transmission side in FIG.

FIG. 5 is a third embodiment of the present invention.

FIG. 6 is an example of data conversion on the transmission side in FIG.

FIG. 7 is a fourth embodiment of the present invention.

8 is an example of data conversion on the transmission side in FIG. 7.

FIG. 9 is a fifth embodiment of the present invention.

FIG. 10 shows a sixth embodiment of the present invention.

FIG. 11 is a seventh embodiment of the present invention.

FIG. 12 is an eighth embodiment of the present invention.

FIG. 13 shows a configuration of a simultaneous change number detection unit (No. 1).

FIG. 14 shows a configuration of a simultaneous change number detection unit (No. 2).

FIG. 15 is a configuration of a change number difference detection unit.

FIG. 16 shows a configuration of a code number difference detection unit (No. 1).

FIG. 17 shows a configuration of a code number difference detection unit (No. 2).

FIG. 18 is a modification (1) of the configuration of FIG. 1.

FIG. 19 is a modification of the configuration of FIG. 1 (No. 2).

FIG. 20 is an extension (1) of the configuration of FIG.

FIG. 21 shows an example of data conversion on the transmission side in FIG.

FIG. 22 is an extension of the configuration of FIG. 1 (No. 2).

FIG. 23 is an example of data conversion on the transmission side in FIG. 22.

FIG. 24 is an extension of the configuration of FIG.

FIG. 25 is an extension of the configuration of FIG.

FIG. 26 is an extension of the configuration of FIG.

FIG. 27 is a combination of the configuration of FIG. 1 and the configuration of FIG. 22 (No. 1).

FIG. 28 is a combination of the configuration of FIG. 1 and the configuration of FIG. 22 (Part 2).

FIG. 29 is a combination of the configuration of FIG. 3 and the configuration of FIG. 22.

FIG. 30 is a combination of the configuration of FIG. 5 and the configuration of FIG. 24 (No. 1).

FIG. 31 is a combination of the configuration of FIG. 5 and the configuration of FIG. 24 (Part 2).

[Explanation of symbols]

 11 Inversion Unit 12 Delay Unit 13 Data Change Detection Unit 14 Simultaneous Change Number Detection Unit 21 Inversion Unit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Takashi Kuwahara, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, within Fujitsu Limited

Claims (9)

[Claims] 1. On the transmitting side, when the number of simultaneously changing codes of the input data and the code of the transmission data corresponding to the input data preceding the input data by one digit is a majority of the number of codes forming the parallel data, The input data is converted so that the number of simultaneous changes between the input data and the code of the data that is one digit ahead of the input data is equal to or less than half the number of codes forming the parallel data, and the conversion is performed. The number of codes that forms parallel data when the code of a specific logical level is added as a flag to be transmitted, and the number of simultaneously changing the code of the input data and the code of the transmission data corresponding to the input data 1 digit ahead of the input data Is less than half, the input data is used as transmission data without converting the input data, and the specific logical level is set as a flag indicating the non-conversion. A code with a logical level different from that of the above is added as a flag and transmitted, and if the received flag is a code with the specific logical level, the reception data is the reverse of the conversion on the transmission side. A parallel data transmission method in which the received data is converted into reproduction data, and when the received flag is a code having a logic level different from the code of the specific logic level, the reception data is reproduction data. 2. The parallel data transmission system according to claim 1, wherein the number of simultaneously changing codes of the received data and the received data which is one digit ahead of the received data is the number of codes forming the parallel data on the receiving side. A parallel data transmission method characterized by generating an alarm when the number is majority. 3. On the transmitting side, the code of the input data and the code of the transmission data corresponding to the input data preceding by 1 digit from the input data are "1" at the same time.
If the difference between the number changing from "0" to "0" and the number changing from "0" to "1" is a majority of the number of codes forming the parallel data, the input data is preceded by one digit. Convert the data so that the difference is less than half of the number of codes forming the parallel data to be transmission data, and add a code of a specific logic level as a flag indicating the conversion. The code of transmission data that is transmitted and corresponds to the input data and the input data that precedes the input data by one digit is "1" at the same time.
If the difference between the number changing from "0" to "0" and the number changing from "0" to "1" is less than half of the number of codes forming the parallel data, the input data is converted into the transmission data without being converted. At the same time, a code of a logic level different from the specific logic level is added as a flag indicating the non-conversion and transmitted, and if the received flag is the code of the specific logic level, reception is performed. If the received flag is a code of a logic level different from the code of the specific logic level, the received data is made to be the reproduction data by performing the reverse conversion of the data on the transmission side to the reproduction data. Parallel data transmission method characterized by. 4. The parallel data transmission method according to claim 3, wherein at the receiving side, the received data and the number of codes of the received data that precedes the received data by one digit change from “1” to “0” at the same time. A parallel data transmission method, wherein an alarm is generated when the difference from the number changing from "0" to "1" is a majority of the number of codes forming parallel data. 5. On the transmitting side, when the number of specific codes in the input data is a majority of the number of codes forming the parallel data, the number of specific codes of the input data is set to the number of codes forming the parallel data. A code that is converted so that the number becomes half or less to be transmission data, and that a code having a specific logic level is added as a flag indicating the conversion and transmitted, and the number of specific codes in the input data forms parallel data. When it is less than half of the number, the input data is used as the transmission data without being converted, and a code of a logical level different from the code of a specific logical level is added as a flag indicating the non-conversion and transmitted. On the receiving side, when the received flag is the code of the specific logical level, the received data is converted into the reproduced data by performing the reverse conversion to the conversion on the transmitting side, and the received flag is the specific logical level. When the sign of the bell is a sign of a different logic level, parallel data transmission system, characterized in that the received data and reproduced data. 6. The parallel data transmission system according to claim 5, wherein an alarm is generated on the receiving side when the number of specific codes in the input data is a majority of the number of codes forming the parallel data. And parallel data transmission method. 7. On the transmitting side, the number of specific codes in input data and 1 from the input data
When the difference in the number of specific codes in the transmission data corresponding to the input data digit-preceding is a majority of the number of codes forming the parallel data, the input data is compared with the data one digit preceding the input data. Is converted so that the difference in the number of specific codes between them is less than half of the number of codes forming parallel data, and the data is transmitted, and a code of a specific logical level is added as a flag indicating the conversion and transmitted. , The number of specific codes in the input data and 1 from the input data
If the difference in the number of specific codes in the transmission data corresponding to the digit preceding input data is less than half of the number of codes forming the parallel data, the input data is converted into the transmission data, and As a flag indicating the non-conversion, a code of a logic level different from the code of the specific logic level is added and transmitted, and when the received flag is the code of the specific logic level, the received data Is converted into reproduction data by performing conversion reverse to the conversion on the transmission side, and if the received flag is a code of a logic level different from the code of the specific logic level, the reception data is set to reproduction data. Characteristic parallel data transmission method. 8. The parallel data transmission system according to claim 7, wherein the number of specific codes in the received data and 1 from the received data at the receiving side.
Digit A parallel data transmission method, wherein an alarm is generated when a difference in the number of specific codes in preceding received data is a majority of the number of codes forming the parallel data. 9. A 2: 1 selector, the number of which is one less than the code number n forming the parallel data, and a two-input AND circuit, which is two less than the code number forming the parallel data, are provided.
Is an integer less than or equal to (n-1) and supplies the i-th bit and the (i + 1) -th bit of the parallel data to the input terminal of the 2: 1 selector and supplies it to the selection signal terminal of the first 2: 1 selector. Is the first bit of the parallel data and the j-th (j is 2 or more (n-
1) The selection signal terminal of the 2: 1 selector (integer less than or equal to) is supplied with the logical product of the j-th bit of the parallel signal and the selection signal supplied to the (j-1) 2: 1 selector. n-
The output of the 2: 1 selector in 1) is used as parallel data to the second stage, and in the second and subsequent stages, a 2: 1 selector that is one less than the immediately preceding stage and a two-input AND circuit that is one less than the immediately preceding stage are used. And the number of codes of the parallel data is reduced by 1 in each stage by the same configuration as described above, and the number of inputs of the output of the 2: 1 selector is reduced in the stage where the reduced number of codes is equal to the minimum value of the majority of n. Whether the number of specific codes of the original parallel data is a majority of n by supplying the logical product circuit equal to the minimum value of the majority of n and the output of the AND circuit whose input number is equal to the minimum value of the majority of n. A majority determination circuit characterized by determining whether or not.