JPH09200752A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor with which high-definition image information can be efficiently transmitted. SOLUTION: A switcher 100 is a switcher for selectively outputting the output of a maximum value detector 108 and the output of a minimum value detector 109 corresponding to the information of a motion detector 105. All the pixel data in respective picture element blocks and the maximum and minimum values of these data are inputted to a divided value converter 11, quantization level obtd. by dividing a gap between the maximum and minimum values into 2<k> is compared with the respective pixel data, and the divided code of (k) bits is provided. The data outputted while being successively switched by a switcher 112 are converted to serial data by a parallel/serial converter 115.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus capable of high efficiency coding.

[0002]

2. Description of the Related Art Conventionally, for example, a high-efficiency coding system for television signals has been known as a processing system in this type of image processing apparatus. In this television signal high-efficiency coding method, a so-called MIN-MAX method is adopted in which the average number of bits per pixel is reduced because of the necessity of narrowing the transmission band. The MIN-MAX method will be described below.

Television signals have a strong spatiotemporal correlation. When the image is divided into minute blocks, each block often has a small dynamic range due to local correlation. Therefore, it is possible to perform very efficient compression by obtaining the dynamic range in each block and adaptively encoding.

Therefore, this encoding will be described in detail with reference to the drawings.

FIG. 3 is a diagram showing a schematic configuration of an image information transmission system as an example of the prior art. Reference numeral 301 in the figure denotes an input terminal, for example, a raster-scanned analog image signal such as a television signal is sampled at a predetermined frequency, and digital image data digitized into n-bit data per sample is input. . This 2 ⁿ gradation digital image data is output to the pixel block division circuit 302
Is supplied to.

FIG. 4 is a diagram showing how all pixel data for one screen is divided into pixel blocks. In the pixel block division circuit 302, all pixel data for one screen is temporarily stored in a memory or the like, and as shown in FIG. 4, r pixels in the horizontal direction (hereinafter, referred to as H direction) and vertical pixels (hereinafter, V direction) are stored. Pixel data is read in a pixel block unit composed of (r × s) pixels of s pixels in a direction. That is, the output is performed for each data of each pixel block.

FIG. 5 shows the structure of each pixel block. In the figure, D _{1,1 to} D _{s, r} represent pixel data. The image data output from the pixel block division circuit 302 includes a maximum value detection unit 303, a minimum value detection unit 304, and a timing adjustment unit.
Input to 305. As a result, of all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block, the one having the maximum value (D
_The one having the maximum value (D _max ) and the minimum value (D _min ) are detected by the detection units 303 and 304 and output.

On the other hand, in the timing adjusting unit 305, all pixel data is delayed by the time required for detecting the D _max and D _min in the maximum value detecting unit 303 and the minimum value detecting unit 304, and each pixel block is delayed. The pixel data is sent to the division value conversion unit 306 in a predetermined order. For example, D _1,1 , D _2,1 , D _3,1 , ..., D _{s, 1} , D _1,2 , ...,
_{D s, 2, ..., D} 1, (r-1), ..., D s, (r-1), D 1, r ..., and sends so on D _{s, r.} In this way, all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block and their maximum value (D _max )
And the minimum value (D _min ) are input to the division value conversion unit 306, and for each pixel data, a k-bit division code (Δ _1, which is compared with the quantization level ^{obtained by} dividing 2 ^k between D _max and D _min ) _{. 1 to} Δ
_{s, r} ). Here, k is an integer smaller than n, and the state of quantization is shown in FIG.

As shown in FIG. 6A, Δ _{i, j} is k
It is output as a binary code of bits. The k-bit division code Δ _{i, j} and n-bit D _max and D thus obtained
_min is the parallel-serial (PS) converter 307, 30
Data selector 3 with 7 ', 307 "converted to serial data
At 08, serial data as shown in FIG. 7 is obtained. Note that FIG. 7 shows transmission data for one pixel block.

The data output from the data selector 308 is time-axis processed by a first-in first-out memory (FIFO memory) 309 so that a constant data transmission rate is obtained, and a synchronization signal is added by a synchronization adding unit 310. Then, it is sent from the output terminal 311 to a transmission line (for example, a magnetic recording and reproducing system such as a VTR). Here, the addition of the synchronization signal may be performed for each pixel block or for each of a plurality of pixel blocks. The operation timing of each of the above-mentioned units is determined based on the timing signal output from the timing control unit 312.

FIG. 8 is a block diagram showing a schematic configuration of a receiving side corresponding to the data transmitting side shown in FIG. In FIG. 8, reference numeral 821 denotes a terminal to which the transmission data, which has been encoded with high efficiency on the transmitting side, is input. The sync signal in the input transmission data is separated by the sync separator 822 and supplied to the timing controller 823. The timing control unit determines the operation timing of each unit on the receiving side based on the synchronization signal.

On the other hand, in the data selector 824, the n-bit data D _max and D _{min in} the transmission data and the code Δ _{i, j} obtained by quantizing each pixel data between D _max and D _min by k bits.
Will be assigned to. This is converted into parallel data by serial-parallel (SP) converters 825 and 825 ', respectively. Maximum value data D _max and minimum value data D _{min in} each pixel block converted into parallel data by SP converter 825
Are latched by latch circuits 826 and 827, respectively, and the latched maximum value data D _max and minimum value data D _min are output to the division value inverse conversion unit 828, respectively. On the other hand, the division code Δ _{i, j} related to each pixel data in each pixel block is output by the SP converter 825 ′ in the predetermined order as described above, and is supplied to the division value inverse conversion unit 828.

FIG. 6B shows division codes Δ _{i, j} and D _max , D.
_In the figure showing how the representative value data D ′ _{i, j} related to the original pixel data is decoded from _min , the representative value is, for example, D
Set _max and D _min in the middle of each quantization level divided into 2 ^k . In this way, the n-bit representative value data (D ′ _{1,1 to} D ′ _{s, r} ) obtained by the division value inverse conversion unit 828 is output for each pixel block in the order described above. In the scan converter unit 829, the output data of the division value inverse conversion unit 828 is converted into the order corresponding to the raster scan, and the decoded image data is output to the output terminal 830.

[0014]

However, in the above-mentioned conventional example, the correlation of only the two-dimensional space of the image is utilized. Therefore, when transmitting a still image or an image with a small amount of motion, there is a drawback that the transmission information has a time-axis redundancy, and the same information is repeatedly transmitted, which deteriorates the transmission efficiency.

Accordingly, an object of the present invention is to provide
An object is to provide an image processing device capable of efficiently transmitting high-quality image information.

[0016]

In order to achieve the above-mentioned object, an image processing apparatus according to the present invention comprises an input means for inputting an image signal and an image signal input by the input means in a single screen. And a second coding mode for coding the image signal input by the input means on a block-by-block basis composed of image signals of a plurality of screens. An encoding unit having an encoding mode; and a transmitting unit for transmitting the first encoding mode and the second encoding mode such that predetermined data forming a unit encoded data string are arranged in different order. I have.

Further, in another image processing apparatus according to the present invention, a first coding mode for coding an input image signal in a block unit constituted by an image signal of a single screen and an image of a plurality of screens. A second coding mode for coding in block units constituted by signals is selectively used for coding, and a unit coded data string is used in the first coding mode and the second coding mode. An image processing apparatus for decoding encoded data transmitted so that the arrangement order of respective constituent data is different, and detecting for detecting an arrangement order of predetermined data forming a unit encoded data string of the encoded data. Means, decoding means for decoding the encoded data for each block, and control means for controlling the decoding processing by the decoding means according to the detection result of the detecting means. That.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail.

1 and 2 are diagrams showing a schematic configuration of an image information transmission system which is an example of an embodiment of the present invention. Here, FIG. 1 shows the configuration of the transmitting side, and FIG. 2 shows the configuration of the receiving side.

In FIG. 1, 101 is an input terminal, 102 is a pixel block division circuit, and 103 is a pixel block division circuit 102.
Of the pixel block division circuit 102 and the frame memory 103
, 105 is a motion detector that performs motion detection from the result of the subtractor 104, and 106 is an average value calculation circuit that calculates the average value of the output of the pixel block division circuit 102 and the output of the frame memory 103. , 107 is a switcher for selecting the output of the average value calculation circuit 106 and the output of the frame memory 103, 108 is a maximum value detector for obtaining the maximum value of the input value from the switcher 107, 109 is a minimum value detector, 110 Is a delay circuit that delays the input of the switch 107, 111 is a division value converter that converts the signal from the delay circuit 110 based on the data from the maximum value detector 108 and the minimum value detector 109, and 100 is a motion detector A switch that selects and outputs the output of the maximum value detector 108 and the output of the minimum value detector 109 based on the information of 105, 112 is a switcher that selects the output signal, and 113 is the data from the motion detector 105. Frame memory, 11
4 is a timing controller that controls the timing of each circuit in this system, and 115 is a parallel / serial converter that converts the parallel data from the switch 112 to serial data.
(PS) converter, 116 is a first-in first-out memory (FIFO memory), 117 is a synchronization adding circuit that adds a synchronization signal to the input signal from the FIFO memory 116, and 118 is an output terminal.

In the block diagram of the receiving side shown in FIG.
0 is a receiver input terminal, 121 is a serial-parallel (SP) converter that performs serial-parallel conversion, 122 is a sync separation circuit that separates the sync signal from the input signal, and 123 is based on the input from the sync separation circuit 122. A timing controller that controls the timing of each circuit, 124 is a maximum / minimum position detector that detects motion information from the data from the SP converter 121, 125 is a frame memory that stores the output signal of the maximum / minimum position detector 124, 126 is a maximum value detector that obtains the maximum value from the input from the SP converter 121, 127 is also a minimum value detector, and 128 is based on the data from the above detectors 126 and 127.
A division value inverse converter that inversely converts the signal from the SP converter 121, 129 is an address generator that generates an address of the frame memory 130 based on the output of the frame memory 125, and 131 is an output terminal.

The operation of each block will be described below step by step.

In the transmission side block shown in FIG. 1, an input terminal 101 samples a raster-scanned analog image signal such as a television signal at a predetermined frequency, and digitizes t-bit digital image data. Is entered. The 2 ^t gradation digital image data is supplied to the pixel block division circuit 102 and divided into pixel blocks composed of (r × s) pixels of r pixels in the horizontal direction and s pixels in the vertical direction. . That is, the output is performed for each data of each pixel block.

The image data output from the pixel block division circuit 102 is input to the frame memory 103, the subtractor 104, and the average value calculation circuit 106. The frame memory 103 delays the data by one frame and outputs the delayed data to the subtractor 104 and the average value calculation circuit 106. The subtractor 104 obtains the correlation in the time axis space by obtaining the difference between the data of the previous frame and the data of the current frame, and the motion detector 105 outputs the motion information.

The motion detector 105 compares the inter-frame difference value with a set threshold value and outputs 1-bit motion information. Based on the obtained motion information, it is determined which of the previously obtained average value between two frames (output of 106) or the original data delayed by one frame (output of 103) is to be encoded and transmitted. This operation is performed by the switch 107.

Based on this motion information, encoded transmission information as shown in FIG. 9 is output. For motion blocks,
The output of the frame memory is encoded by the MIN-MAX method and the information of each frame is transmitted. For static blocks,
The original data and the data one frame before, that is, the frame memory output

[0027]

[Outside 1]

Is encoded by the MIN-MAX method, and information for one frame is transmitted in two frames.

Specifically, first, the case where it is determined that the block is a motion block will be described. The output of the frame memory 103 is
It is input to the maximum value detector 108, the minimum value detector 109, and the delay circuit 110 via the switch 107. This gives the maximum value among all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block.
(D _max ) and the minimum value (D _min ) are detected by the maximum value detector 108 and the minimum value detector 109, and output to the switching device 100.

The switch 100 is a switch for selecting and outputting the output of the maximum value detector 108 and the output of the minimum value detector 109 based on the information of the motion detector 105. For example, a block in which the motion detector 105 is present is selected. When it is determined to be a "moving" image, the output D _max of the maximum value detector 108 is output to the terminal 2a of the switch 112, and the output of the minimum value detector 109 is output to the terminal 2b. When it is judged to be a "still" image, conversely,
D _max is switched to the terminal 2b and D _min is switched to the terminal 2a, respectively, and output.

On the other hand, in the delay circuit 110, all pixel data are delayed by the processing time of the maximum value detector 108 and the minimum value detector 109, and the pixel data are divided value converters in a predetermined order for each pixel block. Send to 111. For example, D _1,1 , D _2,1 , D _3,1 , ..., D _{s, 1} , D _1,2 , ..., D for each pixel block
_{, (R-1)} , ..., D _{s, (r-1)} , D _{1, r} , ..., D _{s, r} .

In this way, all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block and their maximum value (D _max ) and minimum value (D _min ) are input to the division value converter 111. Then, the quantization level ^{obtained by} dividing D _max and D _min by 2 ^k is compared with each pixel data to obtain a k-bit division code (Δ _{1,1 to} Δ _{s, r} ). Here, k is an integer smaller than t. The k-bit division code and t-bit D _max and D _min thus obtained are supplied to the switch 112.

The switch 112 is a switch that selects data according to the transmission order of transmission data. Due to the operation of these switching devices 100, 112, D _max , D _min , Δ _1,1 , ..., Δ _{s, r} for motion blocks and D _min , D _max , Δ _1,1 , ..., for static blocks. The data transmission order can be set in the order of Δ _{s, r} . That is, D _max , D _min
The output order of is changed according to the motion information and is output.

The data sequentially switched and output by the switch 112 is parallel / serial converter 115.
Is converted into serial data.

The data output from the switch 112 is time-axis processed by a first-in first-out memory (FIFO memory) 116 so as to have a constant data transmission rate, and a synchronization signal is added by a synchronization adding circuit 117. Then, it is sent from the output terminal 118 to a transmission line (for example, a magnetic recording / reproducing system such as a VTR). Here, the addition of the synchronization signal may be performed for each pixel block or for each of a plurality of pixel blocks. The operation timing of each of the above-mentioned units is determined based on the timing signal output from the timing controller 114.

Next, the case where it is determined that the block is a still block will be described.

In the frame A shown in FIG. 9, the output of the average value calculation circuit 106 is subjected to the same signal processing through the switch 107 and then output. At the same time, the motion information from the motion detector 105 is recorded in the frame memory 113. This frame memory 113 has one for each pixel block.
It may be configured with a bit data capacity. That is, (r ×
A capacity of s × 1) bits is sufficient.

In the frame B shown in FIG. 9, the image data is not transmitted and the compression rate is increased. Whether to transmit the image data in the B frame is determined by the frame memory 113.
Since the motion information for each block determined in the previous frame (A frame) is stored in, the control is performed based on this information.

FIG. 2 is a schematic block diagram of the receiving side. In the figure, 120 is an input terminal for inputting the signal from the above-mentioned transmitting side, and the transmitted data is a serial / parallel converter.
121 and the sync separation circuit 122. Sync separation circuit 122
Then, the sync signal in the input transmission data is detected and separated, and is supplied to the timing controller 123. The timing controller 123 determines the operation timing of each unit on the receiving side based on the synchronization signal.

On the other hand, in the serial / parallel converter 121, the serial input data is converted into parallel data, and the maximum / minimum position detector 124, the maximum value detector 126, the minimum value detector 127, and the division value inverse converter 128 are converted. Supply.

The maximum / minimum position detector 124 determines the order of D _max and D _min for each block in the transmitted information, and based on the result, it is determined whether the block is a motion block or a still block. Get motion information.

The motion information data for each pixel block obtained by the maximum / minimum position detector 124 is stored in the frame memory 125.
Is stored. Since the above data is sent from the transmitting side only when transmitting the A frame shown in FIG. 9, it is used when receiving and reproducing the B frame.

The divided value inverse converter 128 obtains D _max , D
_{Between min} and D _max , D _min is divided into 2 ^k , and the pixel data Δ _1,1 , ..., Δ _{s, r} from the SP converter 121 is converted into the divided value and output.

In the frame memory 130, the divided value inverse converter 12
The output of 8 is stored, converted into an order corresponding to the raster scan by the control signal of the address generator 129, and output to the output terminal 131 as decoded image data. At this time, data is written in the frame memory 130 for all pixels in the A frame of FIG. 9, but only pixels of the motion block are written in the B frame.

In the address generator 129, the frame memory
A write address is generated based on the information of 125 motion blocks, and at the time of reading, addresses are generated so that the pixel order corresponds to the raster scan as described above, and the data stored in the frame memory 130 is decoded image. The data is output from the output terminal 131.

In the above-mentioned embodiment, the motion information is described as the additional information, but it is not limited to this, and it goes without saying that other information may be used.

[0047]

As described above, according to the present invention, it is possible to obtain an image processing apparatus capable of efficiently transmitting the high-quality image information by removing the redundancy of the image information in the time direction.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a transmitting side in an example of an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a receiving side in an example of an embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a transmitting side of a conventional image information transmission system.

FIG. 4 is a diagram showing how all image data is divided into pixel block groups.

FIG. 5 is a diagram showing a data arrangement of each pixel block.

6 is a diagram showing conversion characteristics of a division value conversion unit in FIG. 3 and conversion characteristics of a division value inverse conversion unit in FIG.

FIG. 7 is a diagram for explaining data to be transmitted.

8 is a diagram showing a schematic configuration of a receiving side corresponding to the transmitting side of the image information transmission system shown in FIG.

FIG. 9 is a diagram for explaining the operation of FIGS. 1 and 2.

[Explanation of symbols]

 102 Pixel block division circuit 103 Frame memory 104 Subtractor 105 Motion detector 106 Average value calculation circuit 100,112,107 Switcher 108,126 Maximum value detector 109,127 Minimum value detector 110 Delay circuit 111 Divided value converter 114,123 Timing controller 115 Parallel / serial converter 121 Serial / parallel converter, 124 Maximum / minimum position detector 128 Divided value inverse converter 129 Address generator 130 Frame memory

Claims (2)

[Claims] 1. An input unit for inputting an image signal, a first encoding mode for encoding the image signal input by the input unit in block units composed of a single screen image signal, and Encoding means having a second encoding mode for encoding the image signal input by the input means in block units composed of image signals of a plurality of screens; the first encoding mode and the second encoding mode. An image processing apparatus comprising: a transmission unit that transmits the predetermined data forming a unit encoded data string in a different order from the encoding mode. 2. A first encoding method for encoding an input image signal in block units composed of a single screen image signal.
Coding mode and a second coding mode for coding in block units constituted by image signals of a plurality of screens are selectively used for coding, and the first coding mode and the second coding mode are used. An image processing apparatus for decoding transmitted encoded data so that the arrangement order of each data forming the unit encoded data string is different from the mode, and forming a unit encoded data string of the encoded data. Detecting means for detecting an arrangement order of predetermined data, decoding means for decoding the encoded data for each block, and control for controlling decoding processing by the decoding means according to a detection result of the detecting means. And an image processing apparatus.