JPH09190690A - Input/output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable multi-bits I/O constitution by reducing a peak current consumed in an output device, reducing power source noise caused by parasitic inductance of a power source cable, and improving data transfer rate. SOLUTION: This output device is provided with output circuits 0-4 inputting signals from data lines DATA 0-4, and driving output lines I/O 0-4 based ion control signals of four control lines Enable 0-4. And, the control lines are classified so as to have operation timing of four kinds, when it is assumed that the time for permitting output of a first control line is a first time t0 and a period from stopping the output to permitting output of the next data is t1, the period t1 is the same in the first to fourth control lines, and the first time of a (k+1)th control line is delayed from the first time of a kth (1<=k<=m) control line, and a first time of a fourth control line is faster than a second time (t0+t1) which is sum of a first time of the first control line and the period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output device for exchanging data between semiconductor devices, and more particularly to an output device in which output timings of data in a plurality of output circuits are shifted and a data input in a plurality of input circuits. The present invention relates to an input device whose timing is shifted.

[0002]

2. Description of the Related Art Today, due to the development of semiconductor microfabrication technology, large-scale, high-speed 32-bit, 64-bit MPU chips including several million transistors and a large-capacity 16M
Bit and 64 Mbit DRAMs have been produced. The operating frequency of MPU, etc. has been increased to 200 MHz, and the bus (BUS) width between MPU and memory is 3
It is spreading to 2 bits and 64 bits.

According to the operating frequency of the MPU, the operating frequency of the data bus is 60 Mb per pin.
/ S, 100Mb / s increased, 64 × 1 for the entire bus
The era of 00 Mb / s = 64 Gb / s is also serious. In such a situation, the amount of current flowing through the entire output circuit becomes enormous, and the fluctuation of the power supply line due to the parasitic inductance of the power supply line becomes extremely large, which causes malfunction unless some measures are taken.

FIG. 15 shows a conventional synchronous DRAM.
7 is an operation timing chart of (DRAM that operates in synchronization). All input / output signals operate in synchronization with the basic clock, and as shown in the figure, the / RAS and / CAS signals are taken in at the rising edge of the clock, and the output signal I / O
(0-3) is also generated at the timing when the receiving side can receive data at the rising edge of the clock.
Naturally, all outputs are generated at the same timing. This I
When the number of I / Os increases and the number of I / Os that perform simultaneous switching increases, the fluctuation of the power supply lines (Vcc, Vss) due to the parasitic inductance of the power supply lines becomes serious.

In the case of the output buffer, for example, the output is High.
When it changes from h to Low, the power supplies Vcc and Vss drop sharply once, and then largely swing to the opposite side due to the influence of the inductance, and this is repeated and attenuated. In particular, when the switching directions of all I / Os are the same, that is, when all the I / Os change from High to Low, the fluctuation of the power supply becomes maximum. This noise becomes in-phase noise in which Vcc and Vss swing in the same direction.

FIG. 16 is a diagram showing a conventional output device and its output line. In this example, four output lines I / O (0 to
3), an output buffer circuit for the same, and its power supply wiring. In many cases, the number of output lines is usually large, and often the I / O lines (input / output lines) are shared with the input lines. In this example, the input buffer is omitted and only the output buffer is shown.

Further, in this example, one power line (Vcc) and one ground line (Vss) are provided for four I / O lines.
Printed circuit board outside the package from the chip: P
The case where it is connected to a CB (Print Circuit Borad) via a bonding wire of the package via a lead frame is shown. In other words, the charging / discharging currents of the four I / O lines flow into the PCB via the two Vcc and Vss lines.
The power supply line sways due to the influence of the parasitic inductance L between the bonding wire and the lead frame. L
Usually has a value of several nH to several tens of nH per pin.

The output line also has parasitic inductance,
Bonding wire and lead frame in the package,
It is also on the PCB wiring. However, the problem is that if the characteristic impedance: Z0 (= root (L / C)) and the value of the terminating resistor Rt are matched and the impedance is matched, the fluctuation (ringing) and reflection of the I / O line can be suppressed. Conventional LV
Terminated LVTTL, CTT, GT that terminates the termination for the TTL compatible interface
The basis of new interface technologies such as L, SSTL, Rambus is a combination of this termination, impedance matching and small amplitude technology.

However, these techniques can only suppress the influence of the inductance of the I / O line, but cannot suppress the influence of the inductance of the power supply line. When the fluctuation of the power supply line becomes large, the output signal fluctuates first, and the correct “0” at the input side,
It becomes impossible to judge "1". Secondly, the swing of the power supply causes malfunction of the internal circuit of the chip. Third,
When the power supply of the chip fluctuates, it becomes difficult to judge "0" or "1" of the signal input to this chip, which causes a serious problem that correct reception cannot be performed.

Conventionally, the only method of suppressing the fluctuation of the power supply line is to reduce the driving ability of the driver at the final stage of the output device or to loosen the timing of turning it on to reduce the peak current. When the fluctuation of the power supply line becomes large, as shown in FIG.
As shown in (a), when the power supply of the output device and the power supply of the other parts of the chip are common, the influence of the inductance of the package is transmitted to the internal circuit and the input device, which causes the first problem and the second problem. The third problem becomes serious.

FIG. 17B shows a power supply line (VddQ, Vss) dedicated to the output device in order to solve the second and third problems.
Q) and other power supplies (Vcc ", Vss") are divided inside the chip, and package wiring is done with different pins, PC
It is connected to the power source line (Vcc ', Vss') on B.
In this case, the influence of the parasitic inductance (L1) between the bonding wire of the package of the output device and the lead frame can be reduced.

However, even in this case, the number of I / Os is 32, 64, 128, 256 even though the number of I / Os is small.
As the current increases, a large amount of current flows even if the number of power supply pins of the output device is increased. Therefore, the parasitic inductance (L4) on the PCB affects the power supply (Vcc ', Vss') on the PCB. The swing becomes large, and as a result, the power supply lines (Vcc ", Vss") of the chip internal circuit and the input circuit are swung through the other power supply pins, which causes the second and third problems. Become.

[0013]

As described above, in the conventional output device, since the output lines are switched at the same time, when the output frequency increases and the number of outputs increases, the fluctuation of the power supply line increases as the peak current increases. Becomes bigger, the first
Therefore, the output signal fluctuates, and the correct judgment of "0" or "1" cannot be made on the input side. Secondly, the fluctuation of the power supply causes malfunction of the internal circuit of the chip. Thirdly, the fluctuation of the power supply of the chip makes it difficult to determine "0" or "1" of the signal input to the chip, which causes a serious problem that correct reception cannot be performed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce multi-bit I / O without decreasing the operation speed of output, that is, without decreasing the data rate. An object of the present invention is to provide an output device capable of significantly reducing the peak value of the consumption current flowing through the power supply line even if the power supply line is switched, and suppressing the fluctuation of the power supply line due to the parasitic inductance of the power supply line, and an input device corresponding thereto. .

[0015]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure. That is, the present invention (claim 1) is n
(N ≧ 2) output lines, n output circuits that drive these output lines, n data lines that are respectively input to these output circuits, and the output circuits that are input to the output circuits. In an output device having n control lines that determine an output time to an output line of a circuit, the n control lines are classified into control lines having m kinds (first to mth) operation timings, The time for permitting the output of the first control line is the first time t
0, when the period until the output is stopped and the output of the next data is permitted is t1, the period t1 is the same for the first to mth control lines, and the kth (1 ≦ k <m) First control line
, The first time of the (k + 1) th control line is delayed,
The first time of the control line is the first time t of the first control line.
It is characterized by being earlier than the second time (t0 + t1) obtained by adding 0 to the period t1.

Further, according to the present invention (claim 7), there are n lines (n ≧).
2) input lines, n input circuits that take in data from these input lines, n data lines that output the input results of these input circuits, and the input circuits that are input to the input circuits. In the input device having n control lines that determine the input input time, the n control lines are classified into control lines having m (first to m) th operation timings, and the first control line First time to allow input of
Time t0, and the period from the stop of the input until the input of the next data is permitted is t1, the period t1 is the first to mth
Control lines are the same, and the first time of the k + 1th control line is delayed from the first time of the kth (1 ≦ k <m) control line, and the first time of the mth control line is delayed. Is the first of the first control lines
The second time (t0 + t) obtained by adding the period t1 to the time t0 of
1) It is characterized by being faster.

Here, preferred embodiments of the present invention include the following. (1) The n control lines are n / m (m> 1) m types (first
~ Be classified as a control line having m-th operation timing. (2) The time from the first time of the kth (1 ≦ k <m) control line until the output (or input) is stopped, and the output (or input) from the first time of the k + 1th control line. ) The time to stop is partly overlapping. (3) The first time of the k-th (1 <k ≦ m) control line is (first time t0 of the first control line) + (period t1) × (k−
1) / m. (4) For the m types of control lines, P that receives the first clock as input
It is generated using an LL (Phase Locked Loop) circuit. (5) The data line, output circuit (or input circuit), and control line are formed on the same semiconductor substrate, and the output line is a connection line to another semiconductor substrate. (Function) When there are n input / output lines (or output lines), conventionally, data is output at the same timing as n lines, data output is stopped at the same timing, and data is output at the same timing. However, in the present invention, n
The operation timings of the output circuit and the output line of the book are shifted. That is, n lines are divided into groups of m / n different timings, for example, n / m lines, and the output period of n lines is the same, but this timing is based on the output line timing at which one data is output. , The output timings of other m-1 types of outputs are dispersed and shifted during the timings when this output line outputs the next data.

As a result, it is possible to disperse the current peak generated at one timing in the past into m kinds of timing positions and to suppress the current peak due to the number of output lines of 1 / m at one timing. As a result, the influence of parasitic inductance on the power supply line can be suppressed. As the number of m is increased, the value of the current peak is reduced. Further, the input circuit of another chip that receives data from such an output circuit may be provided with an input circuit in which the timing of fetching m kinds of data is changed. The present invention has a great effect on multi-bit I / O having a large power supply noise.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 4 are views for explaining an output device according to a first embodiment of the present invention. FIG.
Shows an example of operation timing when the present invention is realized by a synchronous DRAM. / RAS and / CAS are fetched at the rising edge of the basic clock, and I / O is output from the output buffer with a 2-cycle CAS wait time.
Data is output to the lines (I / O0, I / O1, I / O2, I / O3). N _{0 to} N ₃ are output data of the first cycle, and N ₀ + i to N ₃ + i are output data of the i cycle.

The output of I / O0 is output at the timing when the chip to which other data is transferred can receive the data at the rising edge of the basic clock. On the other hand, the remaining I / Os (1 to 3) set the rising edge of the basic clock to 0 degrees and set the rising edge of the next cycle to 36 degrees.
If it is defined as 0 degree, the data is output at the timing of 90 degrees, 180 degrees, and 270 degrees out of phase, and the input side similarly.
Data is taken in at the timing of 90 °, 180 °, and 270 ° phase shifts.

As a result, the peak of the consumption current flowing through the power supply line connected to the output buffer is divided into four, and the peak value is reduced to approximately 1/4 of the conventional method in which all data is output simultaneously. To be done. Due to this effect, a large fluctuation of the power source due to the parasitic inductance of the power source line (package, PCB or chip wiring) is reduced while keeping the transfer rate (data rate) of the output data constant. Then, the conventional problems such as the malfunction of the input buffer and the delay of the input response due to the fluctuation of the output buffer, the malfunction of the internal circuit, and the fluctuation of the power supply are solved.

In the present embodiment, the disadvantage is that the data transfer is delayed by one cycle as compared with the conventional one, but
This is because if continuous transfer is repeated 64 times,
This defect is a negligible value at 1/64 of the conventional value. On the contrary, when the present embodiment is used, the fluctuation of the power supply is reduced, so that the output line driving capability of the output circuit can be increased or the speed of turning on the output circuit can be increased, and as a result the transfer rate itself can be increased. Further, since a larger number of I / Os can be provided, as a result, it is possible to increase the data rate seen in the entire chip.

The phase shift in FIG. 1 is (360 ° / 4) × k (k is a natural number) = 90 °, 180 °, 270
You don't have to be out of sync, it's between 0 and 360 degrees,
It can be any value.

FIG. 2 is a block diagram showing the configuration of the output device according to this embodiment. In this example, four types of output circuits are connected to the power supplies VddQ and VssQ dedicated to the output device, and four different types of output circuits output signals to the respective output lines I / O (0 to 3). The data output enable signal Enableφ (0 to 3) and the data Data (0 to 3) to be output, which are out of phase with each other, are input. If this output circuit has a data latch function, Data (0 to 0
Even if data is input to 3), the output phase can be easily shifted.

FIG. 3 shows an example of a detailed configuration of each output circuit shown in FIG. 2, and FIG. 4 shows an operation timing chart when two cycles are output. In the block diagram of FIG. 3, i is 0, 1,
Either 2 or 3 is shown. Each output circuit is composed of two D-type latch circuits (D-FF1i, D-FF2i) and an output buffer, and the preceding D-FF1i is the internal data RDi.
Data is latched at the rising edge of the latch clock latch. D-FF2i in the latter stage is DF
The output of F1i is taken in and latched at the rising edge of the Enable signal φi whose phase is shifted, and is output to the I / Oi line as it is in the output buffer.

FIG. 4 shows the operation timing. lat
Until the ch signal rises and rises again, DF
The fetched data is held in F1i, and in the meanwhile, the enable signal φ (0 to 0
It is captured again in 3) and output as is. D-FF2
Re-latch with i is, for example, Enable signal φ3
This is because the latch signal rises again while the signal is High and the data of the D-FF1i is changed to the next data.

As described above, according to the present embodiment, the timings of the signals output from the four output circuits to the I / O are dispersed and shifted, so that the current peak due to the number of output lines is ¼ at one timing. Can be suppressed to As a result, the influence of parasitic inductance on the power supply line can be suppressed. Therefore, the peak value of the consumption current flowing in the power supply line can be significantly reduced even if the I / O of multiple bits is switched without lowering the output operation speed, and the power supply line is parasitic due to the parasitic inductance of the power supply line. It is possible to suppress the shaking of the. (Second Embodiment) FIGS. 5 to 7 are views for explaining an input device according to a second embodiment of the present invention. FIG.
[FIG. 4] is a block diagram showing an input device in the present embodiment, for inputting a signal with a timing shift obtained in the first embodiment.

In this embodiment, the power source V dedicated to the input device is used.
Four kinds of input circuits are connected to ddQ ′ and VssQ ′, and the input circuits that output the respective input results to the data lines Data (0 to 3) have four kinds of data input permission signals with different phases. The data from the Enable φ (0 to 3) ′ and the input line I / O (0 to 3) are input. If this input circuit has a data latch function, I / O (0
Even if data is input to 3), the input can be easily taken in.

FIG. 6 shows an example of the configuration of the input circuit of the chip which receives the data transfer with respect to the output of FIG. 4, and FIG. 7 shows the operation timing when two cycles are input. In the block diagram of FIG. 6, i indicates 0, 1, 2, or 3. Each input circuit has two latch circuits (D-FF3
i, D-FF4i) and the preceding D-FF3i
Indicates that the data from the I / Oi line is phase-enable
It is captured and latched at the rising edge of the e signal φi. The D-FF 2i at the subsequent stage captures and latches the output of the D-FF 1i at the rising edge of the latch clock latch, and captures it as it is as the internal input signal Ii.

FIG. 7 shows the operation timing. The data on the data line I / Oi that is transferred out of phase is taken into the D-FF 3i at the rising edge of the Enable signal φ (0 to 3) in which the phase is transferred as it is. That D-
Data of FF3i is shared by D-FF4i
Capture at rising edge of signal. If the rising edge of the latch signal is delayed from the rising edge of the Enable signal φ3 and earlier than the rising edge of the Enable signal φ0, the data in phase will be input to the D-FF 4i.

In this embodiment, data with a phase shift is transferred to the data I / Oi line, but the input circuit also shifts the phase and latches the data in accordance with this, so that the timing at the time of capture is acquired. The margin can be taken for one cycle as in the conventional case. (Third Embodiment) FIG. 8 is for explaining a third embodiment of the present invention and is an example of an output device for driving a multi-bit I / O. In this example, 16-bit I / O (0
˜15), of which the output blocks that output signals to I / O (0 to 3) are output En that are phase-shifted into four types.
It is controlled by an enable signal φ (0 to 3) and I / O (0 to 0)
3) is out of phase. Similarly, I / O (4 to 7), I / O
O (8 to 11) and I / O (12 to 15) are out of phase with each other, conversely, I / O (0, 4, 8, 12) have the same phase, and I / O (12 O (1, 5, 9, 13) is the same, I / O (2, 6, 10, 14) is the same, I / O
(3, 7, 11, 15) are the same.

As described above, in the case of an n-bit I / O, if it is configured with m kinds of phase shifts, those having the same phase are n /
There are m lines, and the values of n and m can be freely selected. (Fourth Embodiment) FIG. 9 is a diagram showing an input / output device according to a fourth embodiment of the present invention.
ed Loop), the clock timing between chips is adjusted, and a signal having an internal frequency multiplied by m is generated in the PLL, and m different types of phase clocks are generated from this. In this example, four types of phase clock φ (0 to 3)
Is generated and data is transferred between the chips A and B in four types of phases.

By using the PLL in this way, it is possible to easily divide the basic clock into m and generate clocks whose phases are evenly shifted (case 1). In the present embodiment, even if the PLL is not used, if the circuits that generate a constant phase shift are mounted on the chips A and B, it is not necessary to divide them separately (case 2). Further, in the chips A and B, the four types of phase clocks φ (0 to 3) and the phase clocks φ (0 to 3) ′ do not necessarily have to match (case A), and they can be used as I / O line transmission lines. Of the phase clock φ (0 to 0
3) 'can be delayed (case B). in this case,
It is possible to improve the timing margin of the input latch and the data rate. (Fifth Embodiment) FIG. 10 shows an example of operation timing in the fifth embodiment of the present invention. In this example, the first
Shows the case of using 8 kinds of phase shift.
Data is transferred to the I / O line with a phase shift of 360/8 degrees with respect to the output cycle of I / O0. In this case, the peak of the current flowing through the power supply can be reduced more than in the example of FIG. 1, and the amount of power supply noise due to parasitic inductance can be reduced.

Second, in this example, the cycle of the basic clock is doubled from that in FIG. The data output / input I / O0 input side is fetched at both the rising and falling edges of the basic clock. This is effective when the data rate becomes high and it becomes difficult to increase the frequency of the basic clock that connects the chips. Even in this case, this embodiment can be easily applied.

11 to 14 show the effect of the present invention by using a simulation. FIG. 11 shows 8
The present invention in the case of being divided into types of phases and a conventional simulation waveform are shown. As a hypothesis, the power supply line dedicated to the output circuit and pin (VddQ, VssQ) and the other internal circuit power supply line and pin (Vcc, Vss) are divided, and it is assumed that the parasitic inductance per pin is 10 nH, and Vdd
One Q and one VssQ are arranged for every four I / O lines. The output I / O line assumes a transmission line of 10 cm,
The characteristic impedances are shown in the case where the termination is performed by the 50Ω and 50Ω termination resistors, impedance matching is performed, and the fluctuation of the I / O line due to the parasitic inductance of the I / O line is eliminated. The waveform of each I / O line is observed at the point where the influence of power supply noise on the output drive transistor side can be seen.

With respect to the basic clock of 400 MHz (a), (b) shows the waveform of the conventional I / O (0 to 7) when the parasitic inductance of the power supply line is 0 nH.
Due to the impedance matching of the I / O line, there is no fluctuation in the I / O line. On the other hand, (c) is 10 nH / power supply pin
The case where the parasitic inductance of is added is shown. Power supply Vdd
The violent shaking of Q and VssQ and the accompanying violent shaking of the I / O line can be observed. Since the I / O line is impedance-matched, it can be seen that this fluctuation is due to the inductance of the power supply line.

On the other hand, (d) and (e) are the present invention,
The waveform is shown when the phase is shifted by 1/8 of the clock cycle. (D) shows the case where the output value of I / O (0-7) changes from "LLLLLLLL" to "HHHHHHHH", and (e) shows the case where it changes from "HLHLHLHLHL" to "LHLHLHLHH". In any case, it can be seen that the fluctuation of the power supply and the fluctuation of the I / O line are significantly reduced as compared with the conventional method.

FIG. 12 shows a transmission line of 20 cm and a power supply line Vdd at data rates of 200 Mb / s and 400 Mb / s.
The maximum fluctuation voltage of Q and VssQ is shown. In the drawing, the triangular marks are conventional examples, the circles and the X marks are values of the present invention, and when the phase shift with respect to the basic clock is changed to 1/2 to 1/16 (that is, the type of phase shift is 2 to 2). (When changed to 16). It will be understood that the present invention is more effective as the number of types of phase shift is increased. FIG. 13 is the same as FIG. 12 except that the length of the transmission line is changed from 20 cm to 10 cm.

FIG. 14 shows a power supply line dedicated to the output circuit and a pin.
(VddQ, VssQ) and other internal circuit power supply lines and pi
Even if n (Vcc, Vss) is divided, if there is a parasitic inductance on the PCB power line, VddQ, Vss
Here's how the Q noise gets on the PCB and how it swings other power supplies inside the chip. Where PC
The parasitic inductance of the power supply line on B is 0.3 nH, PC
It is assumed that the capacitance of the stabilizing capacitor on B is 1 μF and the capacitance between Vcc and Vss inside the entire chip is 10 nF.

When the number of I / O is 16, the conventional method is Vs
The fluctuations of the internal power supplies Vcc and Vss (black circles) are only small values with respect to the large fluctuations of sQ and VddQ (white circles), but when the I / O count increases to 32, 64, 128, 256, The fluctuations of the power supplies Vcc and Vss (black circles) greatly increase. On the other hand, in the present invention, VssQ, VddQ (white triangles) and Vs are worst depending on the output pattern.
It can be seen that both s and Vcc (black triangle) can suppress the power source noise due to the inductance to a small level. Where the triangle is I
When the output value of / O changes from "HHHH ..." to "LLLL ...", the squares change from "HLHL ..." to "LHLH."
... "

From FIG. 14, the internal power supplies Vss, Vc
Assuming that the upper limit of the fluctuation of c is 0.5 V, it is 32 in the conventional method.
It can be seen that 256 I / O numbers can be provided in the present invention, whereas only I / O numbers for books are recognized.

The present invention is not limited to the embodiments described above. In the embodiment, the example applied to the DRAM has been described, but the present invention is not limited to this and can be applied to various memories. Further, the semiconductor device is not necessarily limited to the memory, and any semiconductor device having a plurality of output circuits can be applied. In addition, various modifications can be made without departing from the scope of the present invention.

[0043]

As described in detail above, according to the present invention, the timing of data output in the plurality of output circuits is shifted, so that the read data rate is not lowered.
The consumption current peak can be suppressed, and thus the power supply noise due to the parasitic inductance of the power supply line can be significantly reduced. This effect makes it possible to realize a large number of I / Os in one chip and improve the transfer rate when the maximum noise is constant.

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation timing of a thin cross DRAM according to a first embodiment.

FIG. 2 is a block diagram showing a circuit configuration of an output device according to the first embodiment.

FIG. 3 is a diagram showing an example of a detailed configuration of each output circuit in FIG.

FIG. 4 is a diagram showing an operation timing in the output circuit of FIG.

FIG. 5 is a block diagram showing a circuit configuration of an input device according to a second embodiment.

6 is a diagram showing an example of a detailed configuration of each input circuit in FIG.

7 is a diagram showing operation timing in the input circuit of FIG.

FIG. 8 is a block diagram showing an output device of multi-bit I / O according to a third embodiment.

FIG. 9 is a block diagram showing an input / output device and a transfer line according to a fourth embodiment.

FIG. 10 is a diagram showing operation timing in the fifth embodiment.

FIG. 11 is a diagram showing operation simulation waveforms according to the present invention and the related art.

FIG. 12 is a diagram showing changes in power supply noise with respect to a phase shift between the present invention and the related art.

FIG. 13 is a diagram showing changes in power supply noise with respect to a phase shift between the present invention and the related art.

FIG. 14 is a diagram showing changes in power supply noise with respect to the number of output I / Os according to the present invention and the related art.

FIG. 15 is a diagram showing operation timing of a conventional synchronous DRAM.

FIG. 16 is a diagram showing an example of a conventional output device and its output line.

FIG. 17 is a diagram showing a formation state of parasitic inductance in a conventional output device.

[Explanation of symbols]

 / RAS, / CAS ... DRAM control signal I / O (0 to 7) ... I / O line (transmission line) Enable .phi. (0 to 3) ... Output enable signal Enable .phi. (0 to 3) '... Input enable signal latch ... Latch Signal D-FF (1i to 4i) ... D-type latch circuit VssQ, VddQ ... Output device dedicated power supply line VssQ ', VddQ' ... Input device dedicated power supply line

Claims (12)

[Claims] 1. n (n ≧ 2) output lines, n output circuits for driving these output lines, n data lines respectively inputted to these output circuits, and the output. An output device comprising: n control lines that are input to a circuit and determine an output time to an output line of the output circuit, wherein the n control lines are m kinds (first to mth) operation timings. Assuming that the time period for which the output of the first control line is permitted is the first time t0 and the period for stopping the output and permitting the output of the next data is t1, the period t
1 is the same as the 1st to mth control lines, and is the kth (1 ≦
The first time of the (k + 1) th control line is delayed from the first time of the (k <m) control line, and the first time of the mth control line is the first time.
The output device is earlier than a second time (t0 + t1) obtained by adding the period t1 to the first time t0 of the control line. 2. The n control lines are classified into control lines having m / m (m> 1) m kinds (first to mth) of operation timings. 1. The output device according to 1. 3. A time from the first time of the k-th (1.ltoreq.k <m) control line until its output is stopped, and the time from the first time of the k + 1-th control line to its output being stopped. 2. The output device according to claim 1, wherein the parts are partially overlapped with each other. 4. The first time of the k-th (1 <k ≦ m) control line is (first time t0 of the first control line) + (period t1).
The output device according to claim 1, wherein the output device is x (k-1) / m. 5. The output device according to claim 1, wherein the m kinds of control lines are generated by using a PLL (Phase Locked Loop) circuit having a first clock as an input. 6. The output device according to claim 1, wherein the data line, the output circuit, and the control line are formed on the same semiconductor substrate, and the output line is a connection line to another semiconductor substrate. . 7. n (n ≧ 2) input lines, n input circuits for respectively fetching data from these input lines, and n data lines for outputting the input results of these input circuits, respectively. And n control lines that are input to the input circuit and determine an input capturing time of the input circuit, wherein the n control lines are m kinds (first to mth) operation timings. Assuming that the time for allowing the input of the first control line is the first time t0 and the time until the input is stopped and the input of the next data is allowed is t1, the time is t
1 is the same as the 1st to mth control lines, and is the kth (1 ≦
The first time of the (k + 1) th control line is delayed from the first time of the (k <m) control line, and the first time of the mth control line is the first time.
The input device is characterized by being earlier than a second time (t0 + t1) obtained by adding a period t1 to the first time t0 of the control line. 8. The n control lines are classified into n / m (m> 1) control lines having m types (first to mth) of operation timings. 7. The input device according to 7. 9. A time from the first time of the kth (1.ltoreq.k <m) control line to the stop of its input, and the time from the first time of the k + 1th control line to the stop of its input. 8. The input device according to claim 7, wherein the and are partially overlapped. 10. The first time of the k-th (1 <k ≦ m) control line is (first time t0 of the first control line) + (period t.
1) × (k−1) / m.
Input device as described. 11. The input device according to claim 7, wherein the m kinds of control lines are generated by using a PLL (Phase Locked Loop) circuit having a first clock as an input. 12. The output device according to claim 7, wherein the data line, the input circuit, and the control line are formed on the same semiconductor substrate, and the input line is a connection line to another semiconductor substrate. .