JPH09185641A - Arrangement design method for standard cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip size and to decrease the waste of chip area. SOLUTION: Unit cell areas are made different, plural standard cell groups having different cell forms are registered in a library, and arrangement design is performed by selecting any standard cell group having the minimum cell column area out of the plural standard cell groups for each cell column such as 12A or 12B. As a result, the arrangement design is performed at the cell column 12A while using standard cells in the standard cell group having the small unit cell area and the arrangement layout is performed at the cell column 12B while using standard cells in the standard cell group having the large unit cell area. Thus, the chip size can be reduced and the waste of chip area can be decreased rather than the case of using only one standard cell group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for standard cells used in the manufacture of LSIs and the like, and in particular, layout design is performed by selecting a standard cell group having a minimum cell row area for each cell row. This makes it possible to reduce the chip size and reduce the waste of the chip area.

[0002]

2. Description of the Related Art Conventionally, standard cell type ICs (integrated circuits)
As a configuration method, a standard cell group of either one-stage type or two-stage type is registered in a library, and when a circuit to be integrated is given, the internal layout of the functional blocks forming the circuit is represented. It is known that standard cells are read out from a library and arranged in a region corresponding to the surface of a semiconductor chip (for example, a screen of a display device) as one or a plurality of cell columns.

FIG. 7A illustrates an inverter standard cell NOT belonging to the one-stage standard cell group. The cell NOT includes an inverter Q composed of N-channel and P-channel MOS type transistors T _N and T _{P. The} transistors T _N and T _P are connected at their gates and at their drains, and the source of the transistor T _P is connected. _{Is connected to} the power supply line L ₁ of high potential V _DD and the source of the transistor T _N is connected to the power supply line L ₂ of low potential V _SS , respectively.

In addition to the cell NOT, the one-stage type standard cell group includes standard cells representing the internal layout of functional blocks such as NAND circuits and flip-flop circuits.

FIG. 7B illustrates an inverter standard cell NOT belonging to the two-stage standard cell group. The cell NOT includes complementary MOS type inverters Q ₁ and Q ₂ having the same configuration as that of the inverter Q of FIG. 7 (A), and the inverter Q _{1 is connected} to the first power supply line L ₁₁ of high potential V _DD and low potential. 7 shows an internal layout in which an inverter Q ₂ is connected between a power supply line L ₀ of V _{SS and} an inverter Q ₂ is connected between a second power supply line L ₁₂ and a power supply line L ₀ of high potential V _DD .

In addition to the cell NOT, the two-stage standard cell group includes standard cells representing the internal layout of functional blocks such as NAND circuits and flip-flop circuits.

[0007]

Generally, an inverter,
Functional blocks such as NAND circuits and flip-flop circuits differ in the number of transistors used, and the more complex the function, the greater the number of transistors used. Therefore, it is customary that the plurality of standard cells respectively representing the internal layouts of the plurality of types of functional blocks have different cell areas.

FIG. 8 shows an inverter and a NAN as an example.
It shows the cell column area according to the standard cell type for the standard cells NOT, NAN, and FF respectively corresponding to the D circuit and the flip-flop circuit.

In the single-stage standard cell group, the standard cell (unit cell) having the smallest cell area is defined as the standard cell NOT (FIG. 7).
(Corresponding to (A)), and its area is S, the areas of the standard cells NAN and FF can be expressed as 2S and 6S, respectively, as shown in FIG. 8A. Further, in the two-stage standard cell group, if the standard cell (unit cell) having the smallest cell area is the standard cell NOT (corresponding to FIG. 7B) and the area is 2S, the areas of the standard cells NAN and FF are Can be represented as 2S and 4S, respectively, as shown in FIG.

As standardized circuits to be integrated on one semiconductor chip, seven standard cells NOT, NAN and FF are provided.
It is assumed that a circuit including four, six and six is given. In this case, when the layout design is performed by using the above-mentioned one-stage standard cell group, the cell rows 2A to 2C as shown in FIG.
A cell arrangement including is obtained. Further, in the same case, when the layout design is performed using the above-described two-stage standard cell group, a cell layout including the cell rows 4A and 4B is obtained as shown in FIG.

In the cell arrangement of FIG. 9, cell rows 2A-2
The total area of C is 15S + 18S + 18S = 51S. In the cell arrangement of FIG. 10, the total area of the cell rows 4A and 4B is 24S + 22S = 46S. Therefore, the size of the semiconductor chip 1 having the cell arrangement shown in FIG. 9 needs to be larger than the size of the semiconductor chip 3 having the cell arrangement shown in FIG.

As is apparent from the above example, when integrating a circuit, one-stage standard cell groups are used or two
The chip size may differ depending on whether a standard stepped cell is used. The one-stage type standard cell group requires a small cell column area to form a circuit by arranging standard cells having a simple function with a small number of transistors, but a standard cell having complicated functions such as a flip-flop circuit is arranged to form a circuit. When it is constructed, the cell column area becomes large. The two-stage standard cell group requires a small cell column area to form a circuit by arranging standard cells having complicated functions such as a flip-flop circuit, but the standard cells having simple functions such as an inverter are arranged side by side. When configuring the above, the unused transistor may be generated, and the chip area is wasted.

An object of the present invention is to provide a novel standard cell layout designing method which can reduce the chip size and reduce the waste of the chip area.

[0014]

A standard cell layout design method according to the present invention is a step of registering a plurality of standard cell groups in a library, and each standard cell group has an internal layout of a plurality of types of functional blocks. A plurality of standard cells each of which represents a standard cell group, and a unit cell having the smallest cell area among the plurality of standard cells in each standard cell group has different unit cell areas from each other. And a step of reading a plurality of standard cells respectively corresponding to a plurality of functional blocks forming a circuit to be integrated from the library and arranging them as one or a plurality of cell rows in a region corresponding to the surface of the semiconductor chip,
One standard cell group that minimizes the cell column area for each cell column is selected from the plurality of standard cell groups, and standard cells belonging to the selected standard cell group for each cell column are read from the library. And those arranged in the area.

According to the method of the present invention, the standard cell group that minimizes the cell row area is selected for each cell row, and the layout design is performed using the standard cells in the standard cell group related to the selection. Therefore, the total cell column area can be reduced and the chip size can be reduced as compared with the case where standard cells in one predetermined standard cell group are used. In addition, since a standard cell group having a large unit cell area may not be selected, the number of unused transistors can be reduced and waste of the chip area can be reduced.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION When carrying out the present invention, a plurality of standard cell groups are registered in a library. As an example, the one-stage type and two-stage type standard cell groups as described above with reference to FIGS. 7 and 8 are registered in the library.

Next, standard cells respectively corresponding to a plurality of functional blocks forming a circuit to be integrated are read from the library and arranged in one or a plurality of cell rows in a region corresponding to the surface of the semiconductor chip. In this case, a standard cell group that minimizes the cell column area is selected from the library for each cell column, and the layout design is performed using the standard cells in the standard cell group related to the selection.

For example, as a circuit to be integrated, standard cells NOT, NAN, and FF are each provided in the same manner as in the above-described example.
It is assumed that a circuit including four, four and six is given.
When the layout design is performed using the one-stage type and two-stage type standard cell groups registered in the library, as shown in FIG.
A cell arrangement including 2A and 12B is obtained.

A procedure for obtaining such a cell arrangement will be described with reference to FIGS. First, in the step of FIG. 2, any one standard cell group in the library is selected and provisionally arranged. For example, if a single-stage standard cell group is selected and provisionally arranged, as shown in FIG.
A cell arrangement including 2C is obtained. This cell arrangement is shown in FIG.
Is the same as that shown in FIG.

Next, a standard cell group that minimizes the cell row area is selected for each cell row, and the standard cells are replaced if necessary. In the example of FIG. 3, standard cells of the one-stage type, two-stage type, and two-stage type are selected for the cell rows 12A, 12B, and 12C, respectively, and the one-step type standard cell group is selected for the cell rows 12B and 12C. Instead of the standard cell to which it belongs, standard cells belonging to the two-stage standard cell group are arranged. After this, the process moves to the first layout changing step, and the shortened and lengthened cell strings are combined or divided. In the example of FIG. 3, cell row 1
Since 2B and 12C have become shorter, the cell row 12C is combined with the cell row 12B as indicated by the arrow. As a result, FIG.
A cell arrangement including the cell rows 12A and 12B is obtained as shown in FIG.

Next, in the second step of changing the layout,
The individual standard cells are replaced so that the cell column area becomes smaller while considering the wiring efficiency. In the example of FIG. 4, the standard cell F ₁ for the flip-flop circuit of the cell array 12A has a smaller area when it is a two-stage standard cell. Move to the left of cell F ₂ . Also, the NAND of the cell row 12B
The standard cell NA ₁ for a circuit is moved to a position where the standard cell F ₁ is removed as a one-stage standard cell. Further, since the inverter standard cells N ₁ and N ₂ of the cell row 12B have a smaller area when formed as a single-stage standard cell, the inverter standard cell N ₃ and NAND in the cell row 12A are formed as a single-stage standard cell. It is moved to the standard cell for circuit NA ₂ .

FIG. 5 shows the result of such a layout change, and the cell layout of FIG. 5 is the same as that of FIG.
According to the cell arrangement of FIG. 1, the total of the cell row areas of the cell rows 12A and 12B is 13S + 26S = 39S, and the size of the semiconductor chip 10 can be reduced as compared with the case of either FIG. 9 or FIG. Further, since all the inverter standard cells NOT are arranged in the cell row 12A as single-stage standard cells, the number of unused transistors is reduced as compared with the case of FIG. 9, and waste of the chip area can be reduced. .

FIG. 6 shows an example of a cell placement process suitable for implementing the present invention in an automatic placement design system.

At step 20, temporary placement is performed using one standard cell group selected from the library (FIG. 2). Then, in step 22, a standard cell group having the smallest cell row area is selected for each cell row, and the standard cells are replaced if necessary (FIG. 3). At this time, which standard cell group has the smallest cell column area can be determined by calculating the cell column area for each standard cell group and comparing the standard cell groups.

Next, in step 24, it is determined whether the chip size is the smallest. The smallest chip size means
This means that the total cell column area is the minimum, which corresponds to the total cell column area being 39S in the examples of FIGS.

If the result of the determination in step 24 is negative (N), the process proceeds to step 26 and the layout changing process is performed (FIGS. 3 and 4). Then, the process returns to step 24, and the arrangement changing process of step 26 is repeated until the chip size is determined to be the minimum. When the determination result of step 24 is affirmative (Y), it means that the cell arrangement with the smallest chip size has been obtained, and the processing ends. It should be noted that after the arrangement changing process in step 26, the process may return to step 22 as indicated by the broken line.

The present invention is not limited to the above-described embodiment, but can be implemented in various modified forms. For example, three or more types of standard cell groups having different unit cell areas and different cell shapes may be registered in the library.

[0028]

As described above, according to the present invention, a standard cell group that minimizes the cell column area is selected for each cell column,
Since the layout design is performed using the standard cells in the standard cell group related to the selection, the chip size can be reduced and the waste of the chip area can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a standard cell arrangement according to the present invention.

FIG. 2 is a plan view showing a temporary placement step in the standard cell placement design method according to the present invention.

3 is a plan view showing a cell group selecting step and a first arrangement changing step following the step of FIG. 2. FIG.

FIG. 4 is a plan view showing a second arrangement changing step following the step of FIG.

5 is a plan view showing a cell arrangement after the steps of FIG. 4 are completed. FIG.

FIG. 6 is a flowchart showing an example of cell placement processing.

FIG. 7 is a diagram showing conventional one-stage and two-stage standard cells.

FIG. 8 is a plan view showing a cell area according to a standard cell type for each functional block.

FIG. 9 is a plan view showing a cell arrangement using a single-stage standard cell.

FIG. 10 is a plan view showing a cell arrangement using a two-stage standard cell.

[Explanation of symbols]

10: semiconductor chip, 12A, 12B: cell row, NO
T: Standard cell for inverter, NAN: Standard cell for NAND circuit, FF: Standard cell for flip-flop circuit.

Claims (1)

[Claims] 1. A step of registering a plurality of standard cell groups in a library, each standard cell group including a plurality of standard cells each representing an internal layout of a plurality of types of functional blocks. When the unit cell is the unit cell having the smallest cell area among the plurality of standard cells, the unit cell areas are different between the plurality of standard cell groups and the plurality of functional blocks forming the circuit to be integrated, respectively. A step of reading a plurality of standard cells from the library and arranging them in a region corresponding to the surface of the semiconductor chip as one or a plurality of cell columns, each standard cell having a minimum cell column area A group is selected from the plurality of standard cell groups, and standard cells belonging to the standard cell group related to selection are read out from the library for each cell column, and A layout design method for standard cells including those to be placed in an area.