JPH09185518A - System and device for generating power of source element alpha - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system/device for generating the power of a source element α, by which the necessary number of gates is small and the change of a generated polynomial is easy. SOLUTION: In the system for generating the power of the source element α, which generates the power of α being the source element of the generated polynomial, α-multipliers 202, 203, 204,... constituted only by adders 210 are connected in series by the desired number of stages. The arbitrary power of α(α<b> ) held by a storage means 201 is inputted to the α-multiplier 202 in an initial stage, and the α-multipliers of the respective stages sequentially generate and output the powers of α (α<b+1> , α<b+2> , α<b+3> .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power generation method of a primitive element α and its apparatus in an encoding apparatus and a decoding apparatus using Reed-Solomon code.

[0002]

2. Description of the Related Art Reed-Solomon code (hereinafter abbreviated as RS code) is an excellent code having the largest minimum distance among cyclic codes having the same code length and the number of information symbols, and is used in many fields. It's being used.

In the RS code, there is a field generation polynomial (also called primitive polynomial) which is an irreducible polynomial. The remainder of this field generator polynomial is a Galois field, and the set of remainders is the power of α which is the primitive element of the field generator polynomial {α,
It can be expressed by α ² , α ³ , ...}.

At the time of RS coding, information data is coded using a code generation polynomial whose root is this continuous power of α. Also in the RS decoding, the above continuous α-power is used in the Chien search for obtaining the error position and the error value.

The conventional α-power generation means in RS coding and decoding, for example, as shown in FIG. 4, holds all necessary α-power values in a register 401 which is a storage means, and outputs the output values. I'm using it.

[0006]

However, in order to configure the register 401 which is the storage means, normally 6 gates are required per bit, and in order to store all values of α exponentiation, a large number of gates are required. There was a problem that required.

For example, the field generator polynomial "X ³ + X + 1",
When generating a code generation polynomial as 2 error correction, the number of bits of one α-power is 3 bits, and the number of required α-power is twice the number of error corrections, that is, 4 (total 3 bits × 4 =) A 12-bit register was used. In this case, the number of gates required to configure the register is 72 gates (6 gates × 12 bits =) from 6 gates of 1 register (1 bit).

Further, when changing the field generation polynomial, it is necessary to re-input all 12 bits held by this register, which causes a problem that the number of bits to be re-input increases.

In view of the above problems, the object of the present invention is to reduce the number of required gates and to easily change the generator polynomial.
A power generation method of and a device therefor.

[0010]

In order to solve the above problems, the present invention has the following arrangement. That is, the invention according to claim 1 is a power generation method of a primitive element α that generates a power of α that is a primitive element of a field generation polynomial, and an α multiplier configured only by an adder is connected in series by a desired number of stages, An arbitrary α-power (α ^b ) is input to the α-multiplier of the first stage, and further α-power (α ^{b + 1} ,
α ^{b + 2} , α ^{b + 3} , ...) is sequentially generated and output, which is a power generation method of the primitive element α.

According to a second aspect of the present invention, in the power generation device of the primitive element α for generating the α power which is the primitive element of the field generation polynomial, a storage means for holding any input α power (α ^b ). And each consist of adders only,
A plurality of α multipliers whose outputs are connected to the inputs of the latter stage, and the inputs of the first stage of the plurality of α multipliers are connected to the outputs of the storage means, Further multiplication of α by the multiplier (α ^{b + 1} , α ^{b + 2} , α ^{b + 3} ,
) Is generated and output in sequence.
This is a power generation device of.

With the above configuration, the α-power generation method and the apparatus thereof according to the present invention have only one storage unit for the α-power, and since the α-power multipliers connected in series generate higher-order α-power. , It is possible to reduce the number of gates at a place where α-power which is an element of the field generation polynomial is required.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 (a),
(B) is a block diagram showing a configuration of an RS encoding device and an RS decoding device to which the power generation method of the primitive element α according to the present invention is applied, respectively.

As shown in FIG. 1A, the RS encoder comprises an RS encoder 101 and an α-power generation circuit 102 which supplies the power of α to the RS encoder 101. Then, at the time of RS encoding, the RS encoder 101 encodes the information data I (x) using the code generation polynomial G (x) having a root of the power of α which is the element of the field generation polynomial. Encoded data F (x) is obtained.

Here, the code generation polynomial G (x) has as a root a power of a number equal to a multiple (2t) of the error correction number (t), and using the output value of the power generation circuit 102,

Is calculated by Equation 1] G (X) = (X- α b) (X-α b + 1) ··· (X-α b + (2t-1)) ... (1) Equation (1). Here, t is the number of error corrections.

Next, the structure of the RS decoding device shown in FIG. 1B will be described. As shown in FIG. 1B, the RS decoding device includes an α-power generation circuit 102, a syndrome calculator 104, a Euclidean mutual arithmetic operator 105, a Chien search circuit 106, a delay circuit 107, and a correction execution circuit. And 108.

When decoding the RS code, first, the syndrome calculator 104 calculates the syndrome polynomial S (x) indicating the error position and the size from the received data R (x). Next, this syndrome polynomial S (x) is input to the Euclidean algorithm operator 105, and an error evaluation polynomial ω (x) that serves as an index of error magnitude and an error locator polynomial σ (x) that serves as an index of error position are input. To calculate. Then
The error evaluation polynomial ω (x) and the error locator polynomial σ (x) are input to the Chien search circuit 106 to calculate the error position and the error value. The calculated error position and error value,
The reception data R (x) delayed by the delay circuit 107 is input to the correction execution circuit 108, and the decoded data I ′ (x) is output.

Here, the syndrome polynomial S (x) is
Using the α-power that is the root of the code generation polynomial G (x) generated by the α-power generation circuit 102,

[Number 2] S (x) = R (α b) + R (α b + 1) + ··· + R (α b + (2t-1)) is calculated by ... (2) (2).

The output of the α-power generation circuit 102 is
Also in the Chien search circuit 106, the error locator polynomial σ
It is used when a root is searched by successively substituting α-power to (x) and checking whether σ (α ⁱ ) is 0 or not. The α-power generation circuit 102 used in the RS encoding device and the RS decoding device has the same configuration.

In FIG. 2A, the field generator polynomial is represented by "X ³ + X".
FIG. 2B is a configuration diagram of an α-power generation circuit required when generating a code generation polynomial with +1 ″ and an error correction capability of 2 error correction. FIG. 2B is a detailed diagram of an α multiplier.
FIG. 2C is a logic circuit diagram showing a gate configuration example of the adder (exclusive OR).

As shown in FIG. 2A, the α-power generation circuit has a 3-bit register 201, an α multiplier 202 whose input is connected to the parallel output of the register 201, and an output of the α multiplier 202. An α multiplier 203 having an input connected,
α multiplier 20 whose input is connected to the output of α multiplier 203
And 4. Note that the α multipliers 202 and 20
Reference numerals 3 and 204 are α multipliers having the same internal configuration and connected in series as shown in FIG. 2B.

Next, the operation of the α-power generation circuit having the above configuration will be described. First, the vector value of the minimum root (α ^b ) of an arbitrary code generation polynomial is input to the register 201, for example, serially. The vector value of α ^b is output in parallel from the register 201, constitutes a part of the α exponentiation output, and is input to the next α multiplier 202. alpha multiplier 202, alpha vector value of ^b by multiplying the alpha generates alpha ^{b + 1,} as well as constituting a part of the alpha power output, and inputs to the next alpha multiplier 203. Hereinafter, α is sequentially multiplied by the α multiplier, and the process is repeated until the number of generated α powers is a multiple of the error correction number.

By the way, the content of the logical operation in which the α multiplier multiplies the input by α and converts it into the output is uniquely determined by the field generator polynomial as shown below.

A field generation polynomial "X ³ + X +" which is a Galois field
If α is the root of 1 ”and α is a vector,
It becomes Table 1 shown below.

[0025]

[Table 1] This vector representation is a 3-bit representation consisting of (α ² term, α term, constant term). Then, 1 (= α ⁰ ) shifts to (001), α shifts to (010), and α ² shifts to (100) in sequence, and α ³ = α + 1 by the root of the field generation polynomial.
Therefore, α ³ is (011).

Thus, the power of α is bit-shifted by multiplying by α, and the most significant bit is the constant term and α.
Will be added to the term. That is, the configuration of the alpha multiplier adds the constant term and alpha ² in terms of input and term alpha output, the term alpha input and output of the alpha ² in terms of the input alpha ²
The term of should be the constant term of the output.

Therefore, the α multipliers 202, 203 and 204
Is one adder 210 (exclusive OR circuit)
Can be expressed as shown in FIG. Then, as shown in FIG. 2C, the adder 210 can be configured by a total of three gates of the OR circuit 211, the NAND circuit 212, and the AND circuit 213.

Considering the number of gates required for the α-power generation device in the above configuration, the number of gates of the 1-bit register for holding α-power is “6”, and the gate of the adder is Since the number is “3”, 6 gates × 3 bits + 3 gates × 3 = 27 gates.

As described above, compared with the conventional 72 gates (6 gates × 12 bits), this embodiment has 27 gates, and the number of gates can be greatly reduced.

Further, even when the code generation polynomial is changed, it is necessary to re-input only 3 bits of α ^b which is the minimum root thereof, and the code generation polynomial can be easily changed.

Next, as a second embodiment, a case will be described in which a field generation polynomial is set to "X ⁸ + X ⁴ + X ³ + X ² +1" and a code generation polynomial is generated with an error correction capability of 8 error correction. In this case, when one α-power is expressed as a vector, it becomes 8 bits, and the number of α-powers required becomes 16 which is twice the number of error corrections.

FIG. 3A is a block diagram of an α-power generation device required for generating a code generation polynomial according to the second embodiment, and FIG. 3B is a block diagram of the α multiplier. FIG.

As shown in FIG. 3A, the α exponentiation generating circuit includes an 8-bit register 301 and 15 α multipliers 302 sequentially connected in series to the parallel output of the register 301.
˜316. The α multiplier 30
2 to 316 are α multipliers having the same internal configuration as shown in FIG.

Next, the operation of the α-power generation circuit having the above configuration will be described. First, the vector value of the minimum root (α ^b ) of an arbitrary code generation polynomial is input to the register 301, for example, serially. The vector value of α ^b is output in parallel from the register 301, constitutes a part of the α exponentiation output, and is input to the next α multiplier 302. alpha multiplier 302, alpha vector value of ^b by multiplying the alpha generates alpha ^{b + 1,} as well as constituting a part of the alpha power output, and inputs to the next alpha multiplier 303. Hereinafter, α is sequentially multiplied by the α multiplier, and the process is repeated until the number of generated α powers is a multiple of the error correction number.

In the configuration of the α multiplier at this time, α ⁸ = α ⁴ + α ³ + α ² +1 (3) Equation 3 is established, where α is the root of the field generation polynomial, as in the first embodiment. Therefore, the three adders 210 whose details are shown in FIG. 2C can be represented as shown in FIG. 3B.

Therefore, considering the number of gates in the above configuration, 6 gates × 8 bits + (3 gates × 3) × 15 = 1
83 gates, 768 gates (=
The number of gates is significantly reduced compared to 6 gates × 8 bits × 16).

Further, when changing the generator polynomial, it is necessary to re-input only an arbitrary power of 8 bits of α, which is easier than the conventional re-input of 128 bits (= 8 bits × 16).

Although the preferred embodiment has been described above, this does not limit the present invention. According to the present invention,
Even if an arbitrary irreducible polynomial on a Galois field is selected as the field generator polynomial, when generating an α-power that is its primitive element, it suffices to prepare only one register that stores the minimum root of the code generator polynomial. Since a power of α can be generated by an α multiplier configured only with an adder, the number of gates can be reduced and the code generation polynomial can be easily changed.

[0039]

As described above, according to the present invention, α
When generating a power of, only an arbitrary power of α is held in a register, and based on the value, an additional α power is generated from an α multiplier composed of only an adder. The effect is that the number of gates can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a Reed-Solomon encoding device (a) and a decoding device (b) to which the present invention is applied.

FIG. 2 is a configuration diagram (a) of an α-power generation device and a configuration diagram (b) of an α multiplier when the field generation polynomial “X ³ + X + 1” and the number of error corrections are 2 according to the first embodiment of the present invention. And (c) of the adder.

FIG. 3 is a configuration diagram (a) of an α-power generation device in the case where the number of error corrections is 8 and α multiplication in the field generation polynomial “X ⁸ + X ⁴ + X ³ + X ² +1” according to the second embodiment of the present invention. It is a block diagram (b) of a container.

FIG. 4 is a configuration diagram of a conventional α-power generation device.

[Explanation of symbols]

101 RS encoder 102 α power generation device
104 Syndrome Calculator 105 Euclidean Mutual Operation Operator 106 Chain Search Circuit 107 Delay Circuit 108 Correction Execution Circuit 201
Registers 202, 203, 204 α multiplier
210 adder

Claims (2)

[Claims] 1. In a power generation method of a primitive element α for generating an α power which is a primitive element of a field generator polynomial, an α multiplier composed of only an adder is connected in series by a desired number of stages, and an arbitrary α power is used. (Α ^b ) is input to the α-multiplier of the first stage, and further α-power (α ^{b + 1} ,
α ^{b + 2} , α ^{b + 3} , ...) are sequentially generated and output, and a power generation method of the primitive element α. 2. In a power generation device of a primitive element α for generating an α power which is a primitive element of a field generation polynomial, a storage means for holding any input α power (α ^b ) and an adder only are provided. A plurality of α multipliers each having an output of a preceding stage connected to an input of a subsequent stage, and an input of a first stage of the plurality of α multipliers is connected to an output of the storing means, A power generation device for a primitive element α, which further generates and outputs further powers of α (α ^{b + 1} , α ^{b + 2} , α ^{b + 3} , ...) By an α multiplier of stages.