JPH0918304A - Delay circuit - Google Patents

Abstract

PURPOSE: To provide a delay circuit capable of freely setting resolution and compensating manufacture and temperature dispersion. CONSTITUTION: In first and second delay time compensation parts 22 and 23, delay time generation circuits 221 and 231 are constituted by serially connecting variable delay gates D same as the variable delay gates D used for the paths A11-A14 and B11-B14 of the respective systems of a delay processing part 21 for a number required for delaying clocks f0 and f1 for one cycle and they are arranged closely to the corresponding paths. Then, the clocks f0 and f1 and the delay output of the delay time generation means 221 and 231 are phase- compared, the deviation amount of phases is obtained and delay time control signals CTR1 and CTR2 for correcting the deviation are generated. By the control signals, the variable delay gates D of the delay time generation circuits 221 and 231 and the variable delay gates D of the paths A11-A14 and B11-B14 are simultaneously controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path switching type delay circuit for switching the delay time by selecting one from a plurality of paths having different delay times.

[0002]

2. Description of the Related Art Conventionally, this type of delay circuit is constructed as shown in FIG. This delay circuit includes a selector 11 for connecting the first paths A1 to A4 and the second paths B1 to B4 of each stage.
~ 14 to selectively connect to the final stage paths A4 and B4
Is connected to the input terminal of the OR gate 15.

The input end of the selector 11 is connected to the input terminal IN, and the output end of the OR gate 15 is connected to the output terminal OUT. The first paths A1 to A4 have a delay time T1.
2 ⁿ (n is an integer) of the delay gate D (T1), and the second paths B1 to B4 have delay time T2 (T1> T2) of 2
^{It has n} (n is an integer) delay gate D (T2).

In this example, the numbers of gates of paths A1 to A4 are 1, 2, 1 and 2, and the numbers of gates of paths B1 to B4 are 1, 2, 0 and 0, respectively.

In the configuration of FIG. 4, the signal supplied to the input terminal IN is selectively derived by the selector 11 in the first stage into either the path A1 or the path B1 and input to the selector 12 in the second stage. It Delay gate D of path A1
The delay time T1 of (T1) is the delay gate D of the path B.
It is longer than the delay time T2 of (T2). Therefore, a delay time difference between the delay gate D (T1) and the delay gate D (T2) can be generated in the output of the selector 12 of the second stage according to the selection of the paths A1 and B1.

A signal passing through either path A1 or B1 is selectively derived to either path A2 or B2 by the selector 12 in the second stage and input to the selector 13 in the third stage. The delay time T1 × 2 of the two-stage delay gate D (T1) of the path A2 is equal to the two-stage delay gate D of the path B2.
It is longer than the delay time T2 × 2 of (T2). Therefore, 3
The output of the selector 13 of the first stage includes delay gates D (T1) and delay gates D (T1) of 1 to 3 stages including the delay difference of the outputs of the selector 12 of the second stage, according to the selection of the paths A2 and B2. T
It is possible to cause a delay time difference with 2).

A signal passing through either the path A2 or B2 is selectively derived by the selector 13 in the third stage into either the path A3 or the path B3 and input to the selector 14 in the fourth stage. The path A3 includes the delay gate D (T1), but the path B3 does not include the delay gate. For this reason,
The output of the selector 14 of the fourth stage has delay gates D (T1) corresponding to 1 to 7 stages including the delay difference between the outputs of the selectors 12 and 13 of the second and third stages according to the selection of the paths A3 and B3. And a delay time difference between the delay gate D (T2) can be generated.

A signal passing through either the path A3 or B3 is selectively derived by the selector 14 of the fourth stage into either the path A4 or the path B4 and input to the OR gate 15. The path A4 includes a two-stage delay gate D (T1), but the path B3 does not include a delay gate. Therefore, the output of the OR gate 15 is the selector 1 of the second to fourth stages.
It is possible to cause a delay time difference between the delay gate D (T1) and the delay gate D (T2) for 1 to 15 stages including the delay difference of the outputs of 2 to 14.

Therefore, in the delay circuit having the above configuration, the signal supplied to the input terminal IN is delayed by 1 to 15 stages of the delay gates D (by selecting paths A1 to A4 and B1 to B4 as appropriate. A delay time difference between T1) and the delay gate D (T2) can be given and output from the output terminal OUT.

By the way, since the delay circuit shown in FIG. 4 is a 4-stage path switching system, when the delay time T1 of the delay gate D (T1) is 1, the path A1 selected by the selector 11 of the first stage, The delay time difference of B1 is 1/4, and the delay time difference of the paths A2 and B2 selected by the second-stage selector 7 is 1
/ 2, paths A3, B3 selected by the third-stage selector 13
The delay time difference is 1 and the delay time difference between the paths A4 and B4 selected by the selector 14 of the fourth stage is 2.

The relationship between the delay time of the delay gate D (T1) and the delay time of the delay gate D (T2) is shown in FIG.
If the number of stages in which 1) and D (T2) are used together is generalized as n, the delay gate D (T2) is
It has a delay time of (1-1 / 2 ⁿ ) with respect to the delay time of 1). The delay gate D (T1) and the delay gate D
The delay time difference of (T2) becomes the resolution of the delay circuit.

As described above, in the conventional delay circuit shown in FIG. 4, the selectors 11 to 14 cause the paths A1 to A4 and the path B to pass.
By performing selection control by arbitrarily combining 1 to B4,
The delay time can be changed in a programmable manner.

It should be noted that the above operation is performed by the delay gate D (T
It also holds when the delay time T2 of the delay gate D (T2) is larger than the delay time T1 of 1). If the relationship between the delay times of the delay gate D (T1) and the delay gate D (T2) at this time is generalized as described above, the delay gate D (T
2) is (1+) with respect to the delay time of the delay gate D (T1).
It has a delay time of 1/2 ⁿ ).

However, when the delay circuit based on the conventional path switching system as described above is monolithic, a change in gate delay due to a temperature change and a variation in delay time between manufacturing lots occur. For this reason,
It is impossible to obtain the delay time as designed, and it has been extremely difficult to realize a delay circuit requiring accuracy. Also, once monolithic, it was impossible to change the resolution.

[0015]

In the conventional delay circuit using the path switching method, the change in the gate delay due to the temperature change and the variation in the delay time between the manufacturing lots occur in the monolithic process. Since it is not possible to obtain the exact delay time, it is extremely difficult to realize a highly accurate delay circuit. Also, once monolithic, it was impossible to change the resolution.

An object of the present invention is to provide a delay circuit in which the resolution can be set freely and the delay time can be set with high accuracy by compensating for manufacturing and temperature variations.

[0017]

In order to achieve this object, the present invention provides a plurality of stages each having 2 ⁿ (where n is an integer) and the same number of variable delay gates D in series. A plurality of stages of paths A11 to A14, B11 to B1
4. A delay processing unit 21 including path selecting means 211 to 215 for selectively connecting the plurality of paths of the plurality of stages for each stage to set a delay time, and a delay processing unit 21 provided for each system of the paths, respectively corresponding to each other. A variable delay gate D that is the same as the variable delay gate D used for the system path is connected in series, is arranged in close proximity to that path, and is delayed by one cycle through the input clocks f0 and f1. Phase error detecting means 222, 232 for detecting the input / output phase error of the delay time generating means 221, 231, and control signal generating means for generating the delay time control signals CTR1, CTR2 from the detection results of the phase error detecting means 222, 232. 223 and 233, and the delay time control signal CTR
1. A plurality of delay time compensating units 22 and 23 for simultaneously controlling the delay time of the variable delay gate D used by the CTR 2 together with the internal variable delay gate D for the path of the corresponding system,
A plurality of delay time compensating units 22 from the reference clock f0,
23, and a clock generation unit 24 for generating the respective input clocks f0 and f1 with a constant frequency relationship, and an arbitrary delay time is set by switching the path selection of the delay processing unit 21. To do so.

[0018]

In the delay circuit according to the present invention, the delay processing section 21
The same variable delay gate D is used for the paths A11 to A14 and B11 to B14 of each system, and, for example, the paths A11 to A11 of the system A
The delay time generating means 22 is configured by connecting the same number of variable delay gates D as the variable delay gates D used in A14 in series necessary for delaying the reference clock f0 by one cycle.
1, the path is arranged close to the paths A11 to A14, the reference clock f0 and the output of the delay time generating means 221 are phase-compared to obtain the phase shift amount, and the delay time control signal CTR1 for correcting the shift is generated, With this control signal, the variable delay gate D and the paths A11 to A of the delay time generation means 221 are controlled.
14 variable delay gates D are controlled simultaneously.

Further, the clock generating means 24 causes the clock f1 having a constant frequency relationship from the reference clock f0.
And a variable delay gate D that is the same as the variable delay gate D used in the paths B11 to B14 of the B system are connected in series as delay time generation means 231.
14, the clock f1 and the delay time generation means 2
The output of 31 is compared in phase to obtain a phase shift amount, and a delay time control signal CTR2 for correcting the shift is generated, and this control signal is used to output the variable delay gate D of the delay time generation means 231 and the paths B11 to B14. The variable delay gate D is controlled simultaneously.

Delay time generation means 221 and paths A11 to A
14, the delay time generation means 231 and the paths B11 to B14 are arranged close to each other, and therefore have the same degree of variation, and the same delay time control signals CTR1 and CTR.
Variable delay gate D of the corresponding path using TR2
It is possible to control and compensate for variations in delay time by controlling the. Further, since the difference between the delay time of the variable delay gate D controlled by the delay time compensating unit 22 and the delay time of the variable delay gate D controlled by the delay time compensating unit 23 is compensated for even if there is variation, the resolution is Will be compensated.

Further, by setting the clock f1 generated by the clock generating means 24 to an arbitrary frequency,
The delay time of the variable delay gate D controlled by the delay time compensator 23 can be changed. In other words, the resolution of the delay circuit that is created by the difference between this delay time and the delay time of the variable delay gate D controlled by the delay time compensator 23 can be set arbitrarily.

[0022]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 shows the configuration of a delay circuit according to the 4-stage path switching system according to the present invention. This delay circuit includes a delay processing unit 21 that performs delay processing of an input signal by switching paths between the A system and the B system, and a first delay time that compensates for fluctuations and variations in delay time of a delay gate included in the A system path. A compensating unit 22, a second delay time compensating unit 23 that compensates for fluctuations and variations in the delay time of the delay gate of the B system path, and determines the delay time of the B system path with respect to the A system path. And a PLL (phase locked loop) circuit 24.

The delay processing section 21 includes a first path A1 at each stage.
1 to A14 and the second paths B11 to B14 to the selector 21
1-214 selectively connect to the final stage path A1
4 and B14 are connected to the input terminal of the OR gate 215.

The input end of the selector 211 is connected to the input terminal IN, and the output end of the OR gate 215 is the output terminal OUT.
Connected to. In addition, paths A11 and B11, A12 and B
12, A13 and B13, A14 and B14 have 1
1, 2, 4, and 8 variable delay gates D (all having the same structure) D are interposed in series.

The first delay time compensating unit 22 has the same number of variable delay gates D as the variable delay gates D used in the paths A11 to A14 of the A system, which are required to delay the reference clock f0 by one cycle. Delay time generation circuit 221 connected in series, reference clock f0 and delay time generation circuit 221
The phase comparator (PD) 222 that compares the phase with the reference clock f0 ′ that has been subjected to the delay processing by the low-pass filter (LPF) 223 that passes the low frequency component of the output of the phase comparator 222 to generate a DC voltage signal. With.

The output of the low pass filter 223 is supplied to each variable delay gate D of the delay time generation circuit 221 as the delay time control signal CTR1, and at the same time, the path A11 of the A system.
The variable delay gates D to A14 are also supplied. The delay time generation circuit 221 is the path A1 of the A system of the delay processing unit 21.
1 to A14 are arranged close to each other.

Similarly, the second delay time compensator 23 is
A delay time generation circuit 231 in which the same number of variable delay gates D as the variable delay gates D used in the paths B11 to B14 of the system are connected in series for delaying the reference clock f1 by one cycle, and the reference clock f1. And a phase comparator (PD) 232 for phase comparison between the reference clock f1 ′ delayed by the delay time generation circuit 231 and a low frequency component of the output of the phase comparator 232 to generate a DC voltage signal. And a low pass filter (LPF) 233.

The output of the low pass filter 233 is supplied to each variable delay gate D of the delay time generation circuit 231 as a delay time control signal CTR2, and at the same time, the B path B11.
The variable delay gates D to B14 are also supplied. The delay time generation circuit 231 is a path B1 of the B system of the delay processing unit 21.
1 to B14 are arranged close to each other.

The number of variable delay gates of the delay time generating circuit 221 of the first delay time compensating unit 22 and the number of variable delay gates of the delay time generating circuit 231 of the second delay time compensating unit 23 are the same.

The PLL circuit 24 generates the reference clock f1 from the reference clock f0, and is specifically constructed as shown in FIG.

In FIG. 2, the reference clock f0 is frequency-divided by a frequency divider (1 / X) 241 and the output clock f1 is frequency-divided by a frequency divider (1 / Y) 242 together with a phase comparator ( PD) 243. This phase comparator 2
Reference numeral 43 compares the phases of both inputs and outputs the phase error signal. This phase error signal is a low-pass filter (L
After being converted into a DC voltage signal by the PF) 244, the amplifier 2
It is amplified by 45 and supplied to the voltage controlled oscillator (VCO) 246 as a voltage control signal.

The voltage controlled oscillator 246 generates a clock f1 having a frequency corresponding to the control voltage signal. The clock f1 is supplied to the frequency divider 242 described above, and at the same time, the second delay time as the output clock f1. Compensation unit 2
3 is supplied.

The operation of the above arrangement will be described below. First, in the PLL circuit 24, the input reference clock f0 is frequency-divided by the frequency divider 241 and the signal obtained by frequency-dividing the output clock f1 by the frequency divider 242 is compared in phase by the phase comparator 243. Here, nothing is output when the phases of both are in phase, but if they are out of phase, a phase error signal corresponding to the phase is output.

This phase error signal is passed through the low pass filter 24.
At 4, only the low frequency part is extracted and converted into a DC voltage signal. This signal is amplified by the amplifier 245, and the voltage-controlled oscillator 246 is oscillated by the amplified signal. The oscillation frequency of the voltage controlled oscillator 246 is the output clock f1 of the PLL circuit 24. As described above, the output clock f1 is frequency-divided by the frequency divider 242 and supplied to the phase comparator 243.

By the above operation, the input / output of the PLL circuit 24 is controlled so that f0 / X = f1 / Y (1). Therefore, the output f1 of the PLL circuit 24 is fixed at a frequency Y / X times that of the input f0.

On the other hand, the delay processing section 21 has almost the same structure as the conventional delay circuit of FIG. 4, but the delay time of each stage is controlled by the first delay time compensating section 22 until the final stage. The delay processing is performed by using the delay time difference between D and the variable delay gate D controlled by the second delay time compensating unit 23.

Next, the delay time generation circuit 221 of the first delay time compensator 22 is designed to have a delay time of one cycle of the reference clock f0. The delay time generation circuit 231 of the second delay time compensation unit 23 is designed to have a delay time of one cycle of the clock f1 obtained by converting the reference clock f0 by the PLL circuit 24.

Actually, the delay time of the delay time generation circuits 221 and 231 with respect to the design value varies with temperature,
There are variations, so it is necessary to compensate. Therefore, the reference clock f0 is input to the delay time generation circuit 221 to set 1
The phase is delayed by the period and the phase of its output and input is compared by the phase comparator 2.
Compare with 22. Here, the phase comparator 222 outputs nothing if the phases of the two are matched, but if the phases are shifted, the phase error signal corresponding to the shifted amount is output to the low-pass filter 223.

The low-pass filter 223 comprises the phase comparator 2
The output from 22 is converted into a DC voltage signal by passing only the low frequency part. This signal controls each variable delay gate D of the delay time generation circuit 221 as the delay time control signal CTR1. That is, the delay time generation circuit 221
The delay time of each gate delay time is the delay time control signal C
It is controlled by TR1 and is adjusted to a delay time of one cycle of the reference clock f0 as a whole.

This delay time generation circuit 221 is arranged in the vicinity of the paths A11 to A14 of the A system of the delay processing section 21, and the delay time control signal CTR1 output from the low pass filter 223 is set to each variable delay gate of the paths A11 to A14. Distribute and supply to D. In this case, since the delay time generation circuit 221 and the paths A11 to A14 are arranged close to each other, their variations are about the same.

Therefore, by controlling the variable delay gates D of the paths A11 to A14 using the same delay time control signal CTR1, the delay time can always be adjusted to the design value regardless of temperature changes and variations.

Similarly, also in the second delay time compensating section 23, the clock f1 is input to the delay time generating circuit 231 and delayed by one cycle, and the output and the input phase are compared by the phase comparator 232. A phase error signal is generated, converted into a DC voltage signal by the low pass filter 233, and each variable delay gate D of the delay time generation circuit 231 is controlled as the delay time control signal CTR2.

That is, the delay time of the delay time generation circuit 231 is such that each gate delay time is the delay time control signal CTR2.
And is adjusted to a delay time of one cycle of the clock f1 as a whole.

This delay time generation circuit 231 is arranged in the vicinity of the B system paths B11 to B14, and the low pass filter 2
The delay time control signal CTR2 output from 33 is passed to path B
The variable delay gates 11 to B14 are distributed and supplied. In this case, the delay time generation circuit 231 and the paths B11 to B14
Since and are arranged close to each other, their variations are about the same.

Therefore, by controlling the variable delay gates D of the paths B11 to B14 using the same delay time control signal CTR2, the delay time can always be adjusted to the design value regardless of temperature changes and variations.

The resolution of this delay circuit is variable for one stage of the variable delay gate D controlled by the first delay time compensating unit 22 and for one stage controlled by the second delay time compensating unit 23. This is the difference in delay time of the delay gate D. Since each is compensated for manufacturing and temperature variations, the resolution is compensated.

Here, the first and second delay time compensating units 2
When the number of stages of the variable delay gates D of 2 and 23 is N, the first
The delay time of the variable delay gate D for one stage of the delay time compensating unit 22 is (1 / f0 * 1 / N), and the delay time of the variable delay gate D for one stage of the second delay time compensating unit 23 is Is (1 / f1 * 1 / N). From this, the resolution φ of the delay circuit is φ = (1 / f0 * 1 / N) − (1 / f1 * 1 / N) = (1-X / Y) * (1 / It can be seen that f0 * 1 / N) (2). Therefore, the frequency divider 24 of the PLL 24
The resolution can be freely changed by setting 1 and 242 arbitrarily.

In order to delay the signal input to the delay processing section 21 by an arbitrary time, the selectors 211 to 2 of the respective stages are provided.
At 14, appropriate paths A11 to A14 and B11 to B14 are selected. The delay time of the variable delay gate D in each stage is automatically adjusted by the delay time control signals CTR1 and CTR2. Therefore, the output signal of the delay processing unit 21 is a signal delayed with extremely high accuracy.

Therefore, the delay circuit having the above configuration is
The resolution can be freely set, and the delay time with high accuracy can be set by compensating for manufacturing and temperature variations. In the embodiment of FIG. 1, the number of selector stages in the delay processing unit 21 and the number of variable delay gates in each stage can be increased or decreased as necessary.

FIG. 3 shows the configuration of another embodiment of the delay circuit according to the present invention. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the delay circuit shown in FIG. 3, as apparent from comparison with FIG. 1, the path selection configuration of the delay processing unit 21 is different. That is, in the delay processing unit 21, the paths A11 to
2 inputs and 2 outputs structure (2
Selectors 216 to 21 for outputting one of two input terminals)
A selector 219 having a structure of 8 and 1 input and 1 output is used.

In FIG. 3, the input signal supplied to the input terminal IN is directly input to the selector 216 through both paths A11 and B11, and one of the signals is selected and output to both the paths A12 and B12. To be done.

Similarly, the transmission signals of the paths A12 and B12 are input to the selector 217, one of the signals is selected and output to both the paths A13 and B13, and the path A1 is selected.
The transmission signals of 3 and B13 are input to the selector 218, one of the signals is selected and output to both the paths A14 and B14, and the transmission signals of the paths A14 and B14 are input to the selector 219 and either one of them is selected. The signal is selected and output to the output terminal OUT.

Even with such a structure, the variable delay gate D of the paths A11 to A14 is exactly the same as the embodiment shown in FIG.
Of the variable delay gate D of the paths B11 to B14 is compensated by the delay time control signal CTR2 from the second delay time compensating unit 23 by the delay time control signal CTR1 from the first delay time compensating unit 22. be able to. Further, the delay time difference of one stage of the variable delay gates D of the delay time generation circuits 221 and 231 which is the resolution of the delay circuit can be compensated for manufacturing and temperature variations.

In the above embodiment, as in the previous embodiment, the number of selector stages in the delay processing section 21 and the number of variable delay gates in each stage can be increased or decreased as necessary. Also,
In each of the embodiments, there are two paths, but more paths may be used. In this case, a delay time compensating unit is provided for each system, and the input clock of each delay time compensating unit is PLL.
If the circuit is configured to generate from the reference clock, the same effect can be obtained. Needless to say, various modifications are included in the present invention.

[0055]

As described above, according to the present invention, it is possible to provide a delay circuit in which the resolution can be freely set and which compensates for manufacturing and temperature variations to generate a highly accurate delay time. .

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a delay circuit according to the present invention.

FIG. 2 is a block circuit diagram showing a specific configuration of the PLL circuit shown in FIG.

FIG. 3 is a block circuit diagram showing the configuration of another embodiment of the delay circuit according to the present invention.

FIG. 4 is a block circuit diagram showing a configuration of a delay circuit according to a conventional path switching method.

[Explanation of symbols]

 11-14 Selector 15 OR gate 21 Delay processing part 211-214 Selector 215 OR gate 216-219 Selector 22 First delay time compensating part 221 Delay time generating circuit 222 Phase comparator (PD) 223 Low pass filter (LPF) 23th 2 delay time compensator 231 delay time generation circuit 232 phase comparator (PD) 233 low pass filter (LPF) 24 PLL circuit 241, 242 frequency divider 243 phase comparator (PD) 244 low pass filter (LPF) 245 amplifier 246 voltage Controlled oscillator (VCO) IN input terminal OUT output terminal f0, f0 ', f1, f1' clock A1 to A4, B1 to B4 paths A11 to A14, B11 to B14 paths

Claims (4)

[Claims] 1. A plurality of stages of paths (A11, A12, A13, each of which has 2 ⁿ (where n is an integer) and each system has the same number of variable delay gates (D) in series. A14, B11, B12, B1
3, B14), path selecting means (211, 212, 2) for selectively connecting the plurality of paths of a plurality of stages for each stage to set a delay time.
13,214,215) and a delay processing unit (21) provided for each path system, and the variable delay gates (D) and the same variable delay gates (D) used for the paths of the corresponding systems are connected in series, A delay time generation means (221,231) which is arranged close to the path and delays by one cycle through the input clock (f0, f1), and this delay time generation means (221,231)
Phase error detection means (222, 2
32) is provided with control signal generation means (223, 233) for generating a delay time control signal (CTR1, CTR2) from the detection result of the phase error detection means (222, 232), and the delay time control signal (CTR1, CT
R2) includes a plurality of delay time compensators (22, 23) that simultaneously control the delay time of the variable delay gate (D) used for the path of the corresponding system together with the internal variable delay gate (D), and the reference clock (f0). To the plurality of delay time compensation units (22,2
The clock generator (24) for generating the input clock (f0, f1) of 3) with a constant frequency relationship is provided, and an arbitrary delay time is set by switching the path selection of the delay processor (21). A delay circuit characterized by the above. 2. The path selection means (2) according to claim 1,
11,212,213,214) is a delay circuit characterized by being a selector. 3. The delay circuit according to claim 1, wherein the phase error detecting means (222, 232) is a phase comparator, and the control signal generating means (223, 233) is a low pass filter. 4. The clock generation unit according to claim 1.
(24) is the first frequency divider (24
1) and a second frequency divider (242) that divides the output clock (f1)
And a phase comparator (243) for phase-comparing the outputs of the first and second frequency dividers to obtain a phase error signal, and the output clock (f1) generated from the phase comparator (243). A phase locked loop circuit comprising a clock generating means (244, 245, 246) for controlling the frequency so that there is no phase error signal to be output, wherein the frequency division ratio of each of the first and second frequency dividers (241, 242) A delay circuit characterized in that the delay time resolution of the delay processing section (21) is determined.