JPH0918247A - High frequency amplifier device - Google Patents

High frequency amplifier device

Info

Publication number
JPH0918247A
JPH0918247A JP18222795A JP18222795A JPH0918247A JP H0918247 A JPH0918247 A JP H0918247A JP 18222795 A JP18222795 A JP 18222795A JP 18222795 A JP18222795 A JP 18222795A JP H0918247 A JPH0918247 A JP H0918247A
Authority
JP
Japan
Prior art keywords
signal
envelope signal
input
digital
modulated wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18222795A
Other languages
Japanese (ja)
Inventor
Akira Yamaguchi
陽 山口
Tadao Nakagawa
匡夫 中川
Masahiro Muraguchi
正弘 村口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP18222795A priority Critical patent/JPH0918247A/en
Publication of JPH0918247A publication Critical patent/JPH0918247A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To linearly amplify a digital signal with high efficiency for adjustment of a limited-band phase, etc., by controlling the output level of an amplifier circuit by means of an envelope signal. CONSTITUTION: The modulated wave inputted from an input terminal 9 is inputted to an amplifier means 5 and amplified there after undergoing the adjustment of its phase via a phase adjustment means 3. At the same time, the input modulated wave is also supplied to an envelope signal detection means 2 via the means 1 which detects an envelope signal out of the modulated wave and inputs it to a control voltage generation means 6. The envelope signal inputted to the means 6 is converted into a digital signal by an A/D conversion means 6a, and the output control voltage is generated by a D/A conversion means 6c via a storage means 6b and inputted to the means 5. The output control voltage is applied to a gate G of a gate-grounded FET 5c. Then the distribution of drain bias given from a DC power supply 4 of a grounded-source FET 5b and the FET 5c is changed, and the output of the means 5 is controlled according to the envelope signal. Thus the digital signal can be linearly amplified with high efficiency.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高周波通信装置に用いる
高周波増幅装置に関し、特に帯域制限されたデジタル信
号の高周波増幅を行う高周波増幅装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency amplifier used in a high frequency communication device, and more particularly to a high frequency amplifier for high frequency amplification of a band-limited digital signal.

【0002】[0002]

【従来の技術】図7は従来の高周波増幅装置の構成を示
すブロック図である。同図において、101は信号分配
手段、102は包絡線信号検出手段、104はドレイン
バイアス用直流電源、105は増幅手段、105aは入
力回路、105bはソース接地FET、105dは出力
回路、106は非線形制御回路、108は直流電圧及び
電流変換手段、109は入力端子、110は出力端子を
示す。
2. Description of the Related Art FIG. 7 is a block diagram showing the structure of a conventional high frequency amplifier. In the figure, 101 is a signal distributing means, 102 is an envelope signal detecting means, 104 is a DC power source for drain bias, 105 is an amplifying means, 105a is an input circuit, 105b is a source grounded FET, 105d is an output circuit, and 106 is non-linear. A control circuit, 108 is a DC voltage and current converting means, 109 is an input terminal, and 110 is an output terminal.

【0003】次に、図7に示す従来の高周波増幅装置の
動作を説明する。増幅手段105の出力を制御するため
にソース接地FET105bのドレインバイアスを変化
させていた。このようにドレインバイアスを制御するた
めには、大電流を供給でき、かつ出力可変の直流電圧及
び電流変換手段が必要となる。このため、総合効率で
は、大きな改善手段とはならなかった。例えば、直流電
圧及び電流変換手段としては出力可変DC−DCコンバ
ータがあるが、増幅器の効率が50%、出力可変DC−
DCコンバータの電力変換効率が70%と、ともに高効
率のものを利用したとしても、総合効率は35%とな
る。
Next, the operation of the conventional high frequency amplifier shown in FIG. 7 will be described. In order to control the output of the amplification means 105, the drain bias of the source-grounded FET 105b is changed. In order to control the drain bias in this way, a DC voltage and current converting means capable of supplying a large current and having a variable output is required. For this reason, overall efficiency did not become a major improvement measure. For example, there is an output variable DC-DC converter as the DC voltage and current converting means, but the efficiency of the amplifier is 50%, and the output variable DC-DC converter is
The power conversion efficiency of the DC converter is 70%, and even if both of them are highly efficient, the total efficiency is 35%.

【0004】また、DC−DCコンバータは、トラン
ス、キャパシタ等のハイブリッド部品を必要とするた
め、これが小型化の障害となっていた。
Further, the DC-DC converter requires hybrid parts such as a transformer and a capacitor, which has been an obstacle to miniaturization.

【0005】この問題点を克服するための別の従来の高
周波増幅装置の構成を図8に示す。同図において、20
1は信号分配手段、202は包絡線信号検出手段、20
4はドレインバイアス用直流電源、205は増幅手段、
205aは入力回路、205bはソース接地FET、2
05cはゲート接地FET、205dは出力回路、20
6はレベル変換手段、209は入力端子、210は出力
端子を示す。そして、レベル変換手段206の出力をゲ
ート接地FET205cのゲートに与えてソース接地F
ET205bとゲート接地FET205cのバイアス配
分を変化させることにより、増幅手段205の出力レベ
ルを制御していた。このため、出力の制御信号は電圧の
みでよく、直流電圧及び電流変換手段を削除することが
可能であった。
FIG. 8 shows the structure of another conventional high-frequency amplifier for overcoming this problem. In FIG.
1 is signal distribution means, 202 is envelope signal detection means, 20
4 is a DC power supply for drain bias, 205 is an amplifying means,
205a is an input circuit, 205b is a common source FET, 2
05c is a grounded-gate FET, 205d is an output circuit, 20
6 is a level converting means, 209 is an input terminal, and 210 is an output terminal. Then, the output of the level converting means 206 is given to the gate of the gate-grounded FET 205c to supply the source-grounded F
The output level of the amplifying means 205 is controlled by changing the bias distribution between the ET 205b and the grounded-gate FET 205c. Therefore, the output control signal need only be the voltage, and the DC voltage and current conversion means could be eliminated.

【0006】上記出力制御を行うために必要な制御電圧
の特性例を図9に示す。また、包絡線信号検出手段から
出力される包絡線信号の特性例を図10に示す。この増
幅器を線形に制御するためには、包絡線信号を10mV
以下の精度で制御電圧レベルに変換する必要がある。こ
のため、十分な線形性が得られていなかった。
FIG. 9 shows a characteristic example of the control voltage necessary for performing the above output control. Further, FIG. 10 shows a characteristic example of the envelope signal output from the envelope signal detecting means. In order to control this amplifier linearly, the envelope signal should be 10 mV.
It is necessary to convert to the control voltage level with the following accuracy. Therefore, sufficient linearity has not been obtained.

【0007】また、出力制御信号が増幅手段に供給され
る時刻と増幅される変調波が増幅手段に供給される時刻
との間に時間的な差が生じるため、線形性が低下してい
た。
Further, since there is a time difference between the time when the output control signal is supplied to the amplifying means and the time when the modulated wave to be amplified is supplied to the amplifying means, the linearity is deteriorated.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、第1の
従来の高周波増幅装置では、増幅手段の出力を制御させ
るために、大電流を供給でき、かつ出力可変の直流電圧
及び電流変換手段が必要となる。このため、総合効率で
は、大きな改善手段とはならなかった。また、第2の従
来の高周波増幅装置では、直流電圧及び電流変換手段を
用いずに増幅手段を出力制御することが可能であった
が、その線形性は十分ではなかった。
However, in the first conventional high frequency amplifying apparatus, in order to control the output of the amplifying means, a large current can be supplied and a variable output DC voltage and current converting means is required. Become. For this reason, overall efficiency did not become a major improvement measure. Further, in the second conventional high frequency amplifying device, the output of the amplifying means can be controlled without using the DC voltage and current converting means, but its linearity is not sufficient.

【0009】本発明はこれらの問題点を解決するための
もので、帯域制限された位相変調等のデジタル信号を高
効率かつ線形に増幅することが可能で、デジタル方式の
携帯機の通話時間の延長が可能となる高周波増幅装置を
提供することを目的とする。
The present invention is intended to solve these problems, and is capable of linearly amplifying a digital signal such as band-limited phase modulation with high efficiency and reducing the call time of a digital portable device. It is an object of the present invention to provide a high frequency amplification device that can be extended.

【0010】[0010]

【課題を解決するための手段】本発明は前記問題点を解
決するために、高周波を分配する信号分配手段と、該信
号分配手段により分配された一方の変調波の位相を調整
する位相調整手段と、位相調整された変調波を入力信号
とする増幅手段と、前記信号分配手段により分配された
他方の変調波の包絡線信号を検出する包絡線信号検出手
段と、該包絡線信号検出手段により検出した包絡線信号
をデジタル信号に変換するアナログ−デジタル変換手
段、デジタル信号をアナログ電圧に変換するデジタル−
アナログ変換手段、及び前記アナログ−デジタル変換手
段と前記デジタル−アナログ変換手段を結ぶ記憶手段か
らなる制御電圧生成手段とからなり、前記増幅手段を、
ソース接地FETのドレイン端子とゲート接地FETの
ソース端子を互いに直接接続したカスコード増幅素子か
らなる増幅回路で構成したことに特徴がある。
In order to solve the above problems, the present invention provides a signal distribution means for distributing high frequency waves and a phase adjusting means for adjusting the phase of one modulated wave distributed by the signal distribution means. An amplifying means that uses the phase-adjusted modulated wave as an input signal, an envelope signal detecting means that detects an envelope signal of the other modulating wave distributed by the signal distributing means, and an envelope signal detecting means. An analog-to-digital conversion means for converting the detected envelope signal into a digital signal, a digital-to-digital converter for converting the digital signal into an analog voltage.
The control circuit includes analog conversion means and control voltage generation means including storage means that connects the analog-digital conversion means and the digital-analog conversion means.
It is characterized in that the drain terminal of the source-grounded FET and the source terminal of the gate-grounded FET are directly connected to each other by an amplification circuit including a cascode amplification element.

【0011】また、前記位相調整手段を、包絡線信号検
出手段の直前に、又は記憶手段の直前又は直後に、更に
制御電圧生成手段の直前又は直後に設置することによ
り、位相調整をアナログ信号である変調波に対して行う
のではなく、デジタル信号である記憶手段の入力信号ま
たは出力信号に対して行うようにした。
Further, the phase adjustment means is installed immediately before the envelope signal detection means, or immediately before or after the storage means, and immediately before or after the control voltage generation means, so that the phase adjustment is performed by an analog signal. Instead of performing it on a certain modulated wave, it is performed on the input signal or output signal of the storage means which is a digital signal.

【0012】[0012]

【作用】このような構成を有する本発明によれば、前記
制御電圧生成手段の出力を前記ゲート接地FETのゲー
トに与えて前記ソース接地FETと前記ゲート接地FE
Tのバイアス配分を変化させることにより、前記包絡線
信号に従って前記増幅回路の出力レベルを制御する。
According to the present invention having such a configuration, the output of the control voltage generating means is applied to the gate of the gate-grounded FET to supply the source-grounded FET and the gate-grounded FE.
By changing the bias distribution of T, the output level of the amplifier circuit is controlled according to the envelope signal.

【0013】よって、本発明の高周波増幅装置では、レ
ベル変換によって制御電圧を得るのではなく、前記制御
電圧生成手段によって制御電圧を生成するため、従来よ
りも精度の良い出力制御が可能となった。また、前記位
相調整手段によって出力制御信号が増幅手段に供給され
る時刻と増幅される変調波が増幅手段に供給される時刻
との間に時間的な差を解消し、一層の線形化を達成し
た。
Therefore, in the high frequency amplifying apparatus of the present invention, the control voltage is generated by the control voltage generating means instead of obtaining the control voltage by level conversion, so that the output control can be performed with higher accuracy than in the past. . Further, the time difference between the time when the output control signal is supplied to the amplifying means and the time when the modulated wave to be amplified is supplied to the amplifying means is eliminated by the phase adjusting means, and further linearization is achieved. did.

【0014】したがって、本発明は前記問題点を解決で
き、帯域制限された位相変調等のデジタル信号を高効率
かつ線形に増幅することが可能で、デジタル方式の携帯
機の通話時間の延長が可能となる高周波増幅装置を提供
できる。
Therefore, the present invention can solve the above-mentioned problems, can highly efficiently and linearly amplify a band-limited digital signal such as phase modulation, and can extend the talk time of a digital portable device. It is possible to provide a high-frequency amplification device that becomes

【0015】[0015]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1は本発明の第1の実施例の構成を示すブロッ
ク図である。本実施例は信号分配手段1、包絡線信号検
出手段2、位相調整手段3、直流電源4、並びに、アナ
ログ−デジタル変換手段6a及び記憶手段6b及びデジ
タル−アナログ変換手段6cからなる制御電圧生成手段
6、並びに、ソース接地FET5bのドレイン端子とゲ
ート接地FET5cのソース端子を互いに直接接続した
カスコード増幅素子を用い入力回路5a及び出力回路5
dを有する増幅手段5で構成されている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In this embodiment, a signal distribution unit 1, an envelope signal detection unit 2, a phase adjustment unit 3, a DC power supply 4, and a control voltage generation unit including an analog-digital conversion unit 6a, a storage unit 6b, and a digital-analog conversion unit 6c. 6, and the input circuit 5a and the output circuit 5 using a cascode amplifier element in which the drain terminal of the source-grounded FET 5b and the source terminal of the gate-grounded FET 5c are directly connected to each other.
It is composed of amplification means 5 having d.

【0016】また、同図において、9は入力端子、10
は出力端子を示す。信号分配手段1は変調波を分配する
機能を有しており、簡易な方法ではキャパシタによる容
量性結合で信号を分配することが可能である。
In the figure, 9 is an input terminal and 10 is
Indicates an output terminal. The signal distribution unit 1 has a function of distributing the modulated wave, and can distribute the signal by capacitive coupling with a capacitor by a simple method.

【0017】次に、本実施例に示した装置の動作につい
て説明する。直流電源4は、増幅手段5にドレインバイ
アスを供給する。入力端子9から入力された変調波は、
位相調整手段3で位相調整されたのち増幅手段5に入力
されて増幅される。このとき、変調波の一部は、位相調
整手段3に入力される前に信号分配手段1によって包絡
線信号検出手段2に供給される。包絡線信号検出手段2
では、供給された変調波から包絡線信号を検出する。制
御電圧生成手段6は、入力された包絡線信号に応じて出
力制御電圧を生成する。増幅手段5は、出力制御電圧に
よって出力制御を行い、高効率かつ線形な増幅装置とし
て動作する。
Next, the operation of the apparatus shown in this embodiment will be described. The DC power supply 4 supplies a drain bias to the amplification means 5. The modulated wave input from the input terminal 9 is
The phase is adjusted by the phase adjusting means 3 and then input to the amplifying means 5 and amplified. At this time, a part of the modulated wave is supplied to the envelope signal detecting means 2 by the signal distributing means 1 before being input to the phase adjusting means 3. Envelope signal detection means 2
Then, the envelope signal is detected from the supplied modulated wave. The control voltage generation means 6 generates an output control voltage according to the input envelope signal. The amplifying means 5 controls the output by the output control voltage and operates as a highly efficient and linear amplifying device.

【0018】なお、制御電圧生成手段6の動作は以下の
通りである。包絡線信号は、アナログ−デジタル変換手
段6aによってデジタル信号に変換される。記憶手段6
bは、アナログ−デジタル変換手段6aから供給された
信号に応じてデジタル−アナログ変換手段6cへデジタ
ル信号を送る。デジタル−アナログ変換手段6cは、記
憶手段6bから受けた信号に従って出力制御電圧を生成
する。
The operation of the control voltage generating means 6 is as follows. The envelope signal is converted into a digital signal by the analog-digital conversion means 6a. Storage means 6
b sends a digital signal to the digital-analog conversion means 6c according to the signal supplied from the analog-digital conversion means 6a. Digital-analog conversion means 6c generates an output control voltage according to the signal received from storage means 6b.

【0019】図2は本発明の第2の実施例の構成を示す
ブロック図である。本実施例は、第1の実施例におい
て、位相調整手段3を制御電圧生成手段6の直前ではな
く、包絡線信号検出手段2の直前に配置したものであ
る。これによって、主信号路ではなく制御系路に置いて
位相調整を行う。
FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. In this embodiment, the phase adjusting means 3 is arranged immediately before the envelope voltage detecting means 2 instead of immediately before the control voltage generating means 6 in the first embodiment. As a result, the phase adjustment is performed by placing the control system path instead of the main signal path.

【0020】図3は本発明の第3の実施例の構成を示す
ブロック図である。本実施例は、第1の実施例におい
て、位相調整手段3を位相調整手段33で置き換えたも
のである。これによって、デジタル的に位相調整を行
う。
FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention. In this embodiment, the phase adjusting means 3 is replaced with the phase adjusting means 33 in the first embodiment. By this, the phase is adjusted digitally.

【0021】図4は本発明の第4の実施例の構成をブロ
ック図である。本実施例は、第1の実施例において、位
相調整手段3を位相調整手段43で置き換えたものであ
る。これによって、包絡線信号周波数で位相調整を行
う。
FIG. 4 is a block diagram showing the configuration of the fourth embodiment of the present invention. In this embodiment, the phase adjusting means 3 is replaced with the phase adjusting means 43 in the first embodiment. As a result, phase adjustment is performed at the envelope signal frequency.

【0022】ここで、カスコード増幅素子のゲート接地
FETのゲートバイアスVcを変化させ、これによって
飽和出力を変化させたときの、当該増幅素子からなるA
B級増幅器の出力及び効率の変化の例を図5に細線に示
し、かつ各本実施例の増幅器の出力及び効率の特性の例
を図5に太線に示す。同図からわかるように、各本実施
例の増幅器は、効率の高い領域においても線形動作をし
ている。
Here, when the gate bias Vc of the grounded-gate FET of the cascode amplification element is changed and the saturation output is changed by this, the A formed by the amplification element concerned is changed.
An example of changes in the output and efficiency of the class B amplifier is shown by a thin line in FIG. 5, and an example of characteristics of the output and efficiency of the amplifier of each of the present embodiments is shown by a thick line in FIG. As can be seen from the figure, the amplifier of each of the present embodiments operates linearly even in the high efficiency region.

【0023】また、カスコード増幅素子からなるAB級
増幅器の出力信号のスペクトラムの例を図6中の(a)
として、かつ各本実施例の増幅器の出力信号のスペクト
ラムの例を図6中の(b)として示す。(b)は(a)
と比較するとサイドローブの抑圧比が大きいことが確認
できる。
An example of the spectrum of the output signal of the class AB amplifier composed of the cascode amplifying element is shown in FIG. 6 (a).
Further, an example of the spectrum of the output signal of the amplifier of each embodiment is shown as (b) in FIG. (B) is (a)
It can be confirmed that the suppression ratio of the side lobe is large as compared with.

【0024】[0024]

【発明の効果】以上説明したように、本発明によれば、
帯域制限された位相変調等のデジタル信号を高効率かつ
線形に増幅することが可能で、デジタル方式の携帯機の
通話時間の延長が可能となる。
As described above, according to the present invention,
It is possible to amplify a band-limited digital signal such as phase modulation with high efficiency and linearly, and it is possible to extend the call time of a digital portable device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の構成を示すブロック図
である。
FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

【図2】本発明の第2の実施例の構成を示すブロック図
である。
FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

【図3】本発明の第3の実施例の構成を示すブロック図
である。
FIG. 3 is a block diagram illustrating a configuration of a third exemplary embodiment of the present invention.

【図4】本発明の第4の実施例の構成を示すブロック図
である。
FIG. 4 is a block diagram showing a configuration of a fourth embodiment of the present invention.

【図5】カスコード増幅素子を用いたAB級増幅器の出
力及び効率の制御電圧依存性の例並びに本発明による増
幅器の出力及び効率の特性例を示す図である。
FIG. 5 is a diagram showing an example of control voltage dependence of output and efficiency of a class AB amplifier using a cascode amplifying element and output and efficiency characteristics of an amplifier according to the present invention.

【図6】カスコード増幅素子を用いたAB級増幅器によ
って変調波を増幅した場合の出力信号のスペクトラムの
例及び前記増幅器と同じ動作点における本増幅器の出力
信号のスペクトラムの例を示す図である。
FIG. 6 is a diagram showing an example of a spectrum of an output signal when a modulated wave is amplified by a class AB amplifier using a cascode amplification element and an example of a spectrum of an output signal of the present amplifier at the same operating point as the amplifier.

【図7】従来の高周波増幅装置を示すブロック図であ
る。
FIG. 7 is a block diagram showing a conventional high frequency amplifier.

【図8】別の従来の高周波増幅装置を示すブロック図で
ある。
FIG. 8 is a block diagram showing another conventional high frequency amplifier.

【図9】増幅器を線形制御するために必要な出力制御電
圧の例を示す図である。
FIG. 9 is a diagram showing an example of an output control voltage required for linearly controlling an amplifier.

【図10】包絡線信号検出手段から出力される包絡線信
号の例を示す図である。
FIG. 10 is a diagram showing an example of an envelope signal output from an envelope signal detecting means.

【符号の説明】[Explanation of symbols]

1、101、201 信号分配手段 2、102、202 包絡線信号検出手段 3、33、43 位相調整手段 4、104、204 直流電源 5、105、205 増幅手段 5a、105a、205a 入力回路 5b、5c、105b、205b、205c FET 5d、105d、205d 出力回路 6 制御電圧生成手段 6a アナログ−デジタル変換手段 6b 記憶手段 6c デジタル−アナログ変換手段 9、109、209 入力端子 10、110、210 出力端子 106 非線形制御回路 108 直流電圧及び電流変換手段 206 レベル変換手段 1, 101, 201 Signal distribution means 2, 102, 202 Envelope signal detection means 3, 33, 43 Phase adjustment means 4, 104, 204 DC power supply 5, 105, 205 Amplification means 5a, 105a, 205a Input circuit 5b, 5c , 105b, 205b, 205c FETs 5d, 105d, 205d Output circuit 6 Control voltage generation means 6a Analog-digital conversion means 6b Storage means 6c Digital-analog conversion means 9, 109, 209 Input terminal 10, 110, 210 Output terminal 106 Non-linear Control circuit 108 DC voltage and current conversion means 206 Level conversion means

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 高周波を分配する信号分配手段と、 該信号分配手段により分配された一方の変調波の位相を
調整する位相調整手段と、 位相調整された変調波を入力信号とする増幅手段と、 前記信号分配手段により分配された他方の変調波の包絡
線信号を検出する包絡線信号検出手段と、 該包絡線信号検出手段により検出した包絡線信号をデジ
タル信号に変換するアナログ−デジタル変換手段、デジ
タル信号をアナログ電圧に変換するデジタル−アナログ
変換手段、及び前記アナログ−デジタル変換手段と前記
デジタル−アナログ変換手段を結ぶ記憶手段からなる制
御電圧生成手段とからなり、 前記増幅手段を、ソース接地FETのドレイン端子とゲ
ート接地FETのソース端子を互いに直接接続したカス
コード増幅素子からなる増幅回路で構成し、 前記制御電圧生成手段の出力を前記ゲート接地FETの
ゲートに与えて前記ソース接地FETと前記ゲート接地
FETのバイアス配分を変化させることにより、前記包
絡線信号に従って前記増幅回路の出力レベルを制御する
ことを特徴とする高周波増幅装置。
1. A signal distribution means for distributing a high frequency wave, a phase adjustment means for adjusting the phase of one of the modulated waves distributed by the signal distribution means, and an amplification means for using the phase adjusted modulated wave as an input signal. An envelope signal detecting means for detecting an envelope signal of the other modulated wave distributed by the signal distributing means, and an analog-digital converting means for converting the envelope signal detected by the envelope signal detecting means into a digital signal. A digital-analog conversion means for converting a digital signal into an analog voltage, and a control voltage generation means composed of a storage means connecting the analog-digital conversion means and the digital-analog conversion means. An amplifier circuit consisting of a cascode amplifier element in which the drain terminal of the FET and the source terminal of the gate-grounded FET are directly connected to each other. The output of the control voltage generation means is applied to the gate of the common-gate FET to change the bias distribution of the common-source FET and the common-gate FET, thereby changing the output level of the amplifier circuit according to the envelope signal. A high frequency amplifying device characterized by being controlled.
【請求項2】 前記位相調整手段を前記包絡線信号検出
手段の直前に設置し、前記信号分配手段により分配され
た一方の変調波を前記包絡線信号検出手段の入力とし、
かつ前記信号分配手段により分配された他方の変調波を
前記増幅手段の入力とする請求項1記載の高周波増幅装
置。
2. The phase adjusting means is installed immediately before the envelope signal detecting means, and one of the modulated waves distributed by the signal distributing means is used as an input of the envelope signal detecting means.
The high frequency amplifying device according to claim 1, wherein the other modulating wave distributed by the signal distributing means is input to the amplifying means.
【請求項3】 前記位相調整手段を前記記憶手段の直前
又は直後に設置し、前記信号分配手段により分配された
一方の変調波を前記包絡線信号検出手段の入力とし、か
つ前記信号分配手段により分配された他方の変調波を前
記増幅手段の入力とする請求項1記載の高周波増幅装
置。
3. The phase adjusting means is provided immediately before or after the storage means, and one modulated wave distributed by the signal distributing means is used as an input of the envelope signal detecting means, and by the signal distributing means. The high frequency amplifier according to claim 1, wherein the other distributed modulated wave is input to the amplifying means.
【請求項4】 前記位相調整手段を前記制御電圧生成手
段の直前又は直後に設置し、前記信号分配手段により分
配された一方の変調波を前記包絡線信号検出手段の入力
とし、かつ前記信号分配手段により分配された他方の変
調波を前記増幅手段の入力とする請求項1記載の高周波
増幅装置。
4. The phase adjusting means is installed immediately before or after the control voltage generating means, and one modulated wave distributed by the signal distributing means is used as an input of the envelope signal detecting means, and the signal distributing The high frequency amplifier according to claim 1, wherein the other modulated wave distributed by the means is input to the amplifying means.
JP18222795A 1995-06-27 1995-06-27 High frequency amplifier device Pending JPH0918247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18222795A JPH0918247A (en) 1995-06-27 1995-06-27 High frequency amplifier device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18222795A JPH0918247A (en) 1995-06-27 1995-06-27 High frequency amplifier device

Publications (1)

Publication Number Publication Date
JPH0918247A true JPH0918247A (en) 1997-01-17

Family

ID=16114574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18222795A Pending JPH0918247A (en) 1995-06-27 1995-06-27 High frequency amplifier device

Country Status (1)

Country Link
JP (1) JPH0918247A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100858408B1 (en) * 2005-12-22 2008-09-12 후지쯔 가부시끼가이샤 Device and method for controlling a voltage control signal
US9281790B2 (en) 2014-02-20 2016-03-08 Fujitsu Limited Amplifier circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100858408B1 (en) * 2005-12-22 2008-09-12 후지쯔 가부시끼가이샤 Device and method for controlling a voltage control signal
US9281790B2 (en) 2014-02-20 2016-03-08 Fujitsu Limited Amplifier circuit

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