JPH09179817A - Bus access system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the use efficiency of a control means for a common bus and a master module. SOLUTION: The control means 1 outputs a bus use right request signal. A 1st timer means 4 outputs a bus use right request quitting signal a predetermined time after the said signal is received. An arbitrating means 2 receiving the bus use right request signal waits for a bus state signal to be OFF, outputs a bus request signal and a bus acquisition signal when the bus state signal turns OFF, and quits arbitrating the common bus 40 on receiving the bus use right request quitting signal during the wait. The control means 1 accesses a slave modules 20-2N when receiving the bus acquisition signal and quits a bus accessing process when receiving the bus use right request quitting signal. A 2nd timer means 3 starts clocking the time on receiving the bus acquisition signal and outputs a bus access quitting signal a predetermined time later. The control means 1 quits the bus access when receiving the quitting signal and ends the bus accessing signal normally when receiving answers from slave modules 20-2N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus access method, and more particularly to a bus access method in a system having a plurality of modules.

[0002]

2. Description of the Related Art Conventionally, this type of bus access method has been used in a system having a plurality of modules connected to a common bus so that each of the modules can efficiently access the bus.

Referring to FIG. 4, which is a block diagram showing an example of this conventional bus access system, in the conventional system, a slave module 20 to a slave module 2N connected to a common bus 40, the common bus 40 and the common bus 40 are connected. Bus request line 30 for transmitting a signal requesting acquisition of common bus 40
Is connected to the bus request line 3 for requesting acquisition of the common bus 40 when the use of the common bus 40 is desired.
0 to 0 to obtain the common bus 40 and to access one slave module of the plurality of slave modules via the common bus 40 to a master module 8N. The master module 8N outputs a bus usage right request signal for requesting the usage right of the common bus 40, and when the common bus 40 is acquired by this request, the master module 8N selects one of the slave modules via the bus. A control unit 5 that controls access to one slave module, and receives the bus usage right request signal from the control unit 5, and arbitrates acquisition of the common bus 40 with another master module. The bus right request signal is received from the arbitration unit 6 and the control unit 5, and the time elapses after the signal is received. A timer unit 7 for outputting a time-up signal when the measured time started measuring has passed a predetermined time, a configuration having a.

The arbitration method by the arbitration unit 6 causes the master module that has previously output a signal requesting acquisition of the common bus 40 to acquire the common bus 40, and also allows a plurality of master modules to simultaneously acquire the common bus 40. When a signal requesting acquisition of the common bus 40 is output, the master module having the higher priority order acquires the common bus 40 in accordance with a predetermined priority order of acquisition of the common bus 40.

The time preset in the timer unit 7 is an average time required for the arbitration unit 6 to arbitrate the common bus 40 and an average time required for the control unit 5 to control access to the slave module. It is a time that is larger than the total time.

Next, the operation will be described.

When the master module 80 desires to access one slave module of the plurality of slave modules, the controller 5 outputs the bus use right request signal. The timer unit 7 receives the bus use right request signal and starts measuring time. Further, the arbitration unit 6 receives the bus use right request signal from the control unit 5 and arbitrates acquisition of the common bus 40 with another master module via the bus request line 30. , Acquires the common bus 40 and outputs the bus acquisition signal. The control unit 5 inputs the bus acquisition signal,
One slave module of the plurality of slave modules is accessed, and a response from the slave module to this access is obtained to terminate the access to the slave module.

On the other hand, when the control unit 5 receives the time-up signal from the timer unit 7 between the time when the bus usage right request signal is output and the time when the response from the slave module is received, As an access error, the request for the right to use the common bus 40 or the control of access to the slave module is stopped.

[0009]

According to the above-mentioned conventional bus access method, since the common bus 40 is acquired by the arbitration method of the arbitration unit 6, the master module having a low priority order of common bus acquisition is When a signal requesting acquisition of the common bus is output at the same time as the master module having the higher priority, the common bus 40 is acquired by the module having the higher priority, and therefore, until this module releases the common bus 40. It will wait for the acquisition of the common bus 40. Further, when the master module having a lower priority enters the acquisition waiting state for the common bus 40 when a master module having a higher priority than its own module is waiting for the common bus 40, the common bus 40 is released. Even so, the module having a higher priority than its own module acquires the common bus 40, and thus the waiting state is continued. On the other hand, since the timer unit 7 starts measuring time simultaneously with the input of the bus use right request signal from the control unit 5, the master module with lower priority is finally released from the waiting state and the common Even if the bus 40 is acquired and the slave module is accessed, if the time measurement of the timer unit 7 progresses and the timer unit 7 is about to time up, the time is raised immediately after accessing the slave module and the slave Since the bus access error occurs before the module responds to the access from the master module, the use of the common bus 40 must be abandoned. In such a case, the master module acquires the common bus 40 again and accesses the slave module.
There is a problem that the use efficiency of is deteriorated.

In the case of a system which frequently uses the common bus 40, the common bus 40 is frequently used, so that the master module continues to wait for the acquisition of the common bus 40. However, the means for canceling this state is only the generation of the time-up signal,
Since it is not possible to control the acquisition of the common bus 40 midway, the master module simply keeps waiting for the acquisition of the common bus 40, which causes a problem that the efficiency of use of the control unit 5 of the master module decreases. is there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus access method in which the common bus can be used efficiently and the control unit of the master module can be used efficiently in order to eliminate such conventional drawbacks.

[0012]

According to the bus access method of the present invention, a common bus to which a plurality of modules are connected is connected to each of the modules desiring to use the common bus. In the bus access method in which the module requesting acquisition and the module that has acquired the common bus in response to this request uses the common bus to access another module, the module desiring to use the common bus is the common Measure the time from requesting bus acquisition to acquiring this common bus,
A first timer means for outputting a first time-up signal when the measured time exceeds a predetermined time,
Measuring the time from the acquisition of the common bus to the reception of a response to this access from the other module that has accessed using the acquired common bus,
Second timer means for outputting a second time-up signal when the measured time has passed a predetermined time,
It is provided with.

Further, in the bus access system of the present invention, the plurality of modules connected to the common bus are connected to a bus request line for transmitting a signal requesting acquisition of the common bus, and the use of the common bus is desired. Sometimes, a plurality of master modules that output a signal requesting acquisition of the common bus to the bus request line to acquire the right to use the common bus, and a master module that acquires the common bus use the common bus. Configured by a plurality of slave modules that are accessed and output a response to this access,
In addition, the master module outputs a signal requesting acquisition of the common bus, and the master module indicates that a predetermined time has elapsed between the output of this signal and the acquisition of the common bus. If the time-up signal is input, the request for acquisition of the common bus is abandoned, and if the bus acquisition signal indicating that the common bus is acquired is input, the common bus is used for the slave module. When the second time-up signal indicating that a predetermined time has elapsed from the time when the bus access signal is input and the time when the bus acquisition signal is input until the response to the access is received from the accessed slave module is input. Is
Between the control means for ending the access to the slave module as a bus access error and a signal requesting the right to use the common bus from the control means, and between the other master module via the bus request line. Arbitration means for arbitrating the acquisition of the common bus, acquiring the common bus and outputting the bus acquisition signal, and a signal requesting the right to use the common bus, and a predetermined time after receiving the signal. First timer means for outputting the first time-up signal when the time has elapsed, and the second time-up signal when a predetermined time has elapsed after receiving the bus acquisition signal and the signal And second timer means for outputting.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the bus access system of the present invention.

The embodiment shown in FIG. 1 is a common bus 40.
And the master module 1 connected to the bus request line 30 for transmitting a bus request signal requesting acquisition of the common bus 40.
0 to a master module 1N and a slave module 20 connected to the common bus 40 and accessed from the master module that has acquired the common bus 40 using the common bus 40 and outputs a response to the access.
From the slave module 2N to the slave module 2N, and the master module outputs a bus use right request signal and indicates that a predetermined time elapses from the output to the acquisition of the common bus 40. When the time-up signal is input, the request for the right to use the common bus 40 is abandoned, and when the bus acquisition signal indicating that the common bus 40 is acquired is input, the slave module is accessed. If a second time-up signal indicating that a predetermined time has elapsed between the start of access and the reception of a response from the slave module is input, a bus access error occurs and the slave module is accessed. The control means 1 for terminating and the bus use right request signal from the control means 1 are received, and the bus request signal is sent to the bus. Arbitration means 2 for outputting to the request line 30 to arbitrate acquisition of the common bus 40 with another master module, acquire the common bus 40, and output the bus acquisition signal; and the control means 1. The first timer means 4 which receives the bus usage right request signal and outputs a bus usage right request cancel signal which is the first time-up signal when a predetermined time has elapsed after receiving the signal.
Second timer means for receiving the bus acquisition signal from the arbitration means 2 and outputting a bus access stop signal which is the second time-up signal when a predetermined time has elapsed after receiving the signal. 3 and 3.

Next, the operation of the bus access method of the present invention will be described in detail with reference to FIGS.

FIG. 2 is a flow chart showing an example of the operation of this embodiment.

FIG. 3 is a diagram for explaining the arbitration operation of the arbitration means of the master module 10. The arbitration means 2 receives a bus use right request signal from the control means 1 and receives from the master module 11 a master module 1N. All bus status signals indicating the status of the bus request signal are “OFF” (here, “OFF” indicates that the bus request signal is not output. Similarly, “ON” indicates that the bus request signal is output. Bus request line 3 after confirming that
0, a bus request signal is output to 0, and after this output, the bus status signal of a module having a predetermined priority of the common bus acquisition out of the bus status signals higher than the priority of the master module 10 is “OFF”. Then, a bus acquisition signal indicating that the common bus 40 has been acquired is output to the control means 1, the first timer means 4 and the second timer means 3. There is. In FIG. 3, the master module 10 is described as an example, but the arbitration operation of the arbitration means 2 of another master module is similar.

In FIG. 2, the control means 1 of the master module desiring to use the common bus 40 outputs the bus use right request signal to the first timer means 4 and the arbitration means 2 (S1). .

The first timer means 4 receives the request signal, starts measuring time, and the measured time is 5 μs to 10 μs which is the average time taken for arbitration of the common bus 40.
[mu] s, preferably 8 [mu] s or the like until a predetermined time elapses or until a bus acquisition signal indicating that the common bus 40 has been acquired is received from the arbitration means 2 and while measuring this time. When the bus acquisition signal is received, the measurement of the time is stopped (S2), and when the measured time exceeds the predetermined time, the time is the first time-up signal. A bus use right request cancel signal is output to the control means 1 (S3).

As shown in FIG. 3, the arbitration means 2 is activated by receiving the bus use right request signal output from the control means 1 in the step 1 (S1), and starts the bus from the bus request line 30. Wait until all the status signals are read "OFF" after reading the status signals. If the bus usage right request cancel signal is received during this waiting time, the common bus 4
When the arbitration of 0 is stopped (S4) and all the bus status signals are "OFF", the bus request signal is sent to the bus request line 3
It is output to another master module via 0 (S5), the bus status signal is read again, and the bus status signal of the master module having a higher priority of acquisition of the common bus 40 than its own master module is checked (S6). If the check result indicates "OFF", a bus acquisition signal indicating that the common bus 40 has been acquired is output to the control unit, the first timer means 4 and the second timer means 3 (S7). If the result of the examination in step 6 (S6) indicates "ON", the output of the bus request signal is stopped (S8), and control is continued following step 4 (S4).

The control means 1 controls the step 3 (S
In step 3), the bus use right request cancel signal output from the first timer means 4 or the bus acquisition signal output from the arbitration means 2 in step 7 (S7) is received. If the result of this check indicates a bus acquisition signal, the address and data of the slave module which this module desires to access are output to the common bus 40 (S10), and the step 9 (S9) is executed.
If the result checked in 9) indicates a bus use right request stop signal, the bus use right request stop signal is output to the arbitration means 2 (S11) and the bus access processing is stopped. If this is the case, the common bus 40 of this system is frequently used, so the possibility that the common bus 40 can be acquired is low, and if the bus use right request is made continuously, the control means will be executed. In order to cause the deterioration of the use efficiency of No. 1, the bus access processing is restarted from step 1 (S1) after a predetermined time has elapsed from the suspension of the bus access processing, and other processing is performed in the control means 1 during this time. I will let you.

The second timer means 3 receives the bus acquisition signal output from the arbitration means 2 in step 7 (S7), starts time measurement, and the measured time is controlled by the control means 1. The average time required to control access to the slave module is 5 μs to 10 μs
s Preferably, the time is measured until a predetermined time such as 8 μs elapses or until a bus access end signal indicating that the bus access is ended is received from the control means 1, and while the time is being measured When the bus access end signal is received, the measurement is stopped (S12), and when the measured time exceeds the predetermined time, the bus access which is the second time-up signal is stopped. A bus access stop signal is output to the control means 1 (S13).

The control means 1 receives the bus access stop signal or the response from the slave module accessed in step 10 (S10) and checks whether this is a stop signal or a response (S14). If the signal indicates a stop signal, the bus access is stopped, a bus access end signal is output to the arbitration means 2 (S15), and the bus access processing ends as a bus access error. If the result of the examination in step 14 (S14) indicates a response, the bus access end signal is sent to the arbitration means 2.
(S16), and the bus access process ends normally.

The arbitration means 2 uses the step 15 (S
15) and the control means 1 in step 16 (S16).
Upon receiving the bus access end signal output from the bus request signal, the output of the bus request signal to the bus request line 30 is stopped (S17).

In the above description, an example in which the two timer means, that is, the first timer means 4 and the second timer means 3 are provided, is shown. However, since these timer means do not operate in parallel, the same operation is performed. It may be performed by one timer means.

As described above, according to the bus access method of the present invention, the second timer means 3 acquires the common bus 40 and then the bus access regardless of the priority of the common bus acquisition. Since the time until the processing is completed is measured, even if the master module with a low priority of common bus acquisition acquires the bus, the time up before the accessed slave module responds is reduced. The use efficiency of 40 is improved.

Also, in the case of a system such as a system which frequently uses the common bus 40, in which the waiting state of the common bus 40 continues, the right to use the common bus 40 is requested and then the common bus 40 is acquired. The acquisition of the common bus 40 is waited until the time of the first timer means 4 for measuring the time until it is reached, and the bus access processing can be stopped by this time up, so that the acquisition of the common bus 40 usage right is simply kept waiting. As a result, the use efficiency of the control means 1 of the master module is improved.

Further, since the bus access processing is restarted after a predetermined time has elapsed from the suspension of the bus access processing, the use efficiency of the control means 1 of the master module is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bus access system of the present invention.

FIG. 2 is a flow chart showing an example of the operation of the present embodiment.

FIG. 3 is a diagram illustrating an arbitration operation of an arbitration unit of a master module 10.

FIG. 4 is a block diagram showing an example of a conventional bus access method.

[Explanation of symbols]

 1 Control Means 2 Arbitration Means 3 Second Timer Means 4 First Timer Means 5 Control Units 6 Arbitration Units 7 Timers 10 to 1N Master Modules 20 to 2N Slave Modules 30 Bus Request Lines 40 Common Buses 80 to 8N Master Modules

Claims (3)

[Claims] 1. A common bus to which a plurality of modules are connected, each module of the plurality of modules desiring to use the common bus requests acquisition of the common bus, and the common bus is acquired by this request. In the bus access method in which the module accesses the other module using the common bus, the module desiring to use the common bus requests the acquisition of the common bus before Measuring the time until acquisition, and first timer means for outputting a first time-up signal when the measured time has passed a predetermined time; and after acquiring the common bus Measuring the time to receive a response to this access from the other module that accessed using the common bus,
A bus access method comprising: a second timer unit that outputs a second time-up signal when the measured time exceeds a predetermined time. 2. The plurality of modules connected to the common bus are connected to a bus request line for transmitting a signal requesting acquisition of the common bus, and acquire the common bus when the use of the common bus is desired. A plurality of master modules that output a request signal to the bus request line to acquire the right to use the common bus, and a master module that has acquired the common bus are accessed using the common bus and a response to the access is sent. A plurality of slave modules for outputting, and the master module outputs a signal requesting acquisition of the common bus, and outputs the signal in advance and before acquiring the common bus. When the first time-up signal indicating that the predetermined time has elapsed is input, the request for acquisition of the common bus is abandoned and the common When a bus acquisition signal indicating that a bus has been acquired is input, the slave module is accessed using the common bus, and after the bus acquisition signal is input, the accessed slave module responds to the access. When the second time-up signal indicating that a predetermined time has elapsed before receiving is received, a control means for ending access to the slave module as a bus access error, and the control means Receiving a signal requesting the right to use the common bus, arbitrating the acquisition of the common bus with another master module via the bus request line, acquiring the common bus, and outputting the bus acquisition signal. And a signal requesting the right to use the common bus, and a predetermined time has elapsed since the signal was received. First timer means for outputting the first time-up signal when receiving the bus acquisition signal, and the second time-up signal when the predetermined time has elapsed after receiving the bus acquisition signal. The bus access method according to claim 1, further comprising: second timer means for outputting. 3. The control means, when the first time-up signal is input, outputs a signal requesting the right to use the common bus again after a predetermined time has elapsed from the input of this signal. 3. The method according to claim 2, wherein
Bus access method described.