JPH09179667A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively reduce the power consumption of the whole computer system in accordance with the using state of real resources. SOLUTION: A real computer 101 is provided with real CPUs 102, 103 and receives power supply from a power supply device 104. Under the control of an instruction processor allocating means 11, the real CPUs 102, 103 are allocated to logic computers 120, 130 and driven. A real resource monitor 112 monitors the using rates of the CPUs 102, 103. A degenerate judging means 113 judges whether the number of driven real CPUs allocated to the computers 120, 130 can be regenerated or not based upon the using rates of the CPUs 102, 103. The means 111 regenerates the CPUs 102, 103 based upon the judged result of the means 113 and allocates the regenerated CPUs 102, 103 to the computers 120, 130 and the device 104 interrupts power supply to the regenerated and unused real CPUs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which logically divides an actual computer system to provide a plurality of logical computer systems, and is particularly suitable for an information processing apparatus suitable for power saving.

[0002]

2. Description of the Related Art Currently, a review of energy consumption on a global scale is in progress. In recent years, information processing devices, which have advanced usage in various social fields,
There is a demand for reduction of power consumption.

Conventionally, for example, the following measures have been generally taken in terms of power saving of the information processing apparatus.

(1) Basically, the power consumption of the device is reduced. For example, by devising the electronic circuit that constitutes the information processing device, reducing the power consumption of the element itself that constitutes the electronic circuit, or reducing the power consumption of the components that configure the information processing device. , It is intended to reduce the power consumption as a whole.

(2) The power of the device is frequently cut off. This is "turn off the power when not in use", and although it is primitive, it is a socially proper way and the basics.

(3) Power control is performed for each component of the information processing apparatus. This is because, as is often seen in portable information processing devices these days, for example, the power of the display device is automatically turned off if there is no input from the input device for a certain period of time, and the power consumption of the entire device is reduced. It is intended to reduce the consumption amount.

[0007]

According to the above-mentioned conventional technique, it is possible to surely save the power consumption of the information processing apparatus, but there are problems to be improved as described below.

The method of "turning off the power when not in use" described in (2) above means, conversely, that the power cannot be turned off even if it is used for a while. Most information processing devices do not use their eyes full 24 hours a day, 7 days a week. For example, the usage rate drops extremely on weekends. However, unless the usage rate is still zero,
You cannot turn off the power. From a functional or performance point of view, even though it is "almost unused", the power consumption is almost the same as when it is "full of eyes", and the world is not satisfied.

In this respect, the method described in the above (3) is excellent because the power consumption is reduced as the "usage rate" is lowered as a whole. However, with this method, it is difficult to realize a program that has been conventionally used without any change. For example, the program needs to monitor the usage of some resource. Alternatively, even when the usage status of some resource is monitored as hardware, the hardware needs to transmit information sufficient for determining whether the resource is available to the program. Of course, the program needs to properly process the transmitted information. In any case, the necessary function as such a program must be newly incorporated.

As a matter of course, recent portable information processing devices are equipped with the latest programs, and the latest programs have the power saving function described in the above (3) incorporated therein from the beginning. Is normal. However,
In the case of a general-purpose large-sized information processing device, the "heritage" of programs that have been used for many years is enormous, and it is not possible to easily incorporate a power saving function.

The "basic countermeasure" described in (1) above seems to have no problem at first glance. However, energy consumption is not something that “you have to meet some regulation value”. Even if the information processing device has a sufficiently low power consumption, it is "full of eyes" when it is "mostly unused" in terms of function or performance.
It is important to keep power consumption lower than when using it. Therefore, it is to actively contribute to the human issue of reducing energy consumption on a global scale.

An object of the present invention is to provide an information processing apparatus having a function of dynamically reducing power consumption in response to a reduction in utilization rate of real resources without making any change to a conventional program. To do. In particular, the present invention is to provide convenience in implementing the power saving function as described above in an information processing apparatus that provides a plurality of logical computer systems by logically dividing an actual computer system.

[0013]

The present invention is an information processing system comprising at least one real computer system (real resource) and logically dividing the real resource to provide a plurality of logical computer systems. , Based on the performance of each logical computer system and the actual resource usage status, if possible, dynamically degenerate the real resources and shut off the power of the degenerated part, or reduce the power supply, Means are provided to reduce overall power consumption.

More specifically, means for designating the upper limit of the real resource usage rate of each logical computer system, means for measuring the actual real resource usage rate of each logical computer system, and each designated logical computer. Determining whether or not real resource degeneracy is possible based on the upper limit of system real resource utilization and the measured actual resource utilization of each logical computer system, etc. If it is determined that the real resource is degenerated, a means for cutting off the power of the degenerated real resource or reducing the supplied power is provided. The upper limit of the actual resource utilization rate of each logical computer system may be implicitly determined.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram for explaining an embodiment of the present invention. In the figure, the actual computer 10
Reference numeral 1 is the functional center of the computer system shown in this embodiment, and comprises a real instruction processor 102 and a real instruction processor 103. Real instruction processors 102 and 103
Is a functional part that realizes the calculation function of the real computer 101, and its processor performance is
Both are set to “100”. Of course, in general, the actual instruction processors need not be limited to the two shown in FIG.

The power supply device 104 supplies the power necessary for operating the entire real computer 101 with the power control cable 150.
It is supplied through. In particular, power is supplied to the actual instruction processor 102 and the actual instruction processor 103 by the power control cable 151 and the power control cable 1 respectively.
It can be controlled individually via 52.

The logical partitioning mechanism 110 is a mechanism that logically realizes the logical computer 120 and the logical computer 130 by controlling the real computer 101 and the power supply device 104 as a whole and logically partitioning them. . The logical computer 120 logically includes a logical instruction processor 121. Further, the logical computer 130 uses the logical instruction processor 13
1 is logically provided.

The logical computer 120 and the logical computer 130
Are all logically complete computer systems, each of which can be used as an independent computer by a different user. In this embodiment, the logical computer 120 is used by the user A, and the logical computer 130 is used.
Is used by user B.

The performance setting panel 140 is used for the logical computer 12
0 is an operation panel on which the operator sets the performance (logical performance) of 0 and the logical computer 130. Performance setting panel 1
The value set in 40 is transmitted to the logical partitioning mechanism 110, in particular to the degeneration determination means 113 described later, via the control lines 160 and 161.

The instruction processor allocating means 111 is provided as an important part of the logical partitioning mechanism 110, and under the control of the logical partitioning mechanism 110, how the actual instruction processor 102 and the actual instruction processor 103 are logical instruction processors 121. And the logical instruction processor 131 is controlled.

The actual resource utilization monitor 112 is a real computer 1
The usage statuses of various real resources included in 01 are monitored via monitor lines 163 and 165. In particular, the usage status of the real instruction processor 102 and the real instruction processor 103 can be monitored via monitor lines 162, 164, and 165. In addition, the actual resource utilization monitor 112 provides appropriate information to the control line 167.
Is transmitted to the degeneracy determination means 113 via.

The degeneracy determining means 113 has a control line 16
Performance setting panel 140 transmitted via 0, 161
Data set to (required logical processor performance),
A means for determining whether or not some real resource such as the real computer 101 can be degenerated based on the data (real processor usage status) monitored by the real resource usage rate monitor 112 given via the control line 167. Is. Further, the degeneration determining unit 113 transmits a control signal to the power supply device 104 via the control line 166 regarding the power supply of the real instruction processor 102 and the real instruction processor 103, thereby supplying / shutting off the degenerated real resource. To control. Here, the real resources are the real instruction processors 102 and 103.

The actual resource utilization rate monitor 112 and the degeneration determining means 113 are both a part of the logical partitioning mechanism 110, and as a whole perform each function under the control of the logical partitioning mechanism 110. The operation of FIG. 1 will be described below.

Now, the logical computer 120 is used by the user A, and the logical computer 130 is used by the user B. It is assumed that the user A does not need the processor performance of "100" of the real instruction processor 102 or the real instruction processor 103 in view of the required work processing amount. Specifically, it is assumed that the required processor performance is "70". In such a case, the user A makes an agreement with the system administrator that the processor performance is "70" at the maximum. Generally, since the usage fee of the computer system is determined by the processing performance, the user A may pay the system administrator a usage fee commensurate with the processor performance “70”. As a result, the system administrator sets the performance of the logical computer 120 to "7" on the performance setting panel 140.
Set to "0". On the other hand, it is assumed that the user B does not need the processor performance of "100" of the real instruction processor 102 or the real instruction processor 103 in view of the required work processing amount. Specifically, the required processor performance is "7.
0 ". The user B makes an agreement with the system administrator that the processor performance is "70" at most, and pays the system administrator a usage fee commensurate with the processor performance "70". The system administrator
The performance of the logical computer 130 is set to "70" on the performance setting panel 140.

The logical partitioning mechanism 110 includes a performance panel 140.
The actual instruction processor 102 and the actual instruction processor 103 are scheduled on the basis of the data set in.
In the present case, the required performance of both user A and user B is "7.
It is "0", and when combined, it becomes "140". Therefore, the actual instruction processor 102 or the actual instruction processor 10
It is clear that any one of the 3 is insufficient in performance.

Therefore, the logical partitioning mechanism 101 allocates the real instruction processor 102 and the real instruction processor 103 to the logic instruction processor 121 and the logic instruction processor 131, respectively, as indicated by the assignment lines 129 and 139. However, in this case, the processor performances of the real instruction processor 102 and the real instruction processor 103 are each “10”.
Since it is "0", the user A and the user B can enjoy the service of the processor performance "100" with the usage fee of the processor performance "70". If the system administrator is benevolent, then nothing should go wrong, but it really isn't. Although the user is not responsible at all,
It is a so-called "just take" of processor performance.

Therefore, the logical partitioning mechanism 101 controls allocation of the real instruction processor 102 and the real instruction processor 103 as shown in FIG. 2, for example.

FIG. 2 is a time chart for explaining how the logical partitioning mechanism 101 controls the actual instruction processor 102 used as the logical instruction processor 121 for the sake of convenience. The logical instruction processor 1
The control relating to the actual instruction processor 103 used as 31 is also the same.

As shown in FIG. 2, the logical partitioning mechanism 101 divides the real instruction processor 102 into one unit time and manages and controls it. Then, the logical division mechanism 101 causes the logical instruction processor 121 to use the actual instruction processor 102 only for 70% per unit time. Such control can be easily realized by utilizing, for example, a timer mechanism incorporated in the real computer 101.

One unit time set appropriately, for example, 20
Given that milliseconds are used, the actual performance of the logic instruction processor 121, given a sufficiently long time, is given by the following equation: Logical processor performance = actual instruction processor performance × usage rate per unit time = 100 × 70% = 70 The value “70” calculated here is the performance required by the user A. Therefore, it goes without saying that the above control satisfies not only the user A but also the system administrator.

It should be noted here that the logical partitioning mechanism 110 is
The 70% time per unit time allotted for the logical instruction processor 121 is only the time that the logical instruction processor 121 is allowed to use. Actually, 7 per unit time
Whether or not 0% of the time is used 100% depends on the behavior of the program of the user A.

Next, a description will be given of a case where the usage rate of the logical instruction processor 121 or the logical instruction processor 131 changes, which exhibits the effect peculiar to the present invention. For convenience, the logical instruction processor 131 is taken as an example here.

The program of the user B is the logical partitioning mechanism 1
A logical instruction processor 131 controlled by 10 can be used. However, even if the program of the user B uses the logic instruction processor 131 to the fullest extent,
The actual instruction processor 103 used as the logical instruction processor 131 is only 70% used.

By the way, the program of the user B does not always use the logic instruction processor 131 to the full (24 hours a day, 7 days a week). For example, weekends may experience lower utilization. Or, even on weekdays, the usage rate will decrease at lunchtime. Even so, everyone gets sleepy around 3 pm. If you don't have enough control over the device, the usage rate will drop dramatically.

FIG. 3 shows the actual instruction processor 10 in such a state.
3. The logical life processor 131 will be described.

Due to the function of the logical division mechanism 110, 70% of the time of the real instruction processor 103 is allocated to the logical instruction processor 131 per unit time. The program of the user B manages / controls this logical instruction processor 131. For some reason already mentioned, now,
It is assumed that the usage rate of the logic instruction processor 131 related to the program of the user B is very low, for example, 20%. At this time, the usage rate of the actual real instruction processor 103 related to the logical instruction processor 131 can be calculated by the following formula. Usage rate of actual instruction processor 103 = Percentage of time allocated to logical instruction processor 131 per unit time x Usage rate as logical instruction processor 131 = 70% x 20% = 14% That is, the required processor performance of user B is "70",
If the usage rate of the logical instruction processor 131 of the program of the user B is 20%, the usage rate of the actual instruction processor 103 is 1
4%.

An important point of the result of examining the above situation is that the utilization rate of the actual instruction processor 103 is 14% shorter than the unused time of 30% per unit time. . It is clear from the back calculation, but when it falls below about 40%, the utilization rate of the actual instruction processor falls below the unused time of 30%. That is, the usage rate of the real instruction processor 103 = the ratio of the time allocated to the logical instruction processor 131 per unit time × the usage rate as the logical instruction processor 131 Here, assuming that the usage rate of the real instruction processor 103 is 30% or less, When the usage rate of the logical instruction processor 131 is calculated, the usage rate of the logical instruction processor 131 × 70% <30% The usage rate of the logical instruction processor 131 <30% / 70% ∴ The usage rate of the logical instruction processor 131 < It will be about 40%.

The degeneration determining means 113 determines the current setting "7.
In the case of “0”, the usage rate of the logic instruction processor 131 is about 40.
When it falls below%, it is determined that degeneration is possible.

In this case, the logical partitioning mechanism 110 controls the logical instruction processor 131 so as to allocate the unused time of the real instruction processor 102. FIG. 4 shows the state at this time.

The logical partitioning mechanism 110 is used by the real instruction processor 1
70% of 02 per unit time is allocated to the logical instruction processor 121 as described above with reference to FIG. And
The remaining 30% of the time is allocated to the logic instruction processor 131. At this time, the actual instruction processor 103 is not used at all.

Even in this state, the time of the actual instruction processor 102 assigned to the logical instruction processor 131 is 30% per unit time, which is sufficient for the program of the user B. This is because in the current situation, the program of the user B is in a sufficient operating state if 14% of the actual instruction processor 102 can be used.
Even if the usage rate of the logical instruction processor 131 of the program of the user B slightly rises, it operates without any problem until the usage rate of the logical instruction processor 131 reaches about 40%.

As described above, when the usage rate of the logical instruction processor 131 of the program of the user B is low, the logical partitioning mechanism 110 provides the logical instruction processor 131 by using the unused time of the real instruction processor 102. be able to.
At this time, the actual instruction processor 103 does not need to be used at all. Similarly, when the usage rate of the logical instruction processor 121 of the program of the user A is low, the logical instruction processor 121 can be allocated to the unused time of the real instruction processor 103, and at this time, the real instruction processor 102 You don't have to use it at all. Therefore, the logical partitioning mechanism 11
0, in particular, the degeneration determination means 113 is the power supply device 10
Instruct 4 to stop the power supply to the actual instruction processor that is no longer used.

The detailed operation of the logical partitioning mechanism 110 which brings about the unique effect of the present invention will be described below with reference to FIGS.

FIG. 5 is a detailed functional block diagram of the logical partitioning mechanism 110, in particular, the actual instruction processors 102 and 103 and the instruction processor allocating means 111. As already described with reference to FIG. 1, the logical instruction processor 121 is assigned to the real instruction processor 102 on the assignment line 129, while the logical instruction processor 131 is assigned to the real instruction processor 103 on the assignment line 139. .

Although the real instruction processor 102 is composed of various logic circuits, it is assumed that the functional block seen from the program is composed of a general-purpose register 521, a control register 522, and a program status word 523. That is, the general-purpose register 521 and the control register 52
1 and the value held by the program status word 523 is the actual instruction processor 10 visible to the program at that time.
It can be said that it has all two states.

The actual instruction processor 103 is also composed of various logic circuits, but the functional blocks seen from the program are composed of a general-purpose register 531, a control register 532, and a program status word 533. . That is, the values held by the general-purpose register 531, the control register 532, and the program state word 533 embody all the states of the real instruction processor 103 that can be seen from the program at that time.

The instruction processor allocating means 111 is roughly composed of the following six functional blocks. That is, (1) actual instruction processor control means 520 for controlling the actual instruction processor 102, (2) actual instruction processor control means 530 for controlling the actual instruction processor 103, and (3) processor state for saving the state of the logical instruction processor 121. Storage area 5
26, (4) Processor state save area 536 for saving the state of the logical instruction processor 131, (5) Logical instruction processor 1
21 actual instruction processor 102 or actual instruction processor 1
Timer value save area 52 for holding the allocated time to 03
5 and (6) a timer value storage area 535 for holding the time allocated to the real instruction processor 102 or the real instruction processor 103 of the logic instruction processor 131.

The real instruction processor control means 520 can read and write the general-purpose register 521, the control register 522, and the program status word 523 of the real instruction processor 102 via the control line 561. Also,
The actual command control means 520 comprises a timer 524.
The timer 524 is a subtraction timer for measuring the allocated time of the real instruction processor 102, and when the preset time elapses, the timer 524 controls the real instruction processor control means 520.
Is detected.

Similarly, the actual instruction processor control means 530
A general-purpose register 531 included in the real instruction processor 103,
Control register 532 and program status word 533
Can be read and written via the control line 571.
Also, the actual command control means 530 includes a timer 534. The timer 534 is a subtraction timer that measures the allocated time of the real instruction processor 103, and the real instruction processor control means 530 detects it when a preset time has elapsed.

The processor state storage area 526 is an area for storing a general purpose register, a control register, and a program state word logically included in the logical instruction processor 121, and their values are general purpose register 527, control register 528, and It is held in the program status word 529. Since the general-purpose register, the control register, and the program state word embody all the states of the real instruction processor seen by the program, the processor state save area 526
Can be said to be freezing and saving all the states of the logical instruction processor 121 at a certain point.

The processor state storage area 536 is an area for storing a general purpose register, a control register, and a program state word which the logical instruction processor 131 logically has, and their values are general purpose register 537, control register 538, and It is held in the program status word 539. Like the processor state save area 526, the processor state save area 53
It can be said that 6 freezes and saves all the states of the logic instruction processor 131 at a certain point in time.

The timer value storage area 525 is a register for holding a timer value used for allocation control of the logical instruction processor 121. The timer value storage area 535 is a register that holds a timer value used for allocation control of the logical instruction processor 131.

The logical partitioning mechanism 110 calculates the value to be set in the timer value storage area 525 as follows.
Here, for convenience, one unit time is 20 milliseconds. 70% here means that the performance of the actual instruction processor 102 is "10.
It is a value calculated from "0" and the required performance "70" of the logical instruction processor 121.

In the following description, it is assumed that the timer value "14 milliseconds" calculated by the above equation is preset in the timer value saving area 525 by the logical dividing mechanism 110. Similarly, it is assumed that the timer value "14 milliseconds" is preset in the timer value storage area 535 by the logical partitioning mechanism 110.

Actual instruction processor 10 when viewed in one unit time
The processing procedure of the logical partitioning mechanism 110 for 2 is as follows. The logical partitioning mechanism 110 reads the timer value “14 milliseconds” stored in the timer value storage area 525 and sets it in the timer 524 via the control lines 565, 550, 563.

The logical partitioning mechanism 110 includes the logical instruction processor 12 held in the processor state save area 526.
Read the frozen state of 1 and execute the actual instruction processor 1
Set to 02. More specifically, the actual instruction processor control means 520 includes a general-purpose register 527 and a control register 52.
8 and the value held by the program state word 529 are read via the control lines 564, 550, 562,
Subsequently, the general-purpose register 52 is connected via the control line 561.
1, control register 522, and program status word 523. Simultaneously with this setting, the subtraction count of the timer 524 starts.

Through the above processing, the actual instruction processor 1
02 starts operating as a logic instruction processor 121.
Then, the timer value “14” set in the timer 524
The actual instruction processor 102 continues to operate as the logical instruction processor 121 until "milliseconds" have elapsed.

When the timer value “14 milliseconds” set in the timer 524 elapses, the logical partitioning mechanism 110
Reads the state of the real instruction processor 102 and stores it in the program state storage area 526. That is, the state of the logical instruction processor 121 is frozen. More specifically,
The actual instruction processor control means 520 uses the general-purpose register 52.
1, control register 522, and program status word 5
The value held by 23 is read via the control line 561, and subsequently, via the control lines 562, 550, and 564, the general-purpose register 527, the control register 528, and
Set to program status word 529.

When the timer value “14 milliseconds” set in the timer 524 elapses and one unit time of 20 milliseconds is reached, the time of 6 milliseconds still remains. The logical division mechanism 110 has the start of the next one unit time while the actual instruction processor 102 is unused for the time of 6 milliseconds.

With the above processing procedures, the allocation control of the real instruction processor 102 to the logical instruction processor 121 becomes as shown in FIG.

On the other hand, the allocation control of the real instruction processor 103 to the logical instruction processor 131 is also performed in the same manner as the above procedure. That is, the logical partitioning mechanism 110 reads out the timer value “14 milliseconds” stored in the timer value storage area 535 and sets it in the timer 534 via the control lines 575, 550 and 573.

The logical partitioning mechanism 110 includes the logical instruction processor 13 held in the processor state save area 536.
Read the frozen state of 1 and execute the actual instruction processor 1
Set to 03. More specifically, the actual instruction processor control means 530 includes a general-purpose register 537 and a control register 53.
8 and the value held by the program state word 539 are read via the control lines 574, 550, 572,
Subsequently, the general-purpose register 53 is connected via the control line 571.
1, control register 532, and program status word 5
Set to 33. Simultaneously with this setting, the subtraction count of the timer 534 starts.

Through the above processing, the actual instruction processor 1
03 starts operation as the logical instruction processor 131. The actual instruction processor 103 continues until the timer value “14 milliseconds” set in the timer 534 elapses.
Continues to operate as the logical instruction processor 131.

When the timer value “14 milliseconds” set in the timer 534 elapses, the logical partitioning mechanism 110
Reads the state of the real instruction processor 103 and stores it in the processor state storage area 536. That is, the state of the logical instruction processor 131 is frozen. More specifically, the actual instruction processor control means 530 uses the general-purpose register 531 and
Control register 532 and program status word 533
The value held by is read via the control line 571,
Subsequently, the general-purpose register 537, the control register 538, and the program status word 539 are set via the control lines 572, 550, and 574.

When the timer value “14 milliseconds” set in the timer 534 elapses and one unit time is set, 6 milliseconds still remains. Logical partitioning mechanism 1
The 10 waits for the start of the next one unit time while keeping the actual instruction processor 103 unused for the time of 6 milliseconds.

By repeating the series of processes described above, the actual instruction processor 102 is assigned to the logical instruction processor 121 to operate for 70% of the time (14 milliseconds) per unit time (20 milliseconds). Similarly, the real instruction processor 103 is assigned to the logical instruction processor 131 to operate. The instruction processor assignment line 129 and the instruction processor assignment line 139 in FIG. 1 show this.

When the above-mentioned operation is performed, for example, the utilization rate of the logical instruction processor 131 is reduced for some reason, that is, the utilization rate of the actual instruction processor 103 is reduced, FIG. It demonstrates using.

The operation status of the real instruction processor 103 is monitored by the real resource use monitor 11 via the monitor lines 164 and 165.
2 is being monitored. There are various kinds of data to be monitored, and among them, data on the usage rate of the real instruction processor 103 (real resource usage status) is also included. For example, it monitors that the actual instruction processor 103 is in the "wait state". By measuring the time in the "wait state", the usage rate of the real instruction processor 103 is grasped by the real resource usage rate monitor 112.

Now, as described above with reference to FIG. 3,
It is assumed that the utilization rate of the real instruction processor 103 has dropped to 14%. This measurement data is the actual resource utilization monitor 1
12 through the control line 167, the degeneration determination means 113.
Is transmitted to

The degeneracy determining means 113 has already recognized that the logical partitioning mechanism 110 causes the logical instruction processor 121 to use 70% of the actual instruction processor 102 and the remaining 30% is unused. The degeneracy determination means 113 uses the actual instruction processor 103 transmitted through the control line 167 with a usage rate of “14%” and an actual instruction processor 102 with an unused rate of “3”.
0% ", and as a result, it is determined that the usage rate of the real instruction processor 103 is sufficiently smaller than the unused rate of the real instruction processor 102. Based on this determination result, the degeneracy determination means 113 sends a control signal to the instruction processor allocation means 111 via the control line 168.

Upon receiving the control signal from the degeneracy determining means 113, the instruction processor assigning means 111 assigns the logical instruction processor 131 to the real instruction processor 102 as indicated by the assigning line 639 in FIG. And, 30% of the time of the actual instruction processor 102 which has not been used until now,
It is used by the logical instruction processor 131.

The manner in which the logical instruction processor 121 and the logical instruction processor 131 are assigned to the real instruction processor 102 is as shown in FIG. Hereinafter, more detailed processing of the logical partitioning mechanism 110 at this time will be described with reference to FIG. 7.

The control relating to the logical instruction processor 121 is basically the same as the processing procedure described above with reference to FIG. That is, the logical partitioning mechanism 110 takes 1 unit time (20 milliseconds)
At the beginning of the, the timer value “14 milliseconds” stored in the timer value storage area 525 is read out, and the control lines 565 and 55 are read.
The timer 524 is set via 0 and 563.

The logical partitioning mechanism 110 includes the logical instruction processor 13 held in the processor state save area 526.
Read the frozen state of 1 and execute the actual instruction processor 1
Set to 02. Simultaneously with this setting, the subtraction count of the timer 524 starts.

The real instruction processor 102 starts operating as the logical instruction processor 121. Then, the actual instruction processor 102 continues to operate as the logical instruction processor 121 until the count value “14 milliseconds” set in the timer 524 elapses.

When the timer value “14 milliseconds” set in the timer 524 elapses, the logical partitioning mechanism 110
Reads the state of the real instruction processor 102 and saves the processor state in the save area 526. That is, the state of the logical instruction processor 121 is frozen.

In the description of FIG. 5, the logical partitioning mechanism 1 is then used.
10 left the real instruction processor 102 unused for "6 milliseconds". However, based on the control signal from the degeneracy determination means 113, in this case, the logical partitioning mechanism 110 subsequently controls the “6 milliseconds” to allocate the real instruction processor 102 to the logical instruction processor 103. I do.

Currently, the frozen state of the logical instruction processor 131 is stored in the processor state storage area 536. This content indicates that the allocation of the logical instruction processor 131 is transferred from the real instruction processor 103 to the real instruction processor 102.
When it is about to switch, the state of the actual instruction processor 103 is finally saved. That is, 1
From the beginning of the unit time (20 milliseconds), the actual instruction processor 10
3 operates as the logical instruction processor 131, and when the timer value “14 milliseconds” set in the timer 535 elapses, the actual instruction processor control means 530 causes the general-purpose register 531, the control register 532, and the program status word. The value held by 533 is read via the control line 571, and subsequently, the control lines 572, 550, 57.
General register 537, control register 538,
And the state held by setting the program state word 539.

When the logical partitioning mechanism 110, in particular the instruction processor allocating means 111 receives the control signal from the degeneracy determining means 113, the timer value saving area 535 of "6 milliseconds" is set as the timer value for the logical instruction processor 131.
Set to. Needless to say, this value is the unused time of the real instruction processor 102.

After making the above settings in advance, the logical partitioning mechanism 110 changes the allocation of the logical instruction processor 131 to the real instruction processor 102. That is, when the freezing process for the logical instruction processor 121 is completed, the logical partitioning mechanism 110 subsequently reads the timer value “6 milliseconds” stored in the timer value storage area 535, and the control lines 575, 550, The timer 524 is set via 563. The data flow at this time is shown by an auxiliary broken line 750 in FIG.

The logical partitioning mechanism 110 includes the logical instruction processor 13 held in the processor state save area 536.
Read the frozen state of 1 and execute the actual instruction processor 1
Set to 02. More specifically, the actual instruction processor control means 520 includes a general-purpose register 537 and a control register 53.
8, or the value stored in the program state word 539 is read out via the control lines 574, 550, 562,
Subsequently, the general-purpose register 52 is connected via the control line 561.
1, control register 522, and program status word 5
Set to 23. The data flow at this time is shown by an auxiliary broken line 760 in FIG. At the same time as this setting, the timer 524
The subtraction count of starts.

Through the above processing, the actual instruction processor 1
02 starts operating as the logical instruction processor 131. Then, the actual instruction processor 102 continues to operate as the logical instruction processor 131 until the timer value “6 milliseconds” set in the timer 524 elapses.

When the timer value “6 milliseconds” set in the timer 524 elapses, the logical partitioning mechanism 110
The state of the actual instruction processor 102 at that time is read out and stored in the processor state storage area 536. That is, the state of the logical instruction processor 131 is frozen. More specifically, the actual instruction processor control means 520 uses the general-purpose register 5
21, the control register 522, and the value stored in the program state word 523 are read via the control line 561, and subsequently, the general-purpose register 5327, the control register 538, and the control register 538 via the control lines 562, 550, and 574. , Program status word 539. The data flow at this time is shown by an auxiliary broken line 760.

At this point, since one unit time (20 milliseconds) for the real instruction processor 102 has expired, the allocation of the logical instruction processor 121 is started again.

By repeating the above series of processing, the allocation of the logical instruction processor 121 and the actual instruction processor 131 becomes as shown by the instruction processor allocation line 129 and the instruction processor allocation line 639 in FIG.

In this way, the logical instruction processor 12
1 and the logical instruction processor 131 are provided only by the actual instruction processor 102, as shown in FIG. That is, the real instruction processor 103 is no longer needed to provide the logical instruction processor 131.

In such a situation, the logical partitioning mechanism 110
It is determined that the power of the actual instruction processor 103 can be cut off. Therefore, the degeneration determination unit 113 sends a control signal to the power supply device 104 via the control line 166. Power supply device 104 that has received this control signal
Is the actual instruction processor 1 via the power control cable 151.
The power supply supplied to 03 is cut off. As a result, the actual instruction processor 103 enters a power-off state. Naturally, in this state, the power consumption of the real instruction processor 103 becomes "zero".

The operation when the utilization rate of the logical instruction processor 131 is lowered is summarized as follows. (1) The logical instruction processor 121 and the logical instruction processor 131 are provided only by the actual instruction processor 102. (2) Even in such a state, the required processor performance "70" is surely guaranteed for the logical instruction processor 121. (3) Although the initial required performance "70" is not guaranteed for the logical instruction processor 131, the currently required processor performance is sufficiently satisfied. (4) As mentioned in (2) and (3) above, the power of the actual instruction processor 103 is cut off in a state in which the user A and the user B are provided with sufficient performance and functions. As a result, the power consumption is reduced by the power consumption of the actual instruction processor 103.

The operation when the processing amount of the program of the user B of the logical computer 130 increases again during the operation in the power saving state will be briefly described with reference to FIG. Just like that. The actual resource utilization monitor 112 is the actual instruction processor 10
The usage rate of 2 is monitored. 30% per unit time allocated to the logical instruction processor 131 by the monitor 112
Recognize that the time is almost 100% used. Based on the data sent from the real resource usage rate monitor 112 via the control line 167, the degeneration determining means 113 no longer requires 30% of the real instruction processor 102 as the required performance of the logical instruction processor 131. And the logical instruction processor 131 is set to the actual instruction processor 103.
Determine that it should be assigned to. The power supply device 104 turns on the power of the actual instruction processor 103 via the power supply control line 151 in accordance with the command transmitted from the degeneration determining means 113 via the control line 166. The instruction processor allocating means 111 uses the control line 168.
According to the command transmitted from the degeneracy determination means 113 via the, the allocation of the logical instruction processor 131 is changed from the allocation line 539 to the allocation line 139 in FIG.

Through the series of procedures described above, the computer system returns to the "normal" operating state as described with reference to FIG. The series of operations 1 to 3 described above may take several tens of seconds, but during that time, the logical instruction processor 131 is not inactive at all. Although the required performance may be slightly less than the required performance, it goes without saying that the logical instruction processor 131 is continuously provided using the actual instruction processor 102 during the series of processes.

The embodiment of the present invention has been described above. In the description of the embodiment, the power supply to the unused real instruction processor is completely cut off, but it may be reduced. That is, even when it is not used, the minimum necessary power is supplied to keep the actual instruction processor in the standby state. As a result, when the real instruction processor is needed again, it is possible to return to the normal operation state in a short time.

Further, in the description of the embodiment, the required performance of each logical instruction processor is set from the performance setting panel, but of course, this may be implicitly determined.

[0093]

As described above, according to the present invention, in an information processing device in which a real computer having a plurality of real processors is logically divided and used as a plurality of logical computers, the utilization rate of the logical computers can be reduced. The power consumption of the information processing apparatus as a whole is reduced by dynamically degenerating the actual resources such as the number of actual instruction processors to be operated according to the decrease and shutting off the power of the degenerated actual instruction processors or reducing the power supply. It can be reduced.

[Brief description of the drawings]

FIG. 1 is a functional block diagram for explaining an embodiment of an information processing device according to the present invention.

FIG. 2 is a time chart for explaining allocation control of real instruction processors to logical instruction processors.

FIG. 3 is a time chart for explaining a usage rate of a logical instruction processor.

FIG. 4 is a time chart for explaining real instruction processor allocation control when an effect peculiar to the present invention is exhibited.

5 is a functional block diagram for explaining instruction processor allocation means in FIG. 1. FIG.

FIG. 6 is a functional block diagram for explaining instruction processor allocation when an effect peculiar to the present invention is exhibited.

7 is a functional block diagram for explaining the operation of the instruction processor allocating means in FIG.

[Explanation of symbols]

 101 Real Computer 102, 103 Real Instruction Processor 104 Power Supply Unit 110 Logical Partitioning Mechanism 111 Instruction Processor Allocation Unit 112 Real Resource Utilization Monitor 113 Degeneracy Determining Unit 120, 130 Logical Computer 121, 131 Logical Instruction Processor 129, 139 Instruction Processor Allocation Line 140 Performance setting panel 520, 530 Actual instruction processor control means 521, 531 General purpose register 522, 532 Control register 523, 533 Program status word 524, 534 Timer 525, 535 Timer value storage area 526, 536 Processor status storage area

Claims (3)

[Claims] 1. An information processing apparatus comprising at least one computer system (hereinafter, referred to as a real resource) and logically dividing the substantial source to provide a plurality of logical computer systems, wherein First means for designating logical performance, second means for measuring the actual resource usage of each logical computer system, logical performance designated by the first means, and measurement by the second means Third means for determining whether or not degeneration of the real resource is possible based on the actual resource usage status of each logical computer system, and it is determined that the degeneracy of the real resource is possible by the third means. And a fourth means for degenerating the real resource and cutting off the power of the degenerated part. 2. An information processing apparatus comprising at least one computer system (actual resource), logically dividing the actual resource to provide a plurality of logical computer systems, and logical performance of each logical computer system. Means for designating the actual resource usage status of each logical computer system, the logical performance designated by the first means, and each measured by the second means. Third means for determining whether or not degeneracy of the real resource is possible based on the actual resource usage of the logical computer system, and when it is determined that the degeneracy of the real resource is possible by the third means, An information processing apparatus, comprising: a fourth means for degenerating an actual resource and reducing power supplied to the degenerated portion. 3. An information processing apparatus comprising at least one computer system (real resource), logically dividing the real resource to provide a plurality of logical computer systems, and using the real resource of each logical computer system. Based on the first means for measuring the situation, the logical performance of each logical computer implicitly determined in advance, and the actual resource usage of each logical computer system measured by the first means, Second means for determining whether or not degeneration is possible, and when it is determined that degeneration of the real resource is possible by the second means, degeneration of the real resource is performed and the power supply of the degenerated portion is reduced. Third to reduce
An information processing apparatus comprising: