JPH09172616A - Video down conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a video down conversion device having a superior function by means of simple configuration by adopting prescribed architecture adding interpolators. SOLUTION: The interpolators 30 and 50 receive the pixel of an input video signal by an input pixel rate, execute an interpolating processing and generate an output data value where an active output pixel value and a dummy pixel value coexist by the input pixel rate. Control logic generates an active enable signal being the signal having a first state where the active output pixel value is generated and the second state where the dummy pixel value is generated. A signal processing device is provided with an input latch latching an output data value from the interpolator only when the active enable signal is in the first state. A buffer memory 150 buffers data outputted from the signal processing device and outputs it by the pixel rate of an output video signal with low precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a conversion (video downgrade conversion) device.

[0002]

2. Description of the Related Art A video down-conversion apparatus has a higher definition input video signal and a smaller number of active scan lines than the input video signal, and / or It is an apparatus for converting an output video signal having a lower definition, in which the number of active pixels per scan line is small. This spatial transformation is performed by separate interpolation filters, a horizontal digital interpolation filter and a vertical digital interpolation filter.
Therefore, the spatial transformation from input resolution to output resolution is
At least two-step processing is required. The video down conversion device receives at its input pixel data at the data rate of the input signal. The first of the two interpolation filters (horizontal interpolation filter or vertical interpolation filter) produces intermediate pixel data. The data rate of the intermediate pixel data is lower than the data rate of the input signal, but higher than the required data rate of the output video signal. The intermediate pixel data is data obtained by subsampling in only one direction of space. The second interpolation filter (vertical interpolation filter or horizontal interpolation filter) is the required output signal data rate,
Send pixel data. Therefore, the video down conversion apparatus requires at least three kinds of clock signals to control the data input process, the interpolation process, and the subsequent signal process for the down-converted video signal. Generating and distributing three kinds of clock signals is troublesome. In addition, buffer memory would be required for each processing stage to receive data at one clock rate, process the data, and then output at another clock rate.

Further, in the video down conversion, the input video signal received is a signal of a high definition video signal format of, for example, 1125 lines or 1250 lines, and the output video signal generated for it is, for example, 525. In some cases, it is a signal of a video signal format of normal definition of line or 625 lines. When performing down conversion for converting from a high-definition format with 1125 scan lines to a format with 525 low-definition lines, the high-definition input video signal is a 60 Hz field.・
It may be a signal from a high definition signal source with a rate. In such a case, if the requested output video signal is a 525 line NTSC video signal,
59.9 by changing the field rate by one thousandth
It needs to be 4 Hz. In order to change the field rate in this way, it is convenient to use a field drop converter in which the field of the video signal is dropped every few seconds. However, the signal output from such a field drop converter will have its field polarity abruptly inverted when one field is dropped. The effect of this polarity reversal is particularly remarkable in a video signal format in which the number of active scanning lines is an odd number. This is because in such a video signal format, the number of scanning lines in one of the two fields forming one frame is one more than the number of scanning lines in the other field.

[0004]

According to one aspect of the present invention, an input video signal having a higher definition has a smaller number of active scanning lines than the input video signal and / or the input video signal. The present invention provides a video down-conversion device which has a smaller number of active pixels per scan line and which is converted into an output video signal with lower definition. An interpolator that receives pixels of an input video signal at an input pixel rate and executes an interpolation process to generate an output data value in which active output pixel values and dummy pixel values are mixed at the input pixel rate, A signal associated with an output data value generated by the interpolator, the first signal being generated when an active output pixel value is generated. State and a second state when a dummy pixel value is generated, the control logic generating an active enable signal, and a signal connected to receive the output data value generated by the interpolator. A processing device having an input latch for latching an output data value from the interpolator only when the active enable signal is in the first state; A video down-conversion apparatus comprising a buffer memory for temporarily storing data and outputting the data at a pixel rate of the output video signal having a lower definition.

The present invention addresses the above problems by providing a novel architecture for a video down converter.
The architecture provides an interpolator (eg, a horizontal interpolator, a vertical interpolator, or both).
When sending the output data, the output data is sent at the same data rate as the video data supplied to the input of the interpolator. As can be seen, some of the output data will be "dummy" data. This is because the output video signal requires a smaller number of output pixels. Therefore, use the active enable signal as a flag for those dummy data values to indicate that they are dummy data values, and this active enable signal latches the data value in subsequent signal processing devices. Whether or not it is controlled.

According to this configuration, each component for executing the processing operation can be operated at only one clock rate (clock rate related to the data rate of the input video signal), and thus the buffer is operated. As the memory, only one buffer memory that finally changes the clock rate for outputting the video signal is required. Therefore, according to this configuration, it is not necessary to prepare three or more clock signals in one down conversion device, and it is also necessary to provide each buffer memory corresponding to these clock signals. Absent.

Further, according to this configuration, when the down-conversion device is configured by using, for example, a CMOS logic in which the number of data transitions increases and the power consumption increases, the power consumption is significantly reduced. be able to. Because the active enable signal is the second
In the state (dummy state), the data transition is prohibited, and the ratio of the prohibited data transition is 1125: 5.
This is because in the case of 25 conversions, the number of data transitions is about 5/8, and the number of data transitions is dramatically reduced.

In the embodiment of the present invention, the active enable signal is used to control the latching operation of the input data of the series of signal processing devices connected in series. This allows the clocks used to latch the data in those signal processing devices.
The duration of some of the pulses will be extended, allowing the signal processing devices to operate according to the same basic clock signal as the clock signal of the input video signal.

According to another aspect of the invention, a video is generated by interpolating a scan line of a continuous series of output video fields to a scan line of an input video field corresponding to each of the output video fields. A down conversion device is provided, and this video down conversion device interpolates an input video field of any field polarity to generate each output field. Of the input video fields so that a continuous series of output video fields maintains a regular sequence of odd-even field polarities even in the presence of discontinuities in the field polarity sequence of the input video field. Video down featuring
It is a conversion device.

In order to cope with the occasional inversion of the field polarity in the input video signal, the vertical interpolator in the device according to the present invention uses the input video field whichever polarity the input video field has. An output video field having a specific polarity can be generated from the field. Therefore, a field drop converter can be placed upstream of this signal processing device, and the polarity reversal caused by the field drop converter is present in the video signal generated at the output of this signal processing device. It is supposed not to. However, according to this configuration, it has been found that an unpleasant image disturbance may occur at the uppermost end and the lowermost end of the screen.

The problem that may occur is that from the larger input field (that is, the one with more scanning lines) to the larger (also with one more scanning lines). ) By creating an output field and aligning the position of the output field with the position of the input field, the larger output field actually creates the output field when the polarity of the input field is reversed. It is out of the (smaller) input field from which you do. The top and bottom scanlines of the output field would then be generated, at least in part, from the black scanlines of the inactive area of the input field. On the other hand, if the polarities of the input fields are opposite, the scan lines at the top and bottom of the output field are generated from the scan lines of the active area of the input field. Therefore, when the polarity reversal of the input field occurs, the brightness of the scanning lines at the uppermost end and the lowermost end of the larger output field changes. Because, at that time, the scan lines are changed from the active scan line generated by the interpolation process to the inactive scan line generated by the interpolation process, or vice versa. .

In response to this problem, in some embodiments of the present invention, the top and bottom scanlines of the output frame (ie, the top and bottom scanlines of the larger output field). The position is set to a scanning line other than the uppermost end and the lowermost end of the input frame (that is, a scanning line that is inside at least one scanning line from the uppermost end and the lowermost end of the input frame).
It is dealt with by aligning with the position of. In this case, the output image is cut off at the upper and lower ends, although it is very small. However, this is still considered to be better than the disturbing brightness variation every few seconds that appears at the top and bottom of each inversion of the input polarity.

In one embodiment, the positions of the top and bottom scan lines of the larger output field are:
The larger input field can be aligned with the second scanning line from the uppermost end and the second scanning line from the lowermost end, so that even if a change in the field polarity occurs in the input video signal, the larger scanning field can be aligned. It ensures that the output field does not extend beyond the input field from which it was generated. On the other hand, especially in other embodiments in which the above-mentioned image disturbance appears over several scan lines due to the use of a multi-tap vertical interpolation filter,
The positions of the scanning lines at the uppermost end and the lowermost end of the larger output field can be aligned with the positions of the scanning lines inward by n scanning lines from the uppermost end and the lowermost end of the input frame.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the accompanying drawings,
The present invention will be described with reference to its specific examples. In the attached drawings, corresponding elements have similar reference numerals. FIG. 1 is a block diagram of a down conversion device.
The apparatus of FIG. 1 is entirely configured by a single application specific integrated circuit (ASIC) 10 except for a FIFO memory 150. The down conversion device receives a high definition (HD) digital video signal as its input and produces a standard definition (SD) or normal definition digital video signal at its output. In this downgrade conversion process, horizontal down conversion is performed first, and then vertical down conversion is performed. Here, it is assumed that the input video signal and the output video signal have the same frame rate or field rate, and no temporal conversion is performed.
When the spatial conversion is completed, the video signal data is subsequently subjected to image enhancement (image quality improvement), color mapping, and a formatting process suitable for the required output signal signal system.

Using the apparatus of FIG. 1, various system conversions can be performed under the control of configuration data described later. The conversion modes are as follows. 1035 lines / 2: 1 interlace → 485 lines / 2: 1 interlace 1080 lines / 2: 1 interlace → 485 lines / 2: 1 interlace 1035 lines / 2: 1 interlace → 364 lines / 2: 1 interlace Race 1080 lines / 2: 1 interlace → 364 lines / 2: 1 interlace 1152 lines / 2: 1 interlace → 576 lines / 2: 1 interlace 1035 lines / 2: 1 interlace → 485 lines / 1: 1 Sequential scanning 1080 lines / 2: 1 interlace → 485 lines / 1: 1 sequential scan

High-definition input video data is first converted into a half-band luminance signal (C) filter (horizontal filter) 20.
To the horizontal interpolator 30. FIG. 2 shows these two stages 20, 30 in more detail. FIG. 2 shows how the luminance data stream (Y) and the multiplexed chrominance data stream (PbPr) are input to this down-conversion device, and how these data streams are down-converted. It shows how each is handled in the conversion device. In particular, only the luminance data stream is supplied to the half-band horizontal filter 20. The multiplexed color data stream is first input to the demultiplexer 22 where the Pb signal and P
r signal. The separated signals Pb and Pr are delayed by the respective delay elements 24, thereby matching the delay in the half-band horizontal filter 20. The luminance data filtered by the half-band horizontal filter 20 and the separated and delayed color data are then followed by three horizontal interpolators 30 ', 30 "and 3".
Input to each 0 ″.

The reason why the processing in the first stage is as described above is that in the so-called 4: 2: 2 high definition digital video signal of the signal system having 1125 scanning lines,
The data rate of the luminance data stream (Y) is 74
MHz, two color data streams Pb and P
The data rate of r is 37 MHz (the composite color data stream obtained by multiplexing these two color data streams has a data rate of 74 MHz). Integrated circuits handling a 74 MHz data stream are technically more difficult to manufacture and generally consume more power than integrated circuits handling a 37 MHz data stream. Therefore, the luminance data is first subjected to a half-band horizontal filtering process and a data thinning process (not shown) to thereby set the data rate of the luminance data to 37 MHz. This is the only half-band horizontal filter 20 that has to operate at a data rate of 74 MHz in the signal path through which the luminance data passes. (Note that the half-band horizontal filter 20 is not an architecture (configuration) using multiplication and addition but an architecture using shift and addition so as to be suitable for operation at this high processing speed).

Similarly, the 74 MHz multiplexed color data stream PbPr is first separated (at the demultiplexer 22) into two separate 37 MHz data streams into two separate 37 MHz data streams. On the other hand, the subsequent processing is performed. This allows the color data to pass through 74 in the signal path through.
Only the demultiplexer 22 has to operate at the MHz data rate. Another advantage of the above configuration is that all the data processing after the half band horizontal filtering processing and the data thinning processing on the luminance data are performed on the luminance data stream and the color data stream having the same data rate. That is, that is, all subsequent data processing is performed on the 4: 4: 4 video signal. This provides flexibility in that the output signal can be generated by either the 4: 4: 4 method or the 4: 2: 2 method. As a further advantage of the above configuration, the three horizontal interpolators 30 ', 30 ", 3
There is a case where all of the 0 ″ 's can have the completely same configuration. In designing the ASIC, this greatly contributes to simplification of the design work.

The description will be continued with reference to FIG. 1 again. In addition,
In FIG. 1, only one signal path is shown out of three parallel signal paths (each signal path of Y data, Pb data, and Pr data) in consideration of legibility. The purpose of the horizontal interpolator 30 is to transform from the pixels of the scan line in the (high definition) signaling on the input side to the required pixels of the scan line in the (standard definition) signaling on the output side. To do. The horizontal interpolator 30 is capable of performing this conversion in two ways: a "compression indentation" mode and an "edge cut-off" mode. In the compressed indent mode, the image contents of the pixels of the input scan line are used in full to produce the pixels of the output scan line corresponding to the input scan line. With this mode,
When the aspect ratio of the output video signal is different from the aspect ratio of the input video signal, horizontal compression distortion occurs in the image. On the other hand, in the edge cutoff mode, when the output scan line is generated, the image components at one end or both ends of each scan line are partially discarded.
By appropriately setting the edge cutoff width and compensating for the difference between the input aspect ratio and the output aspect ratio, it is possible to prevent horizontal compression distortion from occurring in the output image. Therefore, the horizontal interpolator 30 may generate the pixels of the output scan line from only some of the pixels of the input scan line, and may also generate all the pixels of the input scan line. Can also generate multiple pixels of the output scan line from. Horizontal interpolator 3
0 can introduce a quarter pixel offset in the edge cropping mode, thereby adjusting the horizontal position of the output image (truncated image) relative to each input image. be able to. On the other hand, in the compression push mode, this horizontal adjustment is accomplished by simply lowering the sample rate of the pixels in the scan line, which is typically about three quarters.

In vertical conversion, vertical interpolation processing is first executed, and then scanning line drop processing for dropping scanning lines is executed. The output of the horizontal interpolator 30 is the scan line 12
Input to the scanning line (line) delay device 40 that delays by this amount,
From there, it is further supplied to a vertical interpolator 50 having 13 taps. Vertical interpolator 50 produces an output scan line of pixels at the same scan line rate as the input scan line. However, as will be described in detail later, only some of the scan lines output from the vertical interpolator 30 are treated as "active" scan lines, and the other scan lines are "dummy" scan lines. Discarded as a wire.

An image enhancer 60 is connected to the output of the vertical interpolator 50, but the image enhancer 60 may or may not be connected. This image enhancer 60
Will be described in more detail later with reference to FIG.
The video data output from the image enhancer 60 is YC.
It is input to the YC-RGB matrix 70 having a general configuration for converting (luminance / color) into RGB (red / green / blue). The YC-RGB matrix 70 outputs
Generate red, green, and blue component video signals. The component video signals (or the color bar test signal generated by the color bar test generator 80) are input to the inverse gamma converter 90. The inverse gamma converter 90 is a converter that applies an inverse gamma correction function to the signal. The signal to which the inverse gamma conversion correction function has been applied is subsequently input to the colorimetric converter 100, and from there is further supplied to the gamma converter 110. These inverse gamma converters 90,
The purpose of the array of converters consisting of the colorimetric converter 100 and the gamma converter 110 is to first undo the gamma conversion performed according to the high definition format, and subsequently to the red, green and blue color references. From the color standard for high definition formats to the color standard for standard definition formats,
And finally, the gamma correction that conforms to the standard definition format is applied. (Note that,
High definition video signals and standard definition video signals usually have different gamma corrections, color or phosphor references applied). According to this configuration, it is also possible to apply basic R, G, and B component signals instead of colorimetric conversion and R, G, and B component signals that have undergone non-linear gamma correction processing.

The output of the gamma converter 110 is input to the FIFO memory 150, which is an external component. FIF
The purpose of the O memory 150 is to enable input of video data at the clock rate of the input video signal and output of video data at the clock rate of the output video signal. Therefore, in this case, the data is stored in the FIFO memory 150.
The clock rate for writing data to the input video signal is the clock rate for the data rate of the input video signal, and the clock rate for reading data from the FIFO memory 150 is the clock rate for the required output video signal format. is there. Further, by setting the position where the FIFO memory 150 is externally connected to this circuit to this position, the external colorimetric converter or the image enhancer is processed by using the connection portion for connecting the FIFO memory 150. It is also possible to interpose in the flow of.

The output of the FIFO memory 150 is the ASIC
RG that can be returned to 10 and can be arbitrarily connected
It is input to the B-YC matrix 120. This RGB-
Depending on whether the YC matrix 120 is connected or not, the standard definition output can be either RGB format output or YC format output. RGB-YC matrix 1
After 20 is connected a half-band color signal (C) filter 130 which can also be arbitrarily connected. If the filter 130 were not included in the circuit, the output would be in 4: 4: 4 format. On the other hand, the filter 13
With 0s included in the circuit, the output is in 4: 2: 2 format because the two color data streams are halfband filtered and subsampled. In either case, the signal is finally sent to the output multiplexer / blanking inserter 140.

FIG. 3 is a schematic diagram for explaining the operation of the vertical interpolator 50. Generally, the vertical position of the output scan line and the vertical position of the input scan line do not match. Depending on how the current output scan line is relative to the input scan line, the set of filter coefficients required for the filtering process performed by the vertical interpolator 50 will be different. In this system, 32 possible filter coefficients are prepared, so that the vertical position of the output scan line can be specified with an accuracy of 1/32 of the interval between the input scan lines. These 32 sets of filter coefficients are not stored in the vertical interpolator 50, but the sets of coefficients suitable for each output scan line are vertically interpolated during the horizontal blanking period immediately preceding each output scan line. The register of the container 50 is loaded. To store all the sets of filter coefficients needed to generate an output field, a bank of thirty-two sets of registers is required, with thirteen 10-bit registers as one set. With this configuration, it is not necessary to equip the vertical interpolator with such a large capacity bank.

Therefore, the vertical interpolator 50 will select the proper set of sequences to load into the vertical interpolator 50 registers during the horizontal blanking interval for the next output scan line's input scan line. A counter for holding a periodic count value of the relative position is provided. Here, this count value is represented by the modulo 32 calculation corresponding to a set of 32 coefficients. This periodic count value is used as an address signal in a control logic (not shown in FIG.
0, and is schematically illustrated in FIG. 4) to specify the proper set of coefficients to send to the vertical interpolator 50 during the next horizontal blanking interval. To be done. FIG. 3 is a diagram showing a simple concrete example of the above processing. In this example, there are three sets of filter coefficients to be used, and correspondingly the address values to be used also have three values (A = 0, 1, 2). As is apparent from FIG. 3, the address value sent to the control logic is determined according to the relative vertical position of the current output scan line with respect to the input scan line.

FIG. 4 is a diagram schematically showing a control logic that controls the updating operation of the filter coefficient of the vertical interpolator 50 and is in charge of many other control items.
The control logic includes two memories that store the above filter coefficients as well as other configuration data associated with the various devices shown in FIG. These memories are dual port random access memories (RA
M) 200 and read only memory (ROM) 210. The address generator 220 controls the data read / write operation with respect to the dual port RAM 200 and the data read operation from the ROM 210.

Dual port RAM 200 and ROM 2
The contents to be stored in each of 10 will be described in more detail later, and will be described here only briefly. R
The OM210 has a possible operating mode of this down conversion device (various conversion modes listed above).
Of the filter coefficients of the horizontal and vertical interpolators corresponding to each of the above, and various possible configuration data for devices such as image enhancers and colorimetric converters. The ROM 210 further stores a 10-byte configuration word that defines the default operation mode of this down conversion device. Dual port RAM20
Similarly to the structure of the ROM 210, 0 also includes one set of filter coefficients for the horizontal interpolator and the vertical interpolator, one set of configuration data for the image enhancer, colorimetric converter, and other devices, and a 10-byte configuration. The storage capacity is such that only one word can be stored.

The operation of those memories will be described. First, a default (default) operation mode (for example, a high-definition input video signal having 1125 scanning lines and 1035 active scanning lines is converted into an output video signal of an interlaced system having 525 scanning lines, It is not necessary to load the dual port RAM 200 when an operation mode for converting in the compression push mode) is requested. Which of the various coefficient sets described above should be used is specified by the 10-byte configuration word permanently written in ROM 210, and the required coefficient is RO
It is read from M210. On the other hand, if a different mode of operation is required that only uses another coefficient stored in ROM 210, another 10-byte configuration word different from that corresponding to the default mode of operation will be sent to RAM 200. Just write to.
Therefore, a pointer that points to a set of non-default coefficients and non-default configuration data stored in the ROM 210 is provided.
As still another case, when an operation mode in which data such as a coefficient set stored in the ROM 210 cannot be used is requested, a plurality of alternative coefficients corresponding to the operation mode are stored in the RAM 200, This RAM20
10-byte configuration stored in 0
The alternative coefficient may be indicated by a word.

Data can be loaded (stored) into the RAM 200 either through the serial interface 230 or through the parallel interface 240. Both the data read from the RAM 200 and the data read from the ROM 210 are supplied to the multiplexer (mux) 250. The multiplexer 250 selects one of the data stored in the RAM 200 and the data stored in the ROM 210. This selection may be performed according to the 10-byte configuration word stored in the ROM 210. However, when the RAM 200 stores the configuration word in 10 bytes, that is prioritized. According to the configuration word of

The various modules shown in FIG. 1, including the horizontal interpolator, vertical interpolator, etc., are interconnected via a common data bus and a common address bus. Whenever it becomes necessary to update the configuration or coefficient data for any of these modules, the control logic will send the correct address on the address bus and place the corresponding data on the data bus. Send out. Generally, the coefficient and control data are updated during the vertical blanking period,
However, the coefficient of the vertical interpolator is an exception, and the coefficient of the vertical interpolator is updated during the horizontal blanking period.

FIG. 5 is a schematic diagram of the image enhancer 60. The basic function of the image enhancer 60 is to improve the reproducibility of the details (details) of the image by amplifying the high frequency component of the video signal. Here, for example, Sony DVW-700 / 700P type and BVW-D600 /
It uses a technique very similar to that used in the D600P camera recorder. The luminance signal is the only target to be subjected to the processing for improving the image quality. The color component signal is simply added with a delay to match the delay introduced into the luminance signal by the delay element 300. The luminance signal Y is output to the delay element 310 and the level-dependent processing device 320.
Are input in parallel to and. The level-dependent processing device 320
A non-linear level-dependent function that changes according to the brightness level is applied to the brightness signal Y, and the non-linear function is
It is set to reduce the enhancement in the dark area,
The reason is that the gamma-corrected luminance signal contains more noise in the dark region than in the bright region. This non-linear level-dependent function peaks the input pixel value up to, for example, 192 (in the range of the input pixel value extending to 1024, that is, 10 bits), and sets the value of the peaked signal at a predetermined rate (for example, 1/16). ), The product is rounded down, and the value of the reduced signal is subtracted from the value of the original signal.

Next, the luminance signal subjected to the above processing is subjected to horizontal and vertical high-pass filter processing and band-pass filter processing. By these processing,
The detail component (high frequency component) is emphasized, and so-called cross color is prevented when the video signal generated by the down conversion is finally encoded according to the NTSC system or the PAL system. By supplying the value of the horizontal / vertical detail ratio to the multiplier 330, the ratio of the degree of detail enhancement in the horizontal direction and the degree of detail enhancement in the vertical direction can be adjusted. After this,
A process of applying another non-linear function called "crispanning" is applied to the signals combined by the adder. Crispanning is a process for reducing the amount of detail added to a small object and for reducing the amount of noise included in a detail signal. In order to achieve this, the threshold applied to the detail signal is set, and the detail gain is set to zero when the detail signal is below the threshold. This block uses yet another function, which is to cap the detail signal to limit the maximum amount of added detail. In order to realize this function, it is sufficient to subject the input signal to capping processing with a variable limit level, and subtract the capped processing signal from the original signal. It should be noted that the level of the detail signal can be adjusted by another multiplier 340 provided at a position immediately before the above-mentioned detail signal is added (350) to the delayed original luminance signal.

FIG. 6 is a schematic diagram of the gamma converter, and FIG.
FIG. 8 is a diagram showing a necessary transfer function of gamma conversion, and FIG.
Is a schematic diagram of the inverse gamma converter, and FIG. 9 is a diagram showing a necessary transfer function of the inverse gamma conversion. Both the gamma converter and the inverse gamma converter have a look-up table (LUT) containing 64 values addressed by the most significant 6 bits of each pixel value. This address causes the difference signal and the base signal to be delivered as outputs. The product of the least significant 7 bits of each input pixel value and the difference signal is taken and the product is added to the base signal, thereby producing the output pixel value. This process is performed on the red, green, and blue pixel values in parallel. The values of the difference signal and the base signal are chosen to approximate the required curves shown in FIGS.

FIG. 10 is a table showing the contents stored in the control ROM 210. In the ROM 210, the first 10 bytes “0x000” to “0x00” are stored.
9 "has a 10-byte configuration word stored, followed by the next. Two sets of coefficients for horizontal interpolation (corresponding to the cut-off mode and compression push mode respectively), four sets of vertical interpolation coefficients, two sets of inverse gamma coefficients, two sets of output gamma correction coefficients,
And three sets of colorimetric conversion coefficients.

The 10-byte configuration word stored in the ROM 210 is equivalent to one of the 2 × 4 × 2 × 2 × 3 operating modes equal to the number of permutations of the coefficient sets listed above. The mode is specified as the default operating mode. The coefficients stored in ROM 210 are used, but when a non-default mode of operation is required, the 10-byte configuration word to be used instead is the corresponding address in RAM 200, as shown in FIG. Just load it in. When an operation mode obtained by further changing the stored operation mode is requested, an address area corresponding to each coefficient in the RAM 200 (see FIG. 11).
Then, load another coefficient value into the RAM200.
The 10-byte configuration word in the file may be set accordingly to indicate that those values should be used.

Configuration of RAM 200
The selection of a word or the configuration word of ROM 210 to be used detects whether the serial port or parallel port for external data transfer to dual port RAM 200 is enabled (enabled). Then, the configuration word of the RAM 200 is used), or the control input (not shown) is externally input to the control logic. As another embodiment, the selection may be performed by detecting whether or not a configuration word has been written in the RAM 200 since the down conversion device was previously turned on. Good.

FIG. 12 is a schematic timing diagram for explaining how the active data enable signal is used in the down conversion device of FIG. As previously mentioned, the vertical interpolator, in response to receiving one scanline of pixels at its input,
A pixel for one scan line is generated at the output. Also similarly, the horizontal interpolator produces pixel values at its output at the same data rate as the pixel values it receives at its input. The reason why the circuit is configured in this way is that all the processing devices existing from the horizontal interpolator to immediately before the external FIFO memory can be operated at the same clock speed. This eliminates the need to have a clock different from the clock for the input for the output from the horizontal interpolator and a clock different from them for the output of the vertical interpolator. .

With this arrangement, however, some of the pixel values output by the horizontal interpolator become "dummy" values that are unnecessary for the output image, and likewise from the pixels output by the vertical interpolator. Some of the scan lines
The entire pixel of that scan line becomes an unwanted "dummy" scan line. Therefore, the "active enable" signal is used to separate the data value that is really needed from the dummy data value. The active enable signal is generated by a counter (not shown) attached to the horizontal interpolator and a counter (not shown) attached to the vertical interpolator. For example, if the subsampling ratio when the horizontal interpolator subsamples is 3/4, the horizontal interpolator sets the active enable flag to the high state once every four pixel values are output. (Thus indicating that it is dummy data). Similarly, if the vertical conversion ratio is about 1/2, the vertical interpolator flags that approximately one-half of the scanlines it produces are "dummy" scanlines. As a result, as a whole, about 3/8 of the pixel values generated and output by the horizontal interpolator and the vertical interpolator are
The flag will indicate "active". Actually, in order to generate the active enable signal, a logical OR combination (logical sum) of the active enable signal generated for the horizontal interpolation processing and the active enable signal generated for the vertical interpolation processing is taken. I am trying to generate it.

The first stage operation of any processing stage (processing device) from the horizontal interpolator to the external FIFO memory of the down conversion apparatus of FIG. 1 is to latch (sample) input data according to a common clock signal. Is. The active enable signal is provided to all of the processing devices in parallel (ie, without latching or delay). When its active enable signal goes high, quite simply, none of these processing devices will currently have their inputs latched, and they will retain their previous values. This will result in the extension of some of the clock cycles for those processing devices that follow the horizontal interpolator.

FIG. 12 is a diagram for explaining the above process.
It is. In the figure, D0, D1, D2, ... D7
Is the active pixel value. X represents a dummy value generated for every four pixels output from the horizontal interpolator. The second line from the top of FIG. 12 is
The active enable signal is shown. When the data output by the horizontal interpolator is latched by the next-stage processing device that receives it and has a dummy value ×, the latch is blocked by the active enable signal, and The values D2 and D5 are held for two clock cycles and the process is stopped for a while. Similarly, on the next scan line, the value D
1 and the value D4 are held for two clock cycles.

FIG. 13 schematically shows a part of the operation of the vertical interpolator. One possible use of the down conversion device of FIG. 1 is that the high definition input video signal is a signal from a high definition signal source having a field rate of 60 Hz. Further, in that case, the required output video signal is 525 line NTSC.
If it is a video signal of the system, it is necessary to change its field rate by one thousandth to 59.94 Hz. In order to change the field rate in this way, a field drop converter in which the field of the video signal is dropped by one field every few seconds is used by connecting it to the upstream side of the down conversion device. It is convenient. However, the signal output from such a field drop converter will suddenly reverse the field polarity of the signal input to this down conversion device when one field is dropped. The effect of this polarity reversal is particularly remarkable in a video signal format having an odd number of active scanning lines, because in such a video signal format, two fields forming one frame are used. This is because the number of scanning lines in one of the fields is one more than the number of scanning lines in the other field.

In order to cope with the field polarity reversal that sometimes occurs in the input video signal, the vertical interpolator outputs an output having a specific polarity from the input video field regardless of the polarity of the input video field. The video field can be generated. This is achieved in this design in a very simple way because the vertical interpolator (specifically, the counter described with reference to FIG. 3) is
This is because, for each output scan line, a proper coefficient set for interpolation processing to be applied to the output scan line is automatically requested according to the relative position of the output scan line with respect to the input scan line. Therefore, the difference between the odd-numbered input field and the even-numbered input field regarding what coefficient should be requested as the interpolation processing coefficient is such that the positions of the input scan lines deviate from each other by ½ of the interval between the scan lines. It's just that.

However, it has been found that this alone may cause annoying image disturbance at the uppermost and lowermost edges of the screen. Therefore, in order to avoid this problem,
Perform the following steps. The problem that may occur is that the larger input field (that is, the one having more scanning lines) to the larger output field (also having the more scanning lines). And generate
If you align the position of the output field with the position of the input field, the larger output field actually becomes the source of the output field (the smaller one) when the polarity of the input field is reversed. It is out of the input field. As such, the top and bottom scanlines of the output field will be generated, at least in part, from the black scanlines of the inactive area of the input field. On the other hand, if the polarities of the input fields are opposite, the uppermost and lowermost scan lines of the output field are generated from the scan lines of the active area of the input field. Therefore, when the polarity reversal of the input field occurs, the brightness of the scanning lines at the uppermost end and the lowermost end of the larger output field changes. Because, at that time, the scan lines are changed from the active scan line generated by the interpolation process to the inactive scan line generated by the interpolation process, or vice versa. .

In this system, the problem is that the position of the uppermost and lowermost scan lines of the output frame (ie, the uppermost and lowermost scan lines of the larger output field) is set to the larger input field. It is dealt with by aligning with the position of the scanning line other than the uppermost end and the lowermost end of the input frame (that is, the scanning line that is inside at least one scanning line from the uppermost end and the lowermost end of the input frame). In this case, the output image is cut off at the upper and lower ends, although it is very small. However, this is considered to be better than the disturbing brightness variation once every few seconds that appears at the top and bottom at every inversion of the input polarity.

FIG. 13 shows a concrete example of the technique described above. In FIG. 13A, the input fields F0 and F1 of the high definition video signal are converted into the output fields F0 and F1 of the video signal of lower resolution, respectively. In particular, the output field F0 is completely generated only from the input field F0, and the output field F1 is completely generated only from the input field F1. 13b is a similar view, but the polarities of the input fields F0 'and F1' are opposite to those of FIG. 13a. The output field F0 is completely generated from only the input field F0 ', and the output field F1 is completely generated from only the input field F1'. Since the positions of the uppermost and lowermost scanning lines of the larger output field F0 are aligned with the positions of the second uppermost scanning line and the second lowermost scanning line of the larger input field, Even if the field polarity changes in the video signal, the larger output field F0
But does not extend beyond the input field from which it was generated.

FIGS. 14, 15 and 16 are diagrams showing three specific examples of usage of the apparatus of FIG. Especially,
FIG. 14 is a diagram schematically showing a video camera incorporating the down conversion device of FIG.
Is a diagram schematically showing a video camera connected to the down conversion device of FIG. 1, and FIG. 16 is
Video with built-in down conversion device of Fig. 1
It is the figure which showed typically the tape recorder (VTR). 14, the video camera 400 includes a high-definition image sensor 410, and the image sensor 410 generates a high-definition video signal. A down-conversion device 420 of the type described above is interposed in the parallel signal path (although a video converter for analog-to-digital conversion may be provided in the signal path if necessary). Good), thereby video camera 4
00 makes it possible to output a standard definition video signal and a high definition video signal substantially simultaneously. If necessary, a delay element may be inserted in the path of the high-definition video signal to introduce a delay to match the delay associated with the processing of the down conversion device 420.

FIG. 15 illustrates a similar arrangement including a video camera which produces a high definition 60 Hz video signal. Field drop type temporal converter (field drop converter) 430
Is connected between the high definition video camera output and the down conversion device 420. field·
The drop converter 430 drops the field of the video signal by one field every a few seconds, thereby reducing the field rate of the video signal from 60 Hz to 5 Hz.
It operates to change to 9.94 Hz (equivalent to a thousandth change). This causes a discontinuity in the field polarity sequence of the signal supplied to the down conversion device 420, which discontinuity is compensated by the operation of the down conversion device 420 as described above.

Finally, FIG. 16 shows a high-definition video recording / playback apparatus 440, which also incorporates a down-conversion apparatus 420, whereby a high-definition video recording / playback apparatus 440 is provided. The output of the standard format and the output of the standard definition format are generated substantially at the same time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a down conversion device.

2 is a block diagram of an input stage and a horizontal interpolation stage of the down conversion device of FIG.

FIG. 3 is a schematic diagram for explaining a coefficient address generation operation by the vertical interpolator of FIG.

FIG. 4 is a block diagram of a controller not shown in FIG.

5 is a block diagram of the image enhancer of FIG.

6 is a block diagram of the gamma converter of FIG.

7 is a schematic graph showing the characteristics of the gamma converter of FIG.

FIG. 8 is a block diagram of the inverse gamma converter of FIG.

9 is a schematic graph showing characteristics of the inverse gamma converter of FIG.

10 is a table showing the contents stored in a control read only memory (ROM) in the control device of FIG.

11 is a chart showing contents stored in a control random access memory (RAM) in the control device of FIG. 4. FIG.

FIG. 12 is a schematic timing diagram for explaining an active data enable signal.

FIG. 13 is a schematic explanatory diagram for explaining the operation of the vertical interpolator of the apparatus in FIG.

14 is a schematic diagram showing a video camera incorporating the device of FIG. 1. FIG.

FIG. 15 is a schematic diagram showing a video camera connected to the apparatus of FIG.

16 is a schematic diagram showing a video tape recorder incorporating the device of FIG.

[Explanation of symbols]

30 horizontal interpolator, 50 vertical interpolator, 150 FIF
O memory, 400 video camera, 420 down conversion device, 440 video recording device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Andrew Campbell United Kingdom Sally, Yateley, Mason Claus 3 (72) Inventor James Edward Burns United Kingdom Hampshire, Basingstoke, Old Basing, Hatch Lane 81 (72) Inventor Ahmad Sajadian Wiltshire, Swindon, Woodall Park, Callaway Drive 8

Claims (11)

[Claims] 1. A higher definition input video signal has a smaller number of active scanning lines than the input video signal,
And / or a video down-conversion device for converting the input video signal into an output video signal having a lower definition in which the number of active pixels per scanning line is smaller, and the pixels of the input video signal At an input pixel rate and performing an interpolation process to generate an output data value in which active output pixel values and dummy pixel values are mixed at the input pixel rate, and the interpolator generates A signal associated with the output data value that is to be output when the active output pixel value is generated.
Control logic for generating an active enable signal, which is a signal having a state and a second state when a dummy pixel value is generated; and a signal connected to receive the output data value generated by the interpolator. A processing device, the active device
A signal processing device having an input latch for latching an output data value from the interpolator only when an enable signal is in the first state, and buffering the data output from the signal processing device, and the buffered data And a buffer memory for outputting at a pixel rate of the output video signal having a lower definition. 2. At least one further signal processing device serially connected to the signal processing device for processing pixel values output by the signal processing device, each of the further signal processing devices comprising: 2. The video down conversion device according to claim 1, further comprising an input latch that latches a pixel value received only when the active enable signal is in the first state. 3. A horizontal interpolator and a vertical interpolator, each having logic for generating a partial active enable signal, and the active enable by logically combining the two partial active enable signals. Video down conversion device according to claim 1 or 2, comprising means for generating a signal. 4. A video down-conversion device for generating a continuous series of output video field scan lines by interpolating scan lines of an input video field corresponding to each of the output video fields. Even if it is an input video field of field polarity, it selectively operates so that each input field can be generated by subjecting the input video field to interpolation processing.
Accordingly, a video down-conversion device that enables a continuous series of output video fields to maintain a regular odd-even field polarity sequence even if a discontinuity exists in the field polarity sequence of the input video field. 5. The video according to claim 4, wherein the positions of the active scan lines at the top and bottom of the output frame are aligned with the positions of active scan lines other than the active scan lines at the top and bottom of the input frame.・ Down conversion device. 6. The video down-conversion apparatus according to claim 4, wherein the output video field has a field rate of 59.94 Hz. 7. The video down conversion apparatus according to claim 6, wherein the output video field is a field of a video signal adopting a signal system having 525 scanning lines. 8. The field of the input video field
Video down according to claim 6 or 7, wherein the rate is 59.94 Hz and the input video field is generated via a mode converter that temporally drops the field from a video signal source with a field rate of 60 Hz.・
Conversion device. 9. A video down-conversion device for generating a continuous series of scan lines of an output video field by interpolating scan lines of an input video field corresponding to each of the output video fields. A video down conversion device in which the positions of the active scan lines at the uppermost and lowermost ends are aligned with the positions of active scanlines other than the active scanlines at the uppermost and lowermost ends of the input frame. 10. A video camera comprising the video down-conversion device according to claim 1. Description: 11. A video recording device comprising the video down-conversion device according to claim 1. Description: