JPH09163261A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain multiscreen display with easy control without deteriorating picture quality with simple configuration by phase-synchronizing a second system clock used in a second decoding means with a synchronizing signal contained in a first picture signal. SOLUTION: TV broadcasting wave received by an antenna 23 is supplied to an NTSC decoder 25. A synchronization reproducing circuit 27 generates the system clock CK which is phase-synchronized with a horizontal synchronizing signal H is reproduced by the decoder 25. Picture data recorded in a digital video disk 28 is read, a picture component is supplied to an MPEG 2 decoder 33 and a decoding processing is executed based on the system clock CK so as to be converted into the picture signal. Therefore, the picture signal outputted from the decoder 33 becomes the one which is phase-synchronized with the horizontal synchronizing signal H of the picture signal outputted from the decoder 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an image display device for displaying an image signal transmitted by a (National Television System Committee) system and an image signal read from a DVD (Digital Video Disc) on a single screen in multiple screens.

[0002]

2. Description of the Related Art As is well known, in recent years, based on the progress of digital signal processing technology and semiconductor technology, digitized moving image signals are subjected to compression processing to be recorded at high density on an optical disc. A recording / reproducing system using a recording medium called a so-called DVD has been developed.
This DVD is a large-capacity recording medium capable of accommodating as much as 5 gigabytes of digital data on one side in a disc having the same diameter as the current CD (Compact Disc), and is expected to be developed in the future.

FIG. 6 shows this DVD reproducing system. That is, the DVD player 11 indicated by reference numeral 11 in the drawing has a tray 11a which is provided so as to be freely inserted and removed in the horizontal direction.
The DVD 12 is loaded via the DVD and played back, and the obtained image data is converted into an NTSC system image signal. The N output from the DVD player 11
By supplying the TSC system image signal to the standard system television receiver 14 via the cable 13,
The image will be displayed.

As a reproducing system for the DVD 12, as shown in FIG. 7, a type in which the DVD player 11 is built in the television receiver 14 is also considered. In this way, the DVD player 11
Since it becomes possible to share a part of the hardware between the part (1) and the television receiver 14, it is possible to make a structural and economic advantage.

FIG. 8 shows the details of the DVD player 11. That is, the DVD 12 is rotated and driven under the control of the disc controller 15, and the recorded digital image data is read via the optical pickup 16. The digital image data read by the optical pickup 16 is supplied to the data conversion circuit 17 and converted into a digital stream signal of a predetermined format, and then supplied to the program stream decoder 18.

This program stream decoder 18
Separates the time-division-multiplexed audio component and image component in the input stream into the audio decoder 19
To the MPEG (Moving Picture Image)
Coding Experts Group) 2 Output to the decoder 20. Then, the audio data and the image data decoded by the audio decoder 18 and the MPEG2 decoder 20 are supplied to an NTSC encoder 21 and subjected to an encoding process to be converted into an NTSC image signal and output. The cable 13 through the terminal 22
Sent to

By the way, in the above-described DVD 12 reproducing system, the data read from the DVD 12 is subjected to decoding processing by the audio decoder 19 and the MPEG2 decoder 20, and after being encoded by the NTSC encoder 21. Since the decoding process and the encoding process are repeated such that the NTSC decoding process is performed in the television receiver 14, there is a disadvantage that the image quality is deteriorated and the configuration is disadvantageous.

Further, the television receiver 14 is not used only for displaying the image signal output from the DVD player 11, but is normally standard (N
Of course, it is also used for receiving an image signal broadcast in the TSC system and displaying the image. That is, the television receiver 14 is supplied with both the image signal output from the DVD player 11 and the received image signal.

Then, as a matter of course, as shown in FIG. 9, the image signal output from the DVD player 11 and the received image signal are combined and, for example, the image signal output from the DVD player 11 is parented. Display as screen A,
To display the received image signal as a small screen B,
Or the television receiver 1 so that it may display on the contrary.
4 is required to perform multi-screen display.

However, the signal obtained by decoding the image signal read from the DVD 12 and the received NT signal
In order to combine a decoded image signal of the SC system and display it on a multi-screen at the same time, an image combining circuit adapted to each image is required, which causes a problem that complicated control is required. There is.

For example, in order to decode an image signal of the NTSC system, it is usually 4 of the color subcarrier frequency fsc.
A clock having a doubled frequency of 4 fsc = 14.3 MHz is used, but a clock having a frequency of 13.5 MHz is used for decoding the image signal read from the DVD 12. Therefore, complicated control is required to combine both image signals.

[0012]

As described above, in the conventional DVD reproducing system, since the decoding process and the encoding process are repeated for the data read from the DVD, the image quality is deteriorated and the data read from the DVD is read. Image signal obtained by decoding the signal and received NTS
There is a problem in that complicated control must be performed in order to combine a C system image signal with a decoded signal and display them on a multi-screen at the same time.

Therefore, the present invention has been made in consideration of the above circumstances, and provides an extremely good image display device capable of performing multi-screen display with easy control without causing deterioration of image quality. The purpose is to do.

[0014]

An image display device according to the present invention generates a first system clock based on a synchronization signal included in a first image signal, and based on the first system clock, a first system clock is generated. The first decoding means for decoding one image signal and the second image signal including the synchronization signal having the same frequency as the synchronization signal included in the first image signal are input, and the first system clock is A second decoding means for decoding the second image signal based on the second system clock having a different frequency, and a second system clock used by the second decoding means are used as the first image. For multi-screen display by synthesizing the synchronizing means for phase-locking with the synchronizing signal included in the signal and each signal output from the first and second decoding means at a timing based on the synchronizing signal. It is obtained by so and an image synthesizing means for generating a signal.

According to the above configuration, the second system clock used in the second decoding means is phase-synchronized with the synchronization signal included in the first image signal, so that the configuration is simple. Thus, it is possible to perform multi-screen display with easy control without deteriorating the image quality.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In FIG. 1, the television broadcast wave received by the antenna 23 is extracted as an NTSC baseband signal by being supplied to a tuner 24 and selecting a desired channel. The baseband signal output from the tuner 24 is supplied to the NTSC decoder 25 and subjected to a decoding process to be converted into an image signal.

In this case, the NTSC decoder 25 reproduces the color subcarrier fsc from the color burst component of the input baseband signal, and the frequency is 4 times the frequency 4fsc = 1.
The system clock CK having 4.3 MHz is generated and the decoding process of the baseband signal is executed.
Further, the NTSC decoder 25 also reproduces the horizontal synchronizing signal H and the vertical synchronizing signal V from the input baseband signal at the same time. And this NT
The image signal reproduced by the SC decoder 25, the horizontal synchronizing signal H, the vertical synchronizing signal V, and the system clock CK are all supplied to the image synthesizing circuit 26.

The horizontal synchronizing signal H and the vertical synchronizing signal V reproduced by the NTSC decoder 25 are supplied to a synchronous reproducing circuit 27. This synchronous reproduction circuit 27 has a system clock having a frequency of 13.5 MHz, which is in phase with the input horizontal synchronizing signal H and vertical synchronizing signal V and which is necessary for decoding the digital image data read from the DVD 28. Generating CK.

On the other hand, the recorded digital image data of the DVD 28 is read via the optical pickup 30 while being rotated and driven under the control of the disc controller 29. The digital image data read by the optical pickup 30 is supplied to a data conversion circuit 31, converted into a digital stream signal of a predetermined format, and then supplied to a program stream decoder 32.

This program stream decoder 32
Is 13.5 MHz generated by the synchronous reproduction circuit 27.
The audio component and the image component which are time-division multiplexed in the input stream are separated based on the system clock CK of. It should be noted that FIG. 1 shows only the image component and omits the audio component. Then, the image component output from the program stream decoder 32 is supplied to the MPEG2 decoder 33, and is subjected to decoding processing based on the 13.5 MHz system clock CK generated by the synchronous reproduction circuit 27.
It is converted into an image signal.

Therefore, the image signal output from the MPEG2 decoder 33 is in phase synchronization with the horizontal synchronizing signal H of the image signal output from the NTSC decoder 25. That is, the DVD 28 is the disk controller 29.
Or an F (not shown) built in the MPEG2 decoder 33.
The recorded image is restored by being controlled by IFO (First In First Out).

Therefore, 13.5 phase-synchronized with the horizontal synchronizing signal H of the image signal output from the NTSC decoder 25.
By operating the disk controller 29 and the MPEG2 decoder 33 with the system clock CK of MHz, it is possible to reproduce the DVD 28 without adding hardware or the like.

Further, in this MPEG2 decoder 33,
At the same time, the horizontal synchronizing signal H and the vertical synchronizing signal V are reproduced from the input image component. Then, the image signal reproduced by the MPEG2 decoder 33, the horizontal synchronizing signal H and the vertical synchronizing signal V, and the system clock CK generated by the synchronizing reproducing circuit 27 are both supplied to the image synthesizing circuit 26.

The data conversion circuit 31, the program stream decoder 32, and the MPEG2 decoder 33 are also provided.
The operation is controlled by the system controller 34. Then, the image synthesizing circuit 26 uses the NT
The image signal output from the SC decoder 25 and MPEG
The image signal output from the 2 decoder 33 is combined and output to the monitor 35.

FIG. 2 shows the details of the synchronous reproduction circuit 27. That is, VCO (Voltage Controlled Osc)
The system clock CK of 13.5 MHz output from the illator) 36 is output via the output terminal 37 to the program stream decoder 32 and the MPEG2 decoder 33.
And the frequency is supplied to the counter 38 and divided to the frequency of the horizontal synchronizing signal H.

The system clock CK frequency-divided by the counter 38 is supplied to the phase comparison circuit 39 and compared in phase with the horizontal synchronizing signal H supplied to the input terminal 40, and the phase error component thereof is supplied to the loop filter 41. Is output. Then, the loop filter 41 generates a DC voltage corresponding to the input phase error component and controls the oscillation frequency of the VCO 36, so that the system clock CK of 13.5 MHz phase-locked with the horizontal synchronizing signal H is obtained. Will be obtained.

In the above synchronous reproduction circuit 27, the NTSC
Using the horizontal synchronizing signal H obtained from the decoder 25, 1
Although the system clock CK of 3.5 MHz is phase-synchronized, this can also be achieved by using the color subcarrier fsc. In this case, the system clock CK of 14.3 MHz generated by the NTSC decoder 25 is equal to 910 times the frequency Fh of the horizontal synchronizing signal H, and the MPEG2
Since the system clock CK of 13.5 MHz used in the decoder 33 is equal to 858 times the frequency Fh of the horizontal synchronizing signal H, the system clock CK of 14.3 MHz generated by the NTSC decoder 25 is 910.
Phase synchronization can be achieved by phase-dividing the frequency-divided signal and the signal by dividing the 13.5 MHz system clock CK used in the MPEG2 decoder 33 by 858.

Next, FIG. 3 shows an example of the image synthesizing circuit 26. The image composition circuit 26 shown in FIG.
Is an image signal output from the NTSC decoder 25,
The image signal output from the MPEG2 decoder 33
Each is compressed horizontally, and 2 horizontally on the same screen.
The image synthesizing means when displaying in each equally divided area is shown.

That is, the image signal output from the NTSC decoder 25 is written in the memory 43 via the input terminal 42. The image signal output from the MPEG2 decoder 33 is written in the memory 45 via the input terminal 44. Each of these memories 43 and 45 has a capacity for storing a data amount corresponding to the number of pixels in the horizontal direction of the image signal, and writing or reading of the image signal is performed based on a timing signal output from the controller 46.

The controller 46 generates the timing signal based on the horizontal synchronizing signal H supplied to the input terminal 47. The frequency of the system clock CK of the image signal supplied to the input terminal 42 is 14.3 MHz, and the frequency of the system clock CK of the image signal supplied to the input terminal 44 is 13.5 MHz. Since they are respectively phase-synchronized, the relative phase relationship of the horizontal sync signal H is always constant.
Therefore, in the memories 43 and 45, the horizontal synchronization signal H
Both images can be combined by performing writing at the timing of 1 and reading at the timing of the same horizontal synchronizing signal H.

The image signals read from the memories 43 and 45 are selectively taken out to the output terminal 49 by the changeover switch 48 controlled by the controller 46 and outputted to the monitor 35. In this case, since the read timings from the memories 43 and 45 are synchronized, the image signal guided to the output terminal 49 via the changeover switch 48 is a combination of two image signals in the horizontal direction, and the NTSC The image signal output from the decoder 25 and the image signal output from the MPEG2 decoder 33 are displayed in respective areas obtained by halving the screen of the monitor 35 in the horizontal direction.

FIG. 4 shows another example of the image synthesizing circuit 26. The image composition circuit 2 shown in FIG.
6 displays the image signal output from the NTSC decoder 25 on the monitor 35 as a parent screen, and the MP is displayed in the parent screen.
The image synthesizing means is shown when the image signal output from the EG2 decoder 33 is displayed as a small screen or vice versa.

That is, the image signal output from the NTSC decoder 25 is supplied to the switch circuit 51 via the input terminal 50. The image signal output from the MPEG2 decoder 33 is supplied to the switch circuit 51 via the input terminal 52. The switch circuit 51 directly guides the image signal supplied to the input terminal 50 to the changeover switch 53, and guides the image signal supplied to the input terminal 52 to the changeover switch 53 via the memory 54. The second switching state in which the image signal supplied to the input terminal 52 is directly guided to the changeover switch 53 and the image signal supplied to the input terminal 50 is guided to the changeover switch 53 via the memory 54 is controlled.

Then, such switching of the switch circuit 51, switching of the changeover switch 53 and memory 54 are performed.
The writing / reading operation of the controller 5 is driven based on the horizontal synchronizing signal H supplied to the input terminal 55.
6. Therefore, the image signals supplied to the input terminal 50 are combined as a parent screen, the image signals supplied to the input terminal 52 are combined as a small screen, and the image signals supplied to the input terminal 52 are combined as a parent screen. It is possible to combine the image signals so that the image signal supplied to the input terminal 50 as a screen becomes a small screen, and output from the output terminal 57 to the monitor 35.

Originally, when synthesizing asynchronous images,
It was necessary to switch the control in consideration of the relative relationship of synchronization of the respective images, but as described above, by preliminarily phase-synchronizing the system clock CK of the processing unit that decodes the respective images, Images can be combined with a simple configuration.

As described above, in addition to the media using the package as a medium, in the future, in addition to the current broadcasting, digital broadcasting in which a digital signal is directly transmitted by a broadcast wave is under study. In this digital broadcasting, it is possible to transmit a large number of channels at once by time-division multiplexing the compressed image together with the compressed images of a plurality of channels. The digital broadcast decoder and the DVD player, which have been studied as described above, have many common parts in configuration, and as described above, the television receiver with the built-in DVD player can also receive the digital broadcast. By using a television receiver, the hardware scale can be significantly reduced.

FIG. 5 shows a television receiver capable of both receiving such a digital broadcast and reproducing a DVD. That is, the digital broadcast wave received by the antenna 58 is supplied to the tuner 59 and converted into a baseband signal. The baseband signal output from the tuner 59 is normally QPSK (Quadratu
Since modulation such as re Phase Shift Keying) is performed, the demodulation circuit 60 converts the multilevel signal into a binary signal.

Since the digital signal converted into the binary signal by the demodulation circuit 60 has a plurality of channels multiplexed, after the signal of the predetermined channel is extracted by the transport stream decoder 61, the image component and the audio signal are extracted. Separated into components. Of these, the audio component is supplied to the audio decoder 63 via the change-over switch 62 and subjected to decoding processing, and then provided for audio reproduction by the speaker 64.

The image components are supplied to the MPEG2 decoder 65 and the clock reproducing circuit 66, respectively. The clock reproducing circuit 66 generates the system clock CK of 13.5 MHz necessary for decoding the input image components. doing. Then, the MPEG2 decoder 65
Performs a decoding process on the input image component based on the system clock CK to generate an image signal, a horizontal synchronizing signal H, and a vertical synchronizing signal V, respectively, and outputs them to the image synthesizing circuit 67. The system clock CK output from the clock reproduction circuit 66 is also supplied to the image synthesis circuit 67.

On the other hand, reference numeral 68 is a DVD, and the recorded digital image data is read through the optical pickup 70 in a state of being rotated and driven under the control of the disk controller 69. The digital image data read by the optical pickup 70 is supplied to the data conversion circuit 71, converted into a digital stream signal of a predetermined format, and then supplied to the program stream decoder 72.

This program stream decoder 72
Is 13.5M generated by the clock recovery circuit 66.
Based on the system clock CK of Hz, the time-division multiplexed audio component and image component in the input stream are separated. Of these, the audio component is supplied to the audio decoder 63 via the changeover switch 62 and is used for audio reproduction. Also, the image component is the MPEG2 decoder 7
3 and is subjected to decoding processing based on the system clock CK of 13.5 MHz generated by the clock reproduction circuit 66, thereby generating an image signal, a horizontal synchronization signal H, and a vertical synchronization signal V, respectively. , To the image synthesis circuit 67.

Then, the image synthesizing circuit 67 causes the MPE
The image signals output from the G2 decoders 65 and 73 are combined for multi-screen display and output to the monitor 74 for image display. That is, digital broadcasting and DVD
In the television receiver that reproduces the signal 68 and the signal 68 at the same time, the system clock CK of 13.5 MHz generated from the digital broadcast wave can be used as it is for the reproduction of the DCD 68, and the hardware scale can be significantly reduced. It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the scope of the invention.

[0043]

As described in detail above, according to the present invention,
It is possible to provide an extremely good image display device capable of performing multi-screen display with easy control without deteriorating image quality with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram showing an embodiment of an image display device according to the present invention.

FIG. 2 is a block configuration diagram showing details of a synchronous reproduction circuit in the same embodiment.

FIG. 3 is a block configuration diagram showing an example of an image synthesizing circuit according to the same embodiment.

FIG. 4 is a block configuration diagram showing another example of the image synthesizing circuit in the embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a perspective view showing an example of a DVD reproducing system.

FIG. 7 is a perspective view showing another example of a DVD reproducing system.

FIG. 8 is a block diagram showing details of a DVD player.

FIG. 9 is a front view shown for explaining multi-screen display.

[Explanation of symbols]

11 ... DVD player, 12 ... DVD, 13 ... Cable, 14 ... Television receiver, 15 ... Disk controller, 16 ... Optical pickup, 17 ... Data conversion circuit, 18 ... Program stream decoder, 19 ... Audio decoder, 20 ... MPEG2 decoder, 21 ... NTS
C encoder, 22 ... Output terminal, 23 ... Antenna, 24
... tuner, 25 ... NTSC decoder, 26 ... image synthesizing circuit, 27 ... synchronous reproducing circuit, 28 ... DVD, 29 ... disk controller, 30 ... optical pickup, 31 ...
Data conversion circuit, 32 ... Program stream decoder, 33 ... MPEG2 decoder, 34 ... System controller, 35 ... Monitor, 36 ... VCO, 37 ... Output terminal, 38 ... Counter, 39 ... Phase comparison circuit, 40 ... Input terminal, 41 ... Loop filter, 42 ... Input terminal, 43 ...
Memory, 44 ... Input terminal, 45 ... Memory, 46 ... Controller, 47 ... Input terminal, 48 ... Changeover switch, 49 ...
Output terminal, 50 ... Input terminal, 51 ... Switch circuit, 52
... input terminal, 53 ... changeover switch, 54 ... memory, 55
... input terminal, 56 ... controller, 57 ... output terminal, 5
8 ... Antenna, 59 ... Tuner, 60 ... Demodulation circuit, 61
... Transport stream decoder, 62 ... Changeover switch, 63 ... Audio decoder, 64 ... Speaker, 65 ... M
PEG2 decoder, 66 ... Clock reproduction circuit, 67 ... Image synthesis circuit, 68 ... DVD, 69 ... Disk controller, 70 ... Optical pickup, 71 ... Data conversion circuit, 72 ... Program stream decoder, 73 ... MP
EG2 decoder, 74 ... Monitor.

Claims (3)

[Claims] 1. A first system clock is generated based on a synchronization signal included in the first image signal, and a decoding process is performed on the first image signal based on the first system clock. Decoding means and a second image signal including a synchronization signal having the same frequency as the synchronization signal included in the first image signal are input, and based on a second system clock having a frequency different from the first system clock. hand,
A second decoding means for performing a decoding process on the second image signal and a second system clock used by the second decoding means are phase-synchronized with a synchronization signal included in the first image signal. Synchronization means, and the first and second
2. An image display device comprising: an image synthesizing unit for generating a signal for multi-screen display by synthesizing each signal output from the decoding unit of 1. at a timing based on the synchronization signal. 2. The image display device according to claim 1, wherein the synchronizing means synchronizes the phase of the second system clock with a horizontal synchronizing signal. 3. The first system clock has a frequency of 910 times that of the horizontal synchronizing signal, and the second system clock has a frequency of 858 times that of the horizontal synchronizing signal. 2. The image display device according to 2.