JPH09160786A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the interruption processing time by using effectively the time during the saving of the contents of various registers accompanying the interruption processing and then setting the address of the interruption destination. SOLUTION: An interruption control part 3 processes the interruption request received from a peripheral device 2 and gives an interruption vector number to a CPU 1. A vector table control part 5 outputs a vector table address 13 and a control signal 12 to the part 5 based on the vector number sent from the part 3. A latch circuit 7 holds the data (interruption destination address) given from the part 5 until the saving of contents of a register is over. A selector 6 switches the data buses 10 and 11 by means of a selection flag that selects the software or hardware to perform the write/read control against the circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to interrupt handling in vector mode.

[0002]

2. Description of the Related Art In interrupt control of a microprocessor, when an interrupt is accepted, a stack pointer pushes down data held in various registers in the microprocessor to a storage device such as a main memory and saves the data. . When this process ends, the interrupt destination is read from the vector table by the vector address determined by the input vector number, and the address is transferred to the program counter. The program is executed from the address loaded in the program counter.

FIG. 2 is a conceptual diagram for explaining an interrupt method in a conventional microprocessor. FIG. 2 is disclosed in Japanese Patent Application Laid-Open No. 61-46531 (hereinafter referred to as "prior art 1"). A vector generating circuit is configured by a latch circuit, and an arbitrary interrupt destination is directly designated by software. The interrupt processing function is being improved.

In FIG. 2, a portion surrounded by a broken line is a microprocessor CPU and a memory area MA.
The memory area MA includes an address space assigned to a RAM (random access memory), a ROM (read only memory), or the like.

The microprocessor CPU has various registers such as an arithmetic and logic operation circuit (not shown) and an accumulator (not shown) for information processing, and a timing control circuit (not shown). In this example, the program counter PC directly related to the interrupt operation,
The stack pointer SP, the status register CC, the instruction register IR, and the decoder DCR are exemplarily shown.

The vector generation circuit designating the interrupt destination transfers data to and from the internal data bus D-BUS. In other words, the vector generation circuit is composed of the latch circuit FF capable of writing / reading. Since such a latch circuit FF constitutes a vector generating circuit, an initial value is written in the latch circuit FF prior to the execution of the program.

Next, the interrupt operation of this example will be described.

When the interrupt signal IQR is input during the processing of a program by the microprocessor CPU, a logic "1" level signal is written to a specific bit of the status register CC. At this time, if the bit information for invalidating the interrupt is not written, the information processing is interrupted and the stack constituted by the stack pointer SP, that is, the address indicated by the stack pointer SP, for example, a hexadecimal number. At F000 (H), the data held in various registers currently being processed is pushed down in the order of program counter PC (lower L, upper U and so on), U register (L, U) to status register CC. It As a result, the state of the interrupted program is saved.

After this, a signal of logic "1" level is written in the status register CC at a specific bit indicating that the interrupt is being processed.

Then, the specific address XXXX (H) held in the latch circuit FF as the vector generating circuit is transferred to the program counter PC. This address XXX (H) is the start address of the interrupt program to be processed by the above interrupt factor. As a result, the address XXXXX which is the interrupt destination is immediately sent.
The program stored in (H) is sequentially read into the instruction register IR, and the decoder CDR decodes the program, and the content of the latch circuit FF is rewritten in the program if necessary. That is, when the interrupt processing to be processed next is different due to the same next interrupt factor, the start address of the program in which it is stored is written. Such change of the interrupt destination can be performed at any time in any information processing. For example, in process control and the like, information processing is performed in a fixed procedure. Therefore, when performing a plurality of interrupt processes of the same factor, the cause of the interrupt in a certain information process is known in advance. The software sets the vector accordingly.

By the execution of the last return instruction of the interrupt processing program, the data saved in the stack area is pushed up and returned to each register again, so that the interrupted original program is restarted. Becomes

The following is known as another prior art related to the present invention. For example, Japanese Patent Laid-Open No. 61-849
Japanese Patent Publication (hereinafter referred to as "prior art 2") adds a register to a microprocessor unit and sets a vector number in this register to create a compact and high-speed interrupt processing procedure "Microcomputer Interrupt". A control method "is disclosed.

[0013]

In the prior art 1 shown in FIG. 2, since the latch circuit FF for holding the interrupt destination address is connected to the internal data bus, the interrupt destination address is set and the interrupt processing is performed. The accompanying saving of the contents of various registers must be performed exclusively. The time problem of saving the contents of the registers for holding the state of the program is that the performance is lowered due to the overhead of the processing time in a system that frequently uses interrupts. In particular, when the transmission / reception processing such as a communication line is performed by an interrupt, when the communication speed is increased, the microprocessor CPU is servicing the interrupt, and the data to be transmitted or received next is underrun or overrun by prolonging the processing. There are drawbacks such as causing As described above, in Prior Art 1, the setting of the interrupt destination address and the saving of the contents of various registers associated with the interrupt processing must be performed exclusively. Has the drawback that it cannot be used effectively.

An object of the present invention is to solve the above problems and to effectively use the time during the saving of the contents of various registers associated with interrupt processing and to set the interrupt destination address, thereby shortening the interrupt processing time. It is to provide a designed microprocessor.

Another object of the present invention is, regarding the interrupt processing in the vector mode, when the vector number is input, the vector table address and the control signal are output to the vector table storage unit, and the CPU is involved in the interrupt processing. An object of the present invention is to provide a microprocessor capable of determining an interrupt destination address while saving the contents of various registers.

The prior art 2 merely discloses a microcomputer unit having a register that can store a vector number applied by an external device and can be read by a procedure for processing an interrupt. This is completely different from the technique of effectively utilizing the time during the saving of the contents of the various registers involved.

[0017]

In order to solve the above problems, the microprocessor according to the present invention saves the data of various registers with the peripheral device which generates an interrupt request and the interrupt processing. Main memory of
In a microprocessor equipped with a CPU, which is connected to a vector table storage unit that stores an interrupt vector table, receives an interrupt request from a peripheral device,
Process the interrupt request and set the interrupt vector number to CP
Depending on the interrupt control unit given to U and the vector number output from this interrupt control unit, the vector table control unit that outputs the vector table address and the control signal to the vector table storage unit, and the end of the saving of the register contents And a latch circuit that holds the data (interrupt destination address) from the vector table storage unit until the saving of the contents of the register is completed.

In the microprocessor described above, a selection flag for writing or reading control to the latch circuit by software or hardware and a selector for switching the data bus by the selection flag may be provided. good.

[0019]

In the present invention, the interrupt control unit outputs the vector number to the vector table control unit after confirming that the CPU has accepted the interrupt request.

Upon accepting the interrupt, the CPU saves the contents of various registers so that the state at the time of accepting the interrupt can be restored after the interrupt processing is completed.

While the CPU saves the contents of various registers, the vector table control unit outputs the vector table address and the control signal to the vector table storage unit according to the input vector number. The vector table storage unit sets the address of the interrupt destination in the latch circuit according to the input address of the vector table.

After that, when the saving of the contents of the register is completed, a signal of logical "1" level is written in the end flag, and the address held in the latch circuit is set in the PC (program counter).

As described above, while the CPU saves the contents of various registers to the main storage unit, the interrupt destination address can be determined, so that the interrupt processing time can be shortened.

Further, by switching the data bus according to a selection flag as to whether writing to the latch circuit holding the interrupt destination address is performed by hardware or software, the software in the prior art 1 described above is used. It is also possible to set the interrupt destination address, and by efficiently switching the write control according to the situation, it is possible to further improve the interrupt function.

[0025]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, an information processing system to which a microprocessor according to an embodiment of the present invention is applied includes a CPU 1, a peripheral device 2, an interrupt control unit 3, and
The vector table control unit 4, the vector table storage unit 5, and the main storage unit 8 are provided. The CPU 1, the interrupt controller 3, and the vector table controller 4 constitute a microprocessor. CPU 1 is selector 6
And a latch circuit 7 and a program counter (PC) 9. The main storage unit 8 includes a stack area.

When an interrupt request is input from the peripheral device 2 to the interrupt control unit 3, the interrupt control unit 3 issues an interrupt request to the CPU 1 and waits for permission to accept an interrupt. After confirming that the CPU 1 has accepted the interrupt request, the interrupt controller 3 outputs the vector number to the vector table controller 4.

On the other hand, in the CPU 1, when the execution of the interrupt processing routine is completed, the current processing is performed on the stack constituted by the stack pointer in the main memory 8 so that the state at the time of accepting the interrupt can be completely restored. The data held in the various registers inside is saved.

In the vector table control unit 4, the CPU 1
While it is saving the contents of the register, it decodes the input vector number and returns the vector table address 13
Generate As a method of generating the vector table address 13, for example, the interrupt destination address of the interrupt vector that is n is calculated in such a manner that it starts from the address (4 × n).

The vector table storage unit 5 stores the start address of the interrupt processing routine at an address determined by the interrupt vector, and the vector table control unit 4 completes the generation of the vector table address 13. Then, the vector table address 13 and the control signal 12 are output to the vector table storage unit 5.

The vector table storage unit 5 sets the interrupt destination address corresponding to the input vector table address 13 in the latch circuit 7.

After this, when the saving of the contents of the various registers is completed, a signal of logic "1" level is written in the end flag (not shown), and the interrupt address held in the latch circuit 7 is transferred to the PC 9. By doing so, the interrupt destination program is executed and interrupt processing is performed.

The various registers whose contents have been saved are returned to their original states by executing a return instruction or the like at the end of the interrupt processing routine, so that the interrupted program is restarted.

Further, depending on the setting contents of a selection flag (not shown) for writing to the latch circuit 7 by software or hardware, the software setting data bus 10 and the hardware setting data bus 11 are set. Switching is performed by the selector 6.

As a result, the interrupt destination address can be set by either software or hardware.

[0036]

As described above, according to the present invention, the interrupt destination address is read from the vector table and set in the latch circuit by utilizing the time taken for the CPU to save various registers in the main memory. Thus, the interrupt processing time can be shortened. By providing a selector that switches depending on whether the flag is software setting or hardware setting, it is possible to perform control in a more efficient manner depending on the type of interrupt.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an information processing system including a microprocessor according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram for explaining an interrupt method in a conventional microprocessor.

[Explanation of symbols]

 1 CPU 2 Peripheral device 3 Interrupt control unit 4 Vector table control unit 5 Vector table storage unit 6 Selector 7 Latch circuit 8 Main storage unit 9 Program counter (PC)

Claims (3)

[Claims] 1. A peripheral device that generates an interrupt request, a main storage unit for saving data of various registers when performing interrupt processing, and a vector table storage unit for storing an interrupt vector table. Connected to and C
In a microprocessor including a PU, an interrupt control unit that receives the interrupt request from the peripheral device, processes the interrupt request, and gives an interrupt vector number to the CPU, and a vector number output from the interrupt control unit ,
The vector table address and control signal are
A vector table control unit for outputting to the table storage unit, an end flag for notifying the end of saving the contents of the register, and a latch circuit for holding the data from the vector table storage unit until the saving of the contents of the register is completed. Including a microprocessor. 2. The method according to claim 1, further comprising a selection flag for controlling whether writing or reading to or from the latch circuit is performed by software or hardware, and a selector for switching the data bus according to the selection flag. The microprocessor according to. 3. The microprocessor according to claim 1, wherein the data from the vector table storage unit includes an interrupt destination address.