JPH09160773A - Microprogram exchanging method in multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time when input to and output from a central processor are stopped by dividing a storage control device into subsystems which can operate independently, e.g. clusters and exchanging microprograms by the subsystems. SOLUTION: Sequence control over off-line requests, microprogram exchanging, rebooting, and on-line requests is performed by clusters 180 (A-plane cluster 180a and B-plane cluster 180b) under the sequence control of a service processor (SVP) 181. A storage controller 100, on the other hand, receives a request from the SVP 181 and instructs a central processor 160 to place a data transfer path in off-line mode, and waits for an off-line request to be accepted from the SVP 181. Then, access to a common memory 120 is temporarily suppressed until the on-line instruction is received from the SVP 181 to prevent malfunction. Off-line completion is reported to the SVP 181, then exchange of microprograms is performed. Then, every processor 140 is rebooted to enable new programs to be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system having a plurality of processors and a shared memory, and more particularly, storage control for interposing a central processing unit and a storage device to control data storage in the storage device. The present invention relates to a storage subsystem having a device and a microprogram exchange method thereof.

[0002]

2. Description of the Related Art In general, a storage controller provided in a storage subsystem used for holding data in an information processing system has a multiprocessor structure in order to improve the efficiency of input / output processing. . For example, as a disk control device that controls a magnetic disk device, which is a type of external storage device, a shared memory type multiprocessor disk control device in which each processor communicates via a shared memory is known. In such a storage control device, each processor stores a program in the internal memory and each operates independently. On the other hand, the information that needs to be shared between the processors is stored in the shared memory.

Microprogram exchange in the storage controller of the shared memory type multiprocessor system is as follows.
It is often performed in an off-line state, that is, in a state where input / output from the central processing unit is stopped. First, the microprogram to be exchanged is stored in, for example, a hard disk equipped with a service processor, the data transfer path between the central processing unit and the storage controller is taken offline, and then the power is turned off / on to start the storage controller. Reload and replace with a new microprogram.

On the other hand, in such a storage device subsystem, as a method of carrying out an on-line state, that is, a micro program exchange without stopping the input / output from the central processing unit, it is described in Japanese Patent Application No. 6-99705 by the present applicant. There is a technique to be done. According to the technique described here, microprogram exchange is performed for each group of processors and shared memory called a cluster. In this method,
In the process of exchanging microprograms, old and new microprograms temporarily mix and operate in each cluster, but a job (processing unit) that is executing in a cluster does not work in other clusters even if it repeatedly waits and posts. By controlling so that the programs are not executed, it is possible to prevent the malfunction of the program due to the mixture. When exchanging the microprogram of each cluster, the data transfer path connected to the cluster is temporarily placed in the offline state, but the data transfer path from the central processing unit to the storage controller is set to 1 for each cluster.
Since most of them are connected to each other, as a result, it becomes possible to exchange the microprogram of the storage controller without stopping the input / output of the central processing unit.

[0005]

[Problems to be Solved by the Invention] Japanese Patent Application No. 6-99705
Although the technology described in No. 1 is capable of exchanging microprograms online, it may not be possible to exchange programs including changing the contents of the shared memory. For example, when the addressing of the shared memory is changed, in the method described in Japanese Patent Application No. 6-99705, the processor replaced by the new microprogram accesses the shared memory that is compatible with the old microprogram. There is a risk that incorrect information will be referenced and updated, causing malfunction. As another example, when the definition of the control information of the shared memory is changed, Japanese Patent Application No.
In the method described in No. -99705, a malfunction may occur when the processor operating in the new microprogram refers to the control information set by the processor operating in the old microprogram.

For the above-mentioned reason, the microprogram exchange including the change of the contents of the shared memory is executed off-line, but it is desirable to shorten the off-line time as much as possible. Normally, it takes 10 minutes or more to restart the storage controller by turning the power off and on, a large capacity cache is mounted, and there is a lot of pending data (write data that has not yet been reflected in the storage device) in the cache. May take 30 minutes to 1 hour. During this time, the input / output of the central processing unit to / from the storage device is stopped, so that it has a great influence on the business.

In view of the above, an object of the present invention is to enable microprogram exchange by minimizing the time during which the storage controller is off-line from the central processing unit.

[0008]

In order to achieve the above object, a storage subsystem according to the present invention comprises a storage controller for controlling data input / output to / from a storage device, and a storage controller via a communication means. And a service processor connected thereto. The storage controller has a means for instructing the central processing unit to take the data transfer path offline or online, a means for monitoring the presence / absence of a job in the cluster subject to microprogram exchange,
Means are provided for temporarily suppressing access to the shared memory according to an instruction from the service processor. On the other hand, the service processor is provided with means for controlling the sequence of microprogram exchange.

In a preferred embodiment of the present invention, the sequence control of the service processor controls the sequence of offline request, microprogram exchange, reboot (restart of processor), and online request for each cluster. On the other hand, in the storage control device, in response to the request from the service processor, the offline instructing unit instructs the central processing unit to take the data transfer path offline, and the job monitoring unit executes the data in the cluster. Wait for the job to complete. afterwards,
The shared memory access inhibiting means temporarily inhibits access to the shared memory until an online instruction is received from the service processor to prevent malfunction. After the above processing, the offline completion is reported to the service processor, and the microprogram is exchanged in response to the report. After that, a reboot is executed for each processor to enable execution of the new program.

Further, the service processor issues an online request to the cluster for which the program exchange has already been completed, after taking the final cluster offline.
In response to this, the storage controller instructs the central processing unit to bring the data transfer path online by the online instructing means.

Also for the final cluster, the offline request, the microprogram exchange, the reboot, and the online request are executed by the above-described method to complete the microprogram exchange.

The above method enables microprogram exchange.

[0013]

1 is a block diagram of a storage system according to an embodiment of the present invention. The device configuration will be described with reference to FIG. The storage system 199 is 1
Storage controller 100 connected to one or more (two in FIG. 1) central processing units 160, and storage controller 100
And at least one storage device 170 (four in FIG. 1) connected to the storage device 170. Storage control device 100
Is composed of two clusters, an A-side cluster 180 (a) and a B-side cluster 180 (b). In the following description, the subscripts (a) and (b) of the reference numbers will be omitted unless it is particularly necessary to distinguish between the A-side and the B-side (the same applies to other components). Power is supplied to each cluster 180 separately, so that even if one cluster 180 goes down due to power interruption, the other cluster can operate. In this embodiment, a storage controller having a cluster configuration is described as an example in this way, but even a storage controller not having a cluster configuration can be divided into a plurality of groups that can operate independently. If not, it can be applied.

The storage controller 100 comprises a central processing unit 16
0 through a channel path 190 and a plurality of storage devices 170 through a drive path 195.
Even if one cluster 180 goes down, each central processing unit 160 has one or more channel paths 190 for each cluster 180 in order to continue the input / output processing in the other cluster 180. For the same reason, the storage control device 100 also has a plurality of drive transfer paths 195 from each cluster for each storage device 170.

Each cluster 180 has a shared memory 110 for storing common control information required for executing multiprocessor control, a cache memory 130 for temporarily storing data, a directory 120 for storing cache memory management information, A processor 140 that controls data transfer between the central processing unit 160, the cache memory 130, and the storage device 170, and a flash memory (FM) 15 that stores processor-specific information such as a microprogram.
Contains 0. Further, the shared memory 110, the cache memory 130, and the directory 120 are accessed from the processor 140 via the common bus 196.

Two shared memories, A-side shared memory 110
The (a) and B side shared memory 110 (b) hold the same contents in a normal state. The access mode from each processor 140 to the shared memory 110 includes the following access modes.

Double read / double write: Both read and write, A side shared memory 110 (a), B side shared memory 1
Both of 10 (b) are performed. When both shared memories 110 are normal, access is performed in this mode.

A side read, A side write: Both read and write are performed on the A side shared memory 110 (a). The B-side shared memory 110 (b) is accessed in this mode when it is blocked due to a failure or maintenance.

A side read, double write: Read is performed from the A side shared memory 110 (a), and write is performed to both the A side shared memory 110 (a) and the B side shared memory 110 (b). Access is made in this mode when the B-side shared memory 110 (b) recovers from the blockage.

B side read, B side write: Both read and write are performed on the B side shared memory 110 (b). Access is performed in this mode when the A-side shared memory 110 (a) is blocked due to a failure or maintenance.

B-side read, double write: Read is performed from the B-side shared memory 110 (b), and write is performed for both. Access is made in this mode when the A-side shared memory 110 (a) recovers from the blockage.

Further, at the time of system start-up, SVP1
When there is a request from 81, the processor 140 initializes the shared memory 110. Also, when recovering from the blocked state or when there is a request from the SVP 181, the shared memory 1 recovered from the normal shared memory 110
Data is copied to 10.

A storage device 170 is provided in the A-side cache memory 130 (a) and the B-side cache memory 130 (b).
A copy of the above data (called clean data) or unreflected data (called dirty data) in the storage device 170 is stored, but basically data of different storage device addresses is stored in each cache memory. It
Therefore, the contents of the two directories 120 are different, and the cache memory 130 corresponding to each surface is different.
Holds management information of.

The service processor (SVP) 181 supporting the maintenance function is connected to each processor 140 via the LAN cable 185, and the processor 14
Communication with 0 is possible. Furthermore, the SVP 181 is a hard disk (HD) 1 that stores microprograms.
82 inside.

FIG. 2 is a flowchart of the processing executed by the SVP 181.

First, in step 200, the storage controller 10
For 0, set the cache prohibition mode. While this mode is set, data retention on the cache memory 130 is suppressed. Then, in step 205, an instruction to save the shared memory information stored in the shared memory 120 is issued. In response to the shared memory information saving instruction, each processor 140 that receives the instruction needs to hold information among the information stored in the shared memory 110, for example, device configuration information, resource mounting information, and an address described later. The path management table is stored in the FM 150. Subsequently, in step 210, an offline instruction is issued to each processor 140 of the A-side cluster 180 (a), and the operation mode of each processor 140 of the A-side cluster 180 (a) is shifted to the shrinking operation. The contraction operation is an operation mode in which any processing other than an instruction from the SVP 181 is not performed. This operation mode inhibits access to the shared memory 110. When each processor 140 goes offline, in step 220, the hard disk 182
Is copied to each FM 150 of the A-side cluster 180 (a), and each processor 140 is rebooted in step 225. In step 227, the access mode of the shared memory is set to B-side read and B-side write. Then in step 230,
The processor 140 having the A-side cluster 180 (a) is instructed to initialize the A-side shared memory 110 (a).

As described above, the microprogram executed by each processor 140 of the A-side cluster 180 (a) is replaced with the new microprogram, and the A-side shared memory 180 is exchanged.
(A) is also updated to support the new microprogram.

Subsequently, microprogram exchange of the B-side cluster 180 (b) is performed in the following procedure. First, in step 235, the SVP 181 determines that the B-side cluster 180
An offline instruction is issued to each processor 140 in (b), and the operation mode is shifted to the shrinking operation. The state of the storage device system 199 at this point is as follows:
Each processor of 80 (a) is in a shrinking operation by the new microprogram, and the A side shared memory 110 (a), the A side directory 120 (a), the A side cache memory 130.
(A) is initialized to support the new microprogram. On the other hand, in the B-side cluster 180 (b), each processor is degenerate by the old microprogram, and the B-side shared memory 110 (b), B-side directory 120 (b), B-side
The surface cache memory 130 (b) remains compatible with the old microprogram.

Then, in step 245, the SVP 181
Sets the access mode of the shared memory 110 to A-side read and A-side write, and issues an online instruction to each processor 140 of the A-side cluster 110 (a) in step 250. When the transition of each processor 140 of the A-side cluster 110 (a) to the online state is completed, the central processing unit 16 by the A-side cluster 180 (a) is
Input / output processing from 0 is restarted. At this point, the A-side cluster 110 (a) is in input / output operation by the new microprogram, and the B-side cluster 110 (b) is in degeneration operation by the old microprogram. Here, changing the access mode of the shared memory 110 in step 245 is
This is to prevent the processor 140 operating in the new microprogram, which is released from the degenerate operation, from accessing the B-side shared memory 110 (b) corresponding to the old microprogram.

At the following step 260, the new microprogram stored in the hard disk 182 is copied to each FM 150 of the B-side cluster 180 (b). Then, in step 265, each processor 140 of the B-side cluster 180 (b) is rebooted. Step 2
In 67, the shared memory access mode is set to A-side read and double write, and in step 270, B-side cluster 1
It instructs the processor 140 of 80 (b) to copy data from the A-side shared memory 110 (a) to the B-side shared memory 110 (b). Here, the shared memory 110
The reason for copying is that the A-side cluster is already operating with the new microprogram and the contents of the A-side shared memory are already compatible with the new microprogram. By being available in a face cluster. Then, in step 273,
The shared memory access mode is set to double read and double write, and in step 275, an online instruction is issued to each processor 140 of the B-side cluster 180 (b).

With the above, the microprogram exchange of both the A-side and B-side clusters is completed.

FIG. 3 is a flowchart of the processing of the processor 140 in response to the cache prohibit mode setting instruction from the SVP 181. The reason for prohibiting the use of the cache is that the storage system 1 is used during microprogram exchange.
99 is temporarily set to the offline state, and the shared memory 11
Since 0 and the directory 120 are initialized, it becomes impossible to hold data. Therefore, as described above, the SVP
Reference numeral 181 prohibits the use of the cache by setting the cache prohibition mode before exchanging the microprogram. In the cache prohibit mode, the cache memory 1
When 30 is not used at all or dirty data is not stored even if it is used, that is, in response to a write request from the central processing unit 160, the data must be written to the storage device 170 in synchronization with it.

The processor 140, which has received the cache prohibition mode setting instruction, at step 300, the shared memory 11
The cache use prohibition mode is set to 0. Next, in steps 310 to 330, the directory 120 is searched to determine the presence or absence of dirty data, and if there is dirty data, all of them are written to the storage device 170. The above is the cache prohibition mode setting process executed by each processor 140.

When the processor 140 detects that the cache prohibit mode is set, the central processing unit 1
In response to a write request from 60, the cache memory 13
The write data is directly written to the storage device 170 without storing the write data in 0, or the write data is immediately written to the storage device 170 even if it is stored, and the write complete is reported to the central processing unit 160.

FIG. 4 is a flowchart of the offline processing performed by the processor 140 in response to the offline processing request (steps 210 and 235 in FIG. 2) issued by the SVP 181.

In step 410, the processor 140 that has received the offline processing request from the SVP 181 sends all storage devices 1 online via its own processor 140.
Off-line processing is performed for 70 with the central processing unit 160. The online storage device 170 is managed by the address path management table shown in FIG. This table is composed of a processor number (column 510), a channel path number (column 520), and a storage device number (column 530), and the storage device k accessible from the channel path i via the processor j. Indicates. Here, i, j, and k represent a processor number, a channel path number, and a storage device number, respectively. Each processor 1
40 performs offline processing using this table.
For details of off-line processing, refer to the related art, for example,
IBM Corporation IBM 3990 Storage Control Planning, Installat
ion, and Storage Administration Guide. GA32-0100-0
Since the method such as CUIR described in 7, P26 may be applied, the description is omitted here.

In step 420, the self processor 140
Checks to see if there is any more work left to do, and if so, completes that work. By the off-line processing of step 410, the central processing unit 160
Although there is no processing request from the storage device system 199, there is a possibility that the processing being internally executed by the storage device system 199 still remains. Therefore step 420 is necessary. Own processor 1
If all the processes to be executed in 40 are exhausted, step 43
At 0, the offline processing completion is reported to the SVP 181.

Subsequently, at step 440, each processor 1
40 starts the contraction operation.

By the above processing, the off-line processing of the cluster 180 to be exchanged with the microprogram is completed.

As described above, when the offline processing of the cluster 180 is completed, the SVP 181 copies the new microprogram to the FM 182 and then reboots each processor. At the time of rebooting, the microprogram of the FM 182 is expanded in the local memory of the processor 140 and executed from the start address of the program. However, since this can be realized by the conventional technique, description thereof will be omitted.

In the microprogram exchange, initialization of these memories may be necessary due to a defective program, support of new functions, or the like. For example, when the structure of the shared memory 110 needs to be added to support a new function, the address in the shared memory 110 where information is stored may change. In the new microprogram, the shared memory corresponding to the old microprogram may be changed. 110 may not be accessible. For this reason, the contraction operation is continued after the reboot until there is an instruction from the SVP 181. For example, when step 225 of FIG. 2 is completed, the contents of the shared memory 110 remain compatible with the old microprogram. For this reason, the exchange of the microprogram is completed, and it cannot be accessed from the processor 140 of the A-side cluster 180 (a) operating in the new microprogram. Therefore, it is necessary to operate in the collapsed mode.

FIG. 6 shows the processor 1 that has received the initialization instruction request (FIG. 2, step 230) issued by the SVP 181.
14 is a flowchart of a shared memory initialization process performed by 40. The SVP181 will be executed according to the procedure described below.
A cluster 180 that received the initialization instruction request by
The specific processor 140 of FIG.
0, the directory 120, and the cache memory 130 are initialized.

First, in steps 610 and 620, the specified plane, in this case, the A plane shared memory 110 (a), the A plane cache memory 130 (a), and the A plane directory 12 are used.
0 (a) is initialized, and each content is updated to the content corresponding to the new microprogram. Subsequently, in step 630, the shared memory information saved in the FM 150 is expanded in the A-side shared memory 110 (a), and the processing is completed.

Before this processing is executed, the SVP 181 has already set the access mode of the shared memory to B-side read and B-side write, so that the BVP operating in the old microprogram is in operation.
The processor of the face cluster 180 (b) never accesses the A-side shared memory 180 (a) corresponding to the new microprogram.

FIG. 7 shows the processor 1 which has received the online instruction (FIG. 2, step 250) issued by the SVP 181.
It is a flowchart of the online transfer process performed by 40.

Processor 140 that has received an online instruction
First, in step 710, issues an online recovery processing request to the central processing unit 160 to recover the online status. For online recovery process,
The above-mentioned CUIR method can be used, and detailed description thereof is omitted here. Then, in step 720, the address path management table is restored. Then, in step 730, the degenerate mode is released. In this step, each processor 140 restarts access to the shared memory 110 and can accept an input / output request. Finally, in step 740, the online migration completion is reported to the SVP 181.

The microprogram exchange in this embodiment is completed by the above processing. In this micro program exchange method, the purpose is to reduce the time during which the storage device system 199 is offline, that is, the time during which input / output from the central processing unit 160 is stopped, but the time is the B-side cluster 110 (b). Is the sum of the time of performing the offline processing of the above and the time of bringing the A-side cluster 110 (a) online. The off-line processing time is determined by the time required to complete all jobs currently being executed, which can be normally completed in several hundred milliseconds to several seconds.
Even if other overheads are taken into consideration, the input / output processing stop time can be set to about several seconds.

[0048]

According to the storage control device of the present invention, by dividing the device into subsystems which can operate independently, for example, a cluster, and exchanging a micro program for each subsystem, an input from the central processing unit is obtained. The time when output is stopped can be shortened.

[Brief description of the drawings]

FIG. 1 is a device configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of processing of a service processor.

FIG. 3 is a flowchart of cache prohibit mode setting processing.

FIG. 4 is a flowchart of offline processing.

FIG. 5 is a configuration diagram of an address path management table.

FIG. 6 is a flowchart of shared memory initialization processing.

FIG. 7 is a flowchart of an online migration process.

[Explanation of symbols]

100: storage control device, 110: shared memory, 120:
Directory, 130: cache memory, 140: processor, 150: flash memory, 160: central processing unit, 170: storage device, 180: cluster, 18
1: service processor, 182: hard disk, 1
90: channel path, 195: drive path, 196:
Bus, 199: Storage system

Claims (7)

[Claims] 1. A storage device connected to a central processing unit for storing data, a plurality of control processors interposed between the central processing unit and the storage device and operating according to a micro program, and storing control information. A storage device subsystem having a storage control device comprising a plurality of shared memories and a cache memory for temporarily storing data, and a service processor connected to the storage control device via a communication means. To
A method of exchanging a micro program for exchanging a first micro program during operation with a second micro program, wherein the storage controller comprises one or more shared memories and one or more control processors. It is divided into a plurality of subsystems that can operate independently, and for each subsystem, the I / O requests from the central processing unit are sequentially shifted to the offline state in which the subsystems placed in the offline state are stopped. When the first microprogram is exchanged for the second microprogram and the last subsystem is taken offline, another subsystem that has already completed microprogram exchange accepts I / O requests from the central processing unit. A method for exchanging a micro program, characterized by making an online state. 2. The microprogram exchange method according to claim 1, wherein the division into the subsystems is performed based on a power supply unit of the storage controller. 3. In the second microprogram exchange, after the microprogram exchange is completed, the control processor in the subsystem being processed is rebooted, and one control processor in the subsystem is exchanged. 3. The microprogram exchange method according to claim 1, further comprising: a process for initializing the contents of the shared memory in the subsystem according to. 4. The microprogram exchange method according to claim 3, wherein the initialization process of the shared memory is performed according to an instruction from the service processor. 5. The shift to the offline state includes a process of writing write data, which has not been reflected in the storage device stored in the cache, to the storage device according to an instruction from the service processor. The microprogram exchange method according to any one of claims 1 to 4. 6. The microprogram exchange method according to claim 5, wherein during the microprogram exchange, control is performed so that write data not reflected in the storage device is not held in the cache. 7. The method according to claim 1, wherein during the exchange of the microprogram, access to the shared memory and the cache memory by the control processor is suppressed by an instruction from the service processor. The method for exchanging a micro program according to.