JPH09153295A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an EEPROM cell from being subjected to casual overwriting and erasing. SOLUTION: This device has the EEPROM cell 1 which executes writing in accordance with the HV signal of the voltage higher than an ordinary operating voltage, a write-read control circuit 4 which controls the operation of this EEPROM cell 1, HV detecting circuit 3 which puts the control circuit 4 into a program mode when the Vpp signal of the high voltage for the program is inputted and a STBenable/disable control circuit 5 which applies effective conditions by a PDATA signal including a specific code signal to the inverse of STB signal for imparting the conditions for impression of the HV signal applied from the control circuit 4 to the EEPROM cell 1 at the time of programming. In the case of writing to the EEPROM cell 1, the specific code signal is applied to the STBenable/disable control circuit 5 to previously make the inverse of STB signal effective and the program to the EEPROM cell 1 by the write/read gate control circuit 4 is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Especially, EEP for programming by applying high voltage from outside
The present invention relates to a circuit system for protecting ROM data from spike noise.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional semiconductor memory device.

In the figure, programmable EEPRO
The M cell 1 can program arbitrary data by externally applying an HV signal higher than a normal operating voltage, and has a function of retaining data even when the power is turned off.

Addresses for reading and writing data in the EEPROM cell 1 are externally given as address data A0 to A7 (8-bit parallel address data). And this address data A
0 to A7 are decoded by the address decoder 2,
It is supplied to the EEPROM cell 1.

On the other hand, in order to control various operation modes of the EEPROM cell 1, a write / read gate control circuit 4 is connected.

At the time of programming, the write / read gate control circuit 4 applies a stress signal to the EEPROM cell 1 to give it a write mode, and a signal having a voltage higher than the voltage during the normal operation is applied as the HV signal. In addition, the data to be programmed is Writ
The e signal is serially supplied to the EEPROM cell 1.

On the other hand, at the time of verification, the data programmed in the EEPROM cell 1 is serially read out as a Verify signal and given to the write / read gate control circuit 4.

When data is programmed in the EEPROM cell 1, a Vpp signal is externally supplied to the HV detection circuit 3. This Vpp signal is E
It is given as a signal having a voltage higher than the normal operating voltage of the EPROM cell 1.

Upon detecting the Vpp signal, the HV detection circuit 3 generates a VppEnable signal and outputs it to the write / read gate control circuit 4 and the address decoder 2. With this VppEnable signal, the address decoder 2 gives a program address to the EEPROM cell 1, and the write / read gate control circuit 4
Enters program mode. At the same time, an HV signal having a voltage higher than the normal operating voltage is applied to the write / read gate control circuit 4. This HV signal is supplied as it is during programming.

Further, with respect to the EEPROM cell 1, data to be programmed is serially SDAT from the outside.
It is input as the A signal. In addition to the SDATA signal, a clock for synchronization is supplied as the SCKφ signal. Further, a PROGRAM • / VERIFY signal for switching between program mode and verify and a / STB signal for controlling the HV signal inputted to the EEPROM cell 1 are supplied.

On the other hand, from the write / read gate control circuit 4, the Ver read from the EEPROM cell 1 is performed.
The ify signal is output as serial data as the SOUT signal.

The operation of the above-described structure will be described below.

When data is programmed in the EEPROM cell 1 of the semiconductor memory device, the semiconductor memory device is mounted on a writing device such as an EEPROM writer (not shown), and the HV detection circuit 3 is normally read from the writing device side. A Vpp signal higher than the operating voltage is input.

The HV detection circuit 3 which has detected the Vpp signal is
The VppEnable signal is output to the write / read gate control circuit 4 and the address decoder 2 to put them in the program mode.

Next, address data A0 to A7 are given to the address decoder 2 as parallel data, and the address decoder 2 decodes this and gives it to the EEPROM cell 1 to set a program address.

Then, the PROGRAM / VERIFY signal is given to the write / read gate control circuit 4 in the program mode, and the serial program data clock-synchronized with the SCKφ signal is sent to the SDAT.
Input as A signal.

Next, the level of the / STB signal is changed, for example, from H level to L level. Then, the write / read gate control circuit 4 outputs the HV signal to the EEPROM cell 1 in response to the level of the / STB signal, for example, the L level, and stresses the EEPROM cell 1 with a high voltage. As a result, the EEPROM cell 1 is in the programmable state.

At the same time, the program data is supplied from the write / read gate control circuit 4 to the EEPROM cell 1 as a Write signal to write the data.

On the other hand, at the time of verification, PROGRAM
-Set the / VERIFY signal to the verify mode. As a result, the write / read gate control circuit 4 enters the verify mode, the data of the EEPROM cell 1 corresponding to the address data A0 to A7 is read to the write / read gate control circuit 4 by the strobe signal, and the Verify signal becomes the SCKφ signal. Synchronized Sou
It is output from t. This Verify signal is referred to as program data on the writing device side, and is used to verify whether or not the data programming is normally performed.

[0020]

As described above, since the conventional semiconductor memory device is configured to enter the program mode in response to the Vpp signal to enable data programming, this semiconductor memory device is used. When the storage device is mounted on a board of a device using the storage device and used on-board, there is a problem that there remains a risk of overwriting data or erasing data due to spike noise or the like.

That is, if spike noise is applied to the Vpp signal terminal of the HV detection circuit 3 and the HV detection circuit 3 malfunctions, the write / read gate control circuit 4 enters the program mode. And PROGRA
If the terminal for inputting the M./VERIFY signal or / STB signal is set to the same level state as in the program mode, the EEPROM cell 1 is overwritten or erased.

This is an accident that may occur because each terminal of the semiconductor memory device is given different functions during programming and during reading. That is, since the terminal for inputting the Vpp signal is used as an input-only pin or an I / O pin in the read mode, it is currently difficult to take measures to protect only this terminal from spike noise. The same applies to the terminals of.

As described above, the conventional semiconductor memory device is
There is a risk of overwriting or erasing program data due to spike noise, and improving reliability by a fundamental response has been a major issue.

The present invention solves the problems of the prior art as described above, and even after an unexpected transition to the program mode due to spike noise or the like occurs after being mounted on a device to which it is applied, overwriting or An object of the present invention is to provide a semiconductor memory device which is not erased and has high reliability in terms of protection of program data.

[0025]

In order to achieve the above object, as a semiconductor memory device of the present invention, an EEPROM cell for programming at a voltage higher than a normal operating voltage and a control for controlling an operation mode of the EEPROM cell. Means, a program mode detecting means for detecting that a high voltage for programming is inputted and setting the control means in a program mode, and at least one of signals for giving a program condition from the control means to the EEPROM cell. On the other hand, the present invention provides a semiconductor memory device including program enable means for providing an effective condition based on a specific code signal.

[0026]

In the semiconductor memory device of the present invention, the program mode detecting means sets the control means in the program mode, and the EEP
When programming a ROM cell, a specific code signal is given to the program enable means in advance,
A signal for giving a programming condition to the EEPROM cell from the control means is made effective in advance, and then the control means is programmed to the EEPROM cell.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention. As shown in the figure, STB
The enable / disable control circuit 5 is
As the / PDATA signal, the serial input of a specific code signal is received, and then the H / L level / STB of the write / read gate control circuit 4 is first received.
It is possible to output a signal, and to provide an HV signal to the EEPROM cell 1 during programming. FIG.
In FIG. 3, the circuits denoted by the same reference numerals as in FIG. 3 indicate the same circuits as in FIG.

FIG. 2 shows STBenable / disab.
3 is a block diagram showing a configuration example of an le control circuit 5. FIG. As shown in the figure, the PDATA signal is a serial signal given in the form of a specific code signal in the program mode, and is input to the inverter circuit 6.
This data is serially transmitted through the NOR circuit 8 and input to the D-type flip-flops 10, 11, 12, and 13 which form a 4-stage shift register. This shift register has a Q output and a / Q output at each stage, and these are taken out in a combination corresponding to a specific code signal and input to the NAND circuit 14.

The D-type flip-flops 10, 1
The reset direct terminals R of 1, 12, and 13 have P.
O. Although the C signal is given, this is a reset signal supplied at the time of power-on and clears the shift register constituted by the D-type flip-flops 10, 11, 12, and 13.

The PCK signal supplied to the clock terminals of the D-type flip-flops 10, 11, 12, and 13 via the inverter circuit 7 and the NOR circuit 9 is the PDATA signal, which is the D-type flip-flops 10, 11, 12, and. It is used as a synchronizing signal to be taken in by 13.

The NOR circuits 8 and 9 have VppEnab.
The le signal is given, and the signal can be passed only in the program mode. In other cases, the outputs of both the NOR circuits 8 and 9 are fixed to the L level.

The NAND circuit 14 is a D flip-flop 1
When the states of 0, 11, 12, and 13 correspond to the specific code signal given as the PDATA signal, the output thereof is set to the L level, and the NOR circuit 15 is set to the signal passing state.

In this case, the / STB signal passes through the NOR circuit 15 and the inverter circuit 16 and is given to the write / read gate control circuit 4.

The operation of the configuration described above will be described below.

In FIG. 1, when data is programmed in the EEPROM cell 1, a writing device (not shown)
Mount the semiconductor memory device, and from this writing device side,
For the V detection circuit 3, Vp higher than the normal operating voltage
Input the p signal.

The HV detection circuit 3 which has detected the Vpp signal is
Write / read gate control circuit 4, address decoder 2 and STβ enable / disable
The VppEnable signal is output to the e control circuit 5 to put them in the program mode.

Next, address data A0 to A7 are given as parallel data to the address decoder 2, and the address decoder 2 decodes this and gives it to the EEPROM cell 1 to set a program address.

Then, the PROGRAM / VERIFY signal is given to the write / read gate control circuit 4 in the program mode, and the serial program data clock-synchronized with the SCKφ signal is sent to the SDAT.
Input as A signal.

During the above operation, when the power is turned on in FIG. O. A specific code signal is written to the D-type flip-flops 10, 11, 12, 13 whose power-on is reset by the C signal.

Writing of this code signal is performed as follows. By the way, the code signal is "1" in this example.
010 ".

First, a serial code signal is input as a PDATA signal, and a clock signal synchronized with this is input as a PCK signal.

The NOR circuits 8 and 9 are connected to the L level VppEn
Since it is possible to pass the signal by the enable signal,
The PDATA signal is given to the D input terminal of the D-type flip-flop 10 through the inverter circuit 6 and the NOR circuit 8. On the other hand, the PCK signal is sent to the inverter circuit 7 and the NOR circuit 9
Through the D-type flip-flops 10, 11, 12, 1
4 clock terminals.

As a result, the PD is generated in 4 clocks of the PCK signal.
The serial code signal of the ATA signal is set in the shift register constituted by the D-type flip-flops 10, 11, 12, and 13.

The code signal "1010" set in the shift register is decoded by the NAND circuit 14. That is, the NAND circuit 14 extracts the logical product condition of the Q outputs of the D-type flip-flops 11 and 13 and the / Q outputs of the D-type flip-flops 10 and 12. As a result, the output of the NAND circuit 14 becomes L level, and the NOR circuit 15 is brought into a signal passing state.

Therefore, the / STB signal is the NOR circuit 1.
5, it becomes possible to input to the write / read gate control circuit 4 via the inverter circuit 16.

After the above operation, the level of the / STB signal is changed, for example, from H level to L level. And the write / read gate control circuit 4
Outputs an HV signal to the EEPROM cell 1 in response to the level of the / STB signal, for example, the L level,
A stress due to a high voltage is applied to the EEPROM cell 1.
As a result, the EEPROM cell 1 is in the programmable state.

At the same time, the program data is supplied as a Write signal from the write / read gate control circuit 4 to the EEPROM cell 1 to write the data.

The operation at the time of verification is performed in the same manner as at the time of programming.

According to the above configuration, after the semiconductor memory device is mounted on the device to be used, the V of the HV detection circuit 3 is changed.
When spike noise is applied to the pp signal terminal and the HV detection circuit 3 malfunctions, the write / read gate control circuit 4 enters the program mode.
Unless a specific code signal is input as the TA signal,
Since the STB signal is not input to the write / read gate control circuit 4, the HV signal is not supplied to the EEPROM cell 1. That is, even if the write / read gate control circuit 4 temporarily enters the program mode due to spike noise, the possibility of overwriting or erasing the program data of the write / read gate control circuit 4 is greatly reduced.

If spike noise is eliminated, HV
Since the detection circuit 3 stops the output of the VppEnable signal, the write / read gate control circuit 4 returns from the program mode and can be used in the read-only mode thereafter.

The D-type flip-flops 10, 11,
Since all of 12 and 13 are reset at power-on, the code signal is not set after that unless the PDATA signal is supplied in the normal procedure.
The probability of erroneous setting or malfunction of the Benable / disable control circuit 5 is very low.

Therefore, the reliability of the program data of the EEPROM cell 1 is significantly improved.

In the above embodiment, the case where 4-bit data is used as the code signal has been illustrated, but this may be any bit data as long as it is data of 1 bit or more. Then, as the number of digits of the code signal increases, the circuit configuration becomes larger, but the reliability is greatly improved.

In the above embodiment, the / STB signal is changed to S
TBenable / disable control circuit 5
Although the configuration of controlling by the example has been illustrated, the same is true even if the condition of enabling or disabling by the code signal is given to another signal which gives an absolute condition for causing the EEPROM cell 1 to program data. Of course, the effect can be obtained. This is appropriately selected depending on the conditions such as sharing the function of the terminals of the semiconductor memory device with other functions.

Further, in the above embodiment, the configuration for giving the program enable condition to only one signal is illustrated, but the program enable condition based on a specific code signal is provided to a plurality of signals. You may give it. In this case, if the same code signal is used for each of a plurality of signals, the reliability can be significantly improved with a simple circuit. Of course, it goes without saying that if the code signal is changed for each signal that gives the program condition, the reliability is dramatically improved.

[0057]

As described above, the semiconductor memory device of the present invention is configured to preset a specific code signal as a condition of a program for the EEPROM, so that the device to which the semiconductor memory device is applied is applied. Even after an unexpected transition to the program mode due to spike noise or the like after overwriting, overwriting and erasing of the EEPROM can be reliably prevented, so that the reliability of the program data can be greatly improved. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is an STBenable / disab having the configuration of FIG.
3 is a block diagram of an le control circuit. FIG.

FIG. 3 is a block diagram of a conventional semiconductor memory device.

[Explanation of symbols]

1 EEPROM cell 2 Address decoder 3 HV detection circuit 4 Write / read gate control circuit 5 STBenable / disable control circuit 6, 7, 16 Inverter circuit 8, 9, 15 NOR circuit 10, 11, 12, 13 D-type flip-flop 14 NAND circuit

Claims (3)

[Claims] 1. An EEPROM cell for performing a program operation by applying a voltage higher than a normal operating voltage, a control means for switching and controlling an operation mode of the EEPROM cell, and detecting that a high voltage for programming is input. At this time, the program mode detecting means for setting the control means to the program mode and the signal for giving the program condition to the EEPROM cell from the control means are effective only when a specific code signal is given to itself. A semiconductor memory device comprising: a program enable unit having: 2. The program enable means is the E
2. The semiconductor memory device according to claim 1, which acts on a signal which gives a condition for giving a high voltage for programming to an EPROM cell. 3. The program enable means is EEP
2. The operation according to a different code signal for each signal which gives a program condition to a ROM cell.
Semiconductor storage device.