JPH09149015A - Clock phase adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust a clock phase automatically in the case of receiving input data with a prescribed period based on a timing of a clock signal of the same period. SOLUTION: An out of synchronism detection circuit 3 uses data and a clock to detect out of synchronism of the data and a timer circuit 4 generates a time-up pulse 101 for each prescribed time while the state 100 of out of synchronism continues. A counter circuit 6 counts the pulse 101 and a selection circuit 2 is controlled depending on the count to select one of delay circuits 1.1-1.N thereby adjusting the phase of the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase adjusting circuit, and more particularly to a clock phase adjusting circuit for fetching input data having a predetermined cycle at the timing of a clock signal having the same cycle as the predetermined cycle.

[0002]

2. Description of the Related Art In a digital data transmission system, a process is performed in which received input data having a constant cycle is fetched at the timing of a clock signal having the same cycle and extracted as a normal data signal. In this case, FIG.
As shown in (A), it is necessary to adjust the clock phase so that the rising change point of the clock falls within the data definite area.

When the phase relationship as shown in FIG. 5 (B) is caused due to the variation of parts and the like, normal data extraction is not performed, and therefore the clock phase is adjusted.
It is necessary to control the phase relationship as shown in (A).

Therefore, in the prior art, as shown in FIG. 6, the phase relationship between the input data and the clock is calculated at each output terminal D.
By observing at OUT and COUT, the delay circuit 1 inserted in the clock line is replaced with one having an appropriate delay time, so that an accurate phase relationship as shown in FIG. 5 (A) is obtained. .

[0005]

In the conventional clock phase adjustment method shown in FIG. 6, the work is performed by observing the phase relationship between the data and the clock and exchanging the delay line with an appropriate delay time. The number of man-hours for the work and the replacement work is generated, which causes a cost increase and also has a problem in reliability.

An object of the present invention is to provide a clock phase adjusting circuit which is low in cost and high in reliability by automatically detecting and adjusting the phase relationship between data and a clock and eliminating manual work. is there.

[0007]

According to the present invention, there is provided a clock phase adjusting circuit for fetching input data having a predetermined cycle at the timing of a clock signal having the same cycle as the predetermined cycle, the phase of the clock signal Of the input data and the clock signal after the phase adjustment by the phase control means and the input data, and detects the out-of-synchronization state of the input data with respect to the clock signal after the phase adjustment. Detecting means, pulse generating means for generating a pulse at fixed intervals while the out-of-synchronization detecting means detects the out-of-synchronization state, and control signal generating means for generating the control signal according to the number of generated pulses. A clock phase adjusting circuit including:

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. Controls to generate a pulse at a constant cycle until the out-of-synchronization state of input data is detected and until this out-of-synchronization state is resolved, and the delay time of the delay circuit for clock delay is sequentially switched at each generation of this pulse. To do.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The data input unit DIN and the data output unit DOUT are directly connected, and the input clock CIN has N delay circuits 1 (N is an integer of 2 or more) having different delay times.
Inputs 1 to 1 · N respectively. These delay circuits 1
Each of the outputs 1 to 1 · N is selectively derived by the selection circuit 2 and becomes the clock output COUT.

The data and the clock output COUT are input to the out-of-synchronization detection circuit 3, and the out-of-synchronization state of the data with respect to the clock is detected. The timer circuit 4 counts up at regular intervals while the out-of-synchronization detection circuit 3 generates the out-of-synchronization state signal 100.

That is, the timer circuit 4 counts a fixed time and generates the time-up pulse 101. At the same time, the timer circuit 4 is reset via the logical OR circuit 5, and if the out-of-synchronization state signal 100 is generated, the time counting is performed again from the reset state, and when the above-mentioned fixed time is reached, the time-up pulse 10 is restarted.
Generates 1 and is reset at the same time.

The above operation is continued during the generation of the out-of-synchronization state signal 100. Therefore, the counter circuit 6 counts the time-up pulse 101 and selectively controls the selection circuit 2 according to the content of the count. By allowing the selection circuit 2 to select, for example, the delay circuits 1 to 1 to N one by one in this order according to the content of the count, the phases of the clocks are sequentially controlled and the out-of-synchronization state is released. . As a result, the out-of-synchronization detection circuit 3 no longer detects the out-of-synchronization state, the generation of the time-up pulse 101 from the timer circuit 4 is stopped thereafter, the counter circuit 6 maintains the count value at that time, and the entire circuit is stabilized. Will be done.

The power-on reset circuit 7 is for resetting the counter circuit 6, the timer circuit 4, and the selection circuit 2 when the power is turned on.
Is reset via the logical OR circuit 5.

FIG. 2 is a block diagram showing a concrete example of the out-of-sync detection circuit 3 of FIG. Referring to FIG. 2, the out-of-sync detection circuit 3 includes a frame pattern detection circuit 31 that detects a synchronous frame signal from data, and a hunting circuit that stops the clock with the out-of-sync signal and detects a frame position pulse during the out-of-sync state. 32, and the forward protection circuit 35 that determines that the frame bit position is out of synchronization when the position of the frame bit cannot be detected consecutively n times because it is not determined to be out of synchronization due to an instantaneous error in the data. The rear protection circuit 36, which determines that the synchronization is recovered when the detection of the frame bit position is detected m times consecutively so that the synchronization is not determined, and the rear protection circuit which is set out of synchronization in the front protection circuit Set / reset circuit 37 that is reset by the synchronization recovery in step S31, the match detection signal of the frame pattern detection circuit 31, and the hunting Circuit 3
It is composed of an AND circuit 33 having two inputs of the output of 2 and an AND circuit 34 having two inputs of the mismatch detection signal of the frame pattern detection circuit 31 and the output of the hunting circuit 32.

FIG. 3 shows the frame pattern detection circuit 31 of FIG.
And a specific example of the hunting circuit 32. In the frame pattern detection circuit 31, first, the data n bits in the n-bit shift register 310 and the n-bit soft register 3 one frame before by the one-frame delay circuit 311 are used.
The pattern with the data n bits in 12 is compared by the frame pattern matching circuit 313. The comparison timing is determined by the timing of the frame position pulse F from the hunting circuit 32.

If a match is detected by this comparison, a match signal is output, and if no match is found, a non-match signal is output, and these are input to the AND circuits 33 and 34, respectively.

The hunting circuit 32 detects the frame position with the input clock COUT.
A frame position pulse F synchronized with the frame pattern by counting the clock in the frame synchronization counter 321
Occurs.

The inhibition circuit 320 inhibits the input clock during the generation of the out-of-synchronization state signal (output from the set / reset circuit 37 in FIG. 2), and otherwise suppresses the input clock. It is transmitted to the frame synchronization counter 321. Therefore, the frame synchronization counter 321 always generates the frame position pulse according to the free-running clock in order to detect the synchronization recovery during the out-of-synchronization state (during hunting).

FIG. 4 (A) shows an example of the waveform of each signal in FIG. 3 at the time of shifting from the front protection state to the hunting state, and is input to the frame synchronization counter 321 from the time of shifting from the front protection state to the hunting state. The clock to be stopped is stopped by the inhibition circuit 320, and the frame position is always indicated by the frame position pulse. FP indicates a frame pulse.

On the contrary, as shown in FIG. 4B, the clock is changed to the frame synchronization counter 32 from the time when the frame pattern is detected in the hunting state and the state shifts to the rear protection state.
1, and a frame position pulse F is generated.

The AND circuit 33 counts up the rear protection circuit 36 and resets the front protection circuit 35 when the frame patterns match in the hunting state,
The AND circuit 34 is configured to reset the rear protection circuit 36 and count up the front protection circuit 35 when the frame patterns do not coincide with each other in the hunting state.

The frame pattern detection circuit 31 is merely an example, and it is obvious that various modifications can be made.

[0024]

As described above, according to the present invention, the delay which has been manually performed by detecting the loss of synchronism and automatically selecting the delay lines connected in advance with different delay times. The number of man-hours for line replacement work can be reduced, which is economically advantageous.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a partial specific example of the block diagram of FIG.

FIG. 3 is a diagram showing a partial specific example of the block diagram of FIG.

FIG. 4 is a time chart of signals of respective parts showing an operation example of the block of FIG.

FIG. 5 is a diagram showing a phase relationship between data and clocks.

FIG. 6 is a diagram showing an example of a conventional clock phase adjustment circuit.

[Explanation of symbols]

 1 · 1 to 1 · N delay circuit 2 selection circuit 3 loss of synchronization detection circuit 4 timer circuit 5 logical OR circuit 6 counter circuit 7 power-on reset circuit 31 frame pattern detection circuit 32 hunting circuit 33, 34 AND circuit 35 forward protection circuit 36 Rear protection circuit 37 Set / reset circuit

Claims (5)

[Claims] 1. A clock phase adjusting circuit for fetching input data of a predetermined cycle at the timing of a clock signal of the same cycle as the predetermined cycle, wherein the phase control controls the phase of the clock signal in accordance with a control signal. Means, an out-of-synchronization detection means for detecting an out-of-synchronization state of the input data with respect to the clock signal after the phase adjustment by the clock signal after the phase adjustment by the phase control means and the input data, and the out-of-synchronization detection means. A clock phase characterized by including pulse generation means for generating a pulse at constant intervals while an out-of-synchronization state is detected, and control signal generation means for generating the control signal according to the number of generated pulses. Adjustment circuit. 2. The clock phase adjusting means receives the lock clock signal as an input and has a plurality of delay means having different delay times, and outputs of the plurality of delay means alternatively according to the control signal. 2. The clock phase adjusting circuit according to claim 1, further comprising: selecting means for deriving. 3. The pulse generating means includes timer means for generating the pulse by counting the certain period of time in response to the synchronization loss detection of the synchronization loss detecting means and resetting by the pulse. Claim 1
Alternatively, the clock phase adjustment circuit described in 2. 4. The clock phase adjusting circuit according to claim 2, wherein the control signal generating means has a counting means for counting the pulses, and the count output is used as the control signal. 5. The fixed time is a fixed time longer than a sync pull-in detection time after the sync loss detecting means detects the sync loss.
4. The clock phase adjustment circuit according to any one of 4 above.