JPH09148631A - Driving circuit for light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cut down the rise time and the fall time of a light emitting element, and to increase the switching speed of the photooutput of the light emitting element. SOLUTION: A signal Vb , which is in the logical condition reverse to a signal Va of the logical condition same as an inputted digital signal, is outputted from an input circuit 2. Reference voltage Vrefa and Vrefb , which level changes to the inverse direction and to the same direction of the logic level of the digital signal based on the Va and Vb , are generated by reference voltage generators 3a and 3b. The changing range of reference voltage of the Vrefb is larger than that of the Vrefa . The magnitude relation between Va and Vb against the Vrefa and the Vrefb is judged by differential comparators 4a and 4b, and comparative judgment signals Vb1 (positive logic) and Vb2 (negative logic) for the two values are outputted. As a result, the Vb2 becomes a lag phase against the Bb1 . Pulse currents Ia and Ib are grown from the Vb1 and Vb2 , and a driving current Id , which is formed by combining the above-mentioned pulse currents, is allowed to flow to the b2, light emitting diode 1. A peaking part is added to the rising and the falling of the driving current Id based on the above-mentioned phase difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for driving a light emitting device such as a light emitting diode or a laser diode which is preferably used for optical communication.

[0002]

2. Description of the Related Art In a conventional light emitting element driving circuit, various improvements have been made in order to improve the switching characteristics of the light emitting element. As a technique for proposing such an improvement, for example, there are the following three configurations.

(1) "Optical semiconductor element driving circuit" (disclosed in JP-A-2-272778) (2) "Optical semiconductor element driving circuit" (JP-A-5-2965)
(Disclosed in Japanese Patent Publication No. 5) (3) "Light emitting element drive circuit" (Japanese Patent Laid-Open No. 5-121783)
Each of the drive circuits described in (1) to (3) is hereinafter referred to as a first to a third drive circuit.

The first driving circuit, as shown in FIG.
The switch circuit 21 drives the light emitting element 22. In this first drive circuit, the resistors 23-25
As a result, a forward pre-bias voltage is applied across the light emitting element 22 and the speed-up capacitor 2
6, the light emitting element 22 is quickly charged and discharged at the transition of switching by the switch circuit 21. As a result, it becomes possible to drive the light emitting element 22 at high speed and with a reduced amount of jitter.

The second drive circuit, as shown in FIG.
The light emitting element 32 is driven by the switch circuit 31 that outputs two signals having different polarities. In this second drive circuit, the diodes 33 and 34 and the resistor 3
A forward pre-bias voltage is applied across the light emitting element 32 by 5.36.

In the above second drive circuit, the light emitting element 32
Is biased even when there is no signal, so that electric charges can be quickly accumulated in the junction capacitance of the light emitting element 32 when turned on. Thereby, the switching of the light emitting element 32 can be speeded up and the amount of jitter can be suppressed.

In the third drive circuit, as shown in FIGS.
As shown in FIG. 5, the retiming circuit 41 reproduces an input data signal which takes a binary logic in synchronization with the clock signal, and the output signal (reproduced data signal) is converted into a pulse current by the pulse conversion circuit 42 to generate a light emitting element. 43 is supplied as a drive current. On the other hand, the output signal of the retiming circuit 41 is waveform-shaped by being differentiated by the differentiating circuit 44 at the rising edge and the falling edge thereof, respectively, and further, a DC bias circuit 45 gives a DC bias.

As a result, the output of the differentiating circuit 44 is added as a peaking current to the drive pulse given to the light emitting element 43, and the electric charge accumulated in the light emitting element 43 is forcibly discharged by this peaking current. As a result, it is possible to obtain an optical output waveform with little light emission delay, short rise time and fall time of the light output of the light emitting element 43, and little jitter.

[0009]

In the first driving circuit described above, the magnitude and duration of the transient current supplied to the light emitting element 22 is determined by the junction capacitance of the light emitting element 22 and the capacitance of the speed-up capacitor 26. It is determined by the ratio. Therefore, the magnitude and duration of the transient current are very difficult to set, and change greatly depending on the junction capacitance. Therefore, the target appropriate transient current cannot be obtained, and the performance of the individual drive circuits during mass production becomes unstable.

In the second drive circuit described above, the switching of the light emitting element 32 is speeded up by applying the pre-bias voltage, but the application of the pre-bias voltage is also limited, and further switching speed can be increased. I can not cope.
Therefore, the light emitting element 32 cannot be driven at a frequency exceeding the switchable frequency band of the light emitting element 32.

In the above third drive circuit, if a phase difference occurs between the output signal of the pulse conversion circuit 42 and the output signal of the DC bias circuit 45, there is a risk that the peaking current will not be added to the desired portion of the drive pulse current. is there. If the peaking current is not properly added, the optical output waveform may be distorted, and the performance of the light emitting element 43 may be degraded. In order to avoid such inconvenience, it is necessary to perform very precise phase adjustment of a fraction or less of the target rise time and fall time of the optical output, which cannot be a realistic method.

As described above, according to each of the drive circuits described above,
When the operating speed (frequency) band of each drive circuit and the light emitting element is not sufficient for the frequency of the input signal, the switching of the light emitting element cannot follow the input signal and the current pulse for driving the light emitting element becomes off level. A slight amount of light continues to be emitted after that.

When a light emitting diode having a light wavelength of 660 nm is used as the light emitting element, the upper limit of its operating frequency is generally the cutoff frequency f _c when the gain of the light emitting diode is lowered by 3 dB. This cutoff frequency f
_c is represented by f _c ≈0.35 / t _r , where t _r is the rise time required for the gain to transition from 10% to 90% of the steady value. Therefore, the t _r each 30nse
When c, 20 nsec, and 10 nsec, f _c are 11.7 MHz, 17.5 MHz, and 35.0 MHz, respectively.
Becomes

As described above, the operating frequency of the light emitting diode is t _r and the fall time (gain is 90 which is a steady value).
% To 10%).

In the conventional drive circuit, in contrast to the above operation speed being insufficient, a bias current is caused to flow through the light emitting element even at the off level, a peaking current is added at the time of switching the drive current pulse, or a combination of these is applied. Therefore, we are trying to reduce the generation delay of the light emitting element, reduce the jitter, and shorten the rise time and fall time of the optical output, but it is not possible to obtain a sufficient effect or it is theoretically difficult to realize it. The point is that it is a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to shorten the rise time and fall time of a light emitting element to increase the switching speed of the light output of the light emitting element.

[0017]

In order to solve the above-mentioned problems, a drive circuit for a light-emitting element according to the present invention has two signals, one of which has the same logic state as an input digital signal and the other of which has the opposite logic state. A signal generating means for generating a signal, a phase difference giving means for giving a phase difference to the change in the logic level of the two signals so that the signal on the negative logic side has a delayed phase, and a phase difference given by the phase difference giving means. And a current generating means for generating a drive current having a phase difference based on the change in the logic level, and two drive currents from the current generating means are supplied to the light emitting element together.

In the above arrangement, the phase difference giving means gives a phase difference to the logic levels of the two signals from the signal generating means so that the negative logic side has a delayed phase. Then
The current generating means generates two drive currents based on the change in the logic level. Since this drive current has the above phase difference, the drive current is also supplied to the light emitting element to correspond to the signal on the positive logic side that should be the signal component of the above two signals. The peaking portion is added to the rising edge and the falling edge of the signal component of the drive current.

When such a driving current is supplied to the light emitting element, the junction capacitance of the light emitting element is quickly charged and discharged,
The rising time and the falling time of the light emitting element can be shortened. Moreover, since a current flows through the light emitting element even when the light emitting element is turned off, the charging / discharging time of the junction capacitance can be reduced. Further, since the amount of peaking is determined by the phase difference, the peaking portion can be added to the drive current relatively easily.

The phase difference giving means in the above-mentioned drive circuit specifically changes the level in the opposite direction to the change in the logic level of the digital signal corresponding to the positive logic side of the two signals, while it is negative. A reference voltage generator that generates two reference voltages whose levels change in the same direction as the change in the logic level of the digital signal corresponding to the logic side and has different change widths, and two signals for the two reference voltages. And a comparator that represents the magnitude relationship by a binary signal.

In the above configuration, since the level of the reference voltage generated by the reference voltage generator changes, the determination level of the magnitude relation between the two signals with respect to the reference voltage changes in the comparator. Therefore, since the change widths of the two reference voltages are different, the determination levels of the magnitude relations of the two signals are different, and the two 2's obtained as a result of the determination are different.
A phase difference occurs in the value signal.

As described above, in the above structure, the phase difference can be easily provided in the binary signal by adjusting the change width of the reference voltage. Therefore, adjustment when giving a phase difference to the logic levels of two signals becomes easier than when a delay circuit or the like is used. Further, the reference voltage generator as described above can be configured by only slightly modifying the differential amplifier and the like, and the circuit does not become complicated.

The drive circuit comprising the reference voltage generator and the comparator is preferably of two systems in which the reference voltage generator, the comparator and the current generating means have the same characteristics corresponding to two signals respectively. It is composed of a circuit.

As a result, a phase difference hardly occurs in the signal processing between the circuits of both systems, so that the influence of such a phase difference does not affect the drive current. Further, since the above-mentioned drive circuit is configured to provide a phase difference between the signals between the two systems, even when the above-mentioned phase difference occurs, the phase difference is determined by the logical level of the two signals. It can be absorbed by the phase difference. Further, the circuit configuration can be simplified by using the circuits of two systems having the same characteristics.

In addition to the above drive circuit, the phase difference giving means in the above drive circuit has one of the two signals as a reference, and the level difference of the other with respect to this, the level difference between the two signals becomes larger than a predetermined value. It is also possible to have a comparator which is represented by a binary signal which is sometimes inverted and which is set differently for two signals which can be used as a reference for a predetermined value.

In the above arrangement, the comparator determines the magnitude relation of the other of the two signals with reference to one of the two signals. This determination is made at a position delayed from the position where the two signals intersect due to the predetermined value of the level difference between the two signals. Therefore, since the predetermined value is different for the two signals, the above determination time is also different for the two signals, and a phase difference occurs between the two binary signals obtained as a result of the comparison.

As described above, in the above configuration, the phase difference can be easily provided in the binary signal by adjusting the predetermined value. Therefore, adjustment when giving a phase difference to the logic levels of two signals becomes easier than when a delay circuit or the like is used. Further, the reference voltage generator as in the above configuration is not required, and the circuit can be further simplified.

In the drive circuit including the comparator, preferably, the comparator and the current generating means are composed of two circuits having the same characteristics corresponding to two signals.

As a result, a phase difference hardly occurs in the signal processing between the circuits of both systems, so that the influence of such a phase difference does not affect the drive current. Further, since the above-mentioned drive circuit is configured to provide a phase difference between the signals between the two systems, even when the above-mentioned phase difference occurs, the phase difference is determined by the logical level of the two signals. It can be absorbed by the phase difference. Further, the circuit configuration can be simplified by using the circuits of two systems having the same characteristics.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the drive circuit according to the present embodiment has an input circuit 2 and reference voltage generators 3a and 3b.
And differential comparators 4a and 4b and differential amplifiers 5a and 5b.

The input circuit 2 as a signal generating means is configured to shape the waveform of a digital signal inputted from the outside and to output a signal whose logic state is the same as that of the digital signal and which is the opposite signal. Reference voltage generator 3a ・ 3
b is adapted to generate a reference voltage used in the differential comparators 4a and 4b based on the signals from the positive logic side output and the negative logic side output of the input circuit 2, respectively.

The differential comparator 4a compares the reference voltage V _refa from the reference voltage generator 3a with the signal from the positive logic side output, and when the signal is larger than the reference voltage V _refa, it is at a high level. While outputting a signal, it outputs a low level signal in the opposite case. The differential comparator 4a also outputs a signal whose logical level is opposite to that of the above signal. The differential comparator 4b compares the reference voltage V _refb from the reference voltage generator 3b with the signal from the above negative logic side output and, like the differential comparator 4a, two signals of different logic levels. Is output.

As shown in FIG. 2, the reference voltage generators 3a and 3b change the values of the reference voltages V _refa and V _refb according to the input voltage (level of the input digital signal). Reference voltage V _REFA is input voltage at a higher range T ₂ input voltage threshold V _th becomes a low level as compared with the low range T ₁ than the threshold V _th is, the reference voltage V _refb a reference voltage V
_{It has the} opposite level relationship to _refa . In addition, the level decrease width Δ
The decrease width ΔV _refb is larger in V _refa · ΔV _refb . Further, V _refa > V _refb in the range T ₁ , and V in the region T ₂ .
_refa <V _refb .

The reference voltage generators 3a and 3b are specifically constructed as shown below in order to generate the above-mentioned reference voltages V _refa and V _refb .

As shown in FIG. 3A, the reference voltage generator 3a is based on a differential amplifier circuit having a pair of transistors 6a and 6b. The negative logic side output of the input circuit 2 is connected to the base of the transistor 6a, and the transistor 6a
The positive logic side output of the input circuit 2 is connected to the base of b. The collectors of the transistors 6a and 6b are connected to the power supply via the resistors 7a and 7b having the same resistance value, and are also connected to each other via the resistor 8. The emitters of the transistors 6a and 6b are both connected to the constant current source 9.

As shown in FIG. 3B, in the reference voltage generator 3b, the positive logic side output of the input circuit 2 is connected to the base of the transistor 6a, and the negative logic side output of the input circuit 2 is connected to the base of the transistor 6b. The reference voltage generator 3a has the same structure as that of the reference voltage generator 3a except that is connected.

In the above reference voltage generator 3a, when the input voltage is at a high level (higher than the threshold value V _th ),
Since the high-level signal is output from the positive logic side output and the low-level signal is output from the negative logic side output, the transistor 6a is turned off and the transistor 6b is turned on.
At this time, a current flows into the transistor 6b via the resistors 7a and 8 and the resistor 7b.

On the other hand, when the input voltage is at a low level (a level lower than the threshold value V _th ), a low level signal is output from the positive logic side output and a high level signal is output from the negative logic side output. The transistor 6a turns on and the transistor 6b turns off. At this time, the transistor 6
A current flows into a through the resistors 7a and 7b.8.

If the current flowing through the resistor 7b is I ₁ when the input voltage is at the high level and I ₂ is the current flowing through the resistor 7b when the input voltage is at the low level, then I ₁ > I It becomes ₂ . Therefore, when the input voltage is at the high level, the voltage drop due to the resistor 7b becomes larger, and the reference voltage V _refa becomes smaller than when the input voltage is at the low level.

In the above reference voltage generator 3b, the input circuit 2 for each base of the transistors 6a and 6b is used.
The connection relationship between the positive logic side output and the negative logic side output is opposite to that of the reference voltage generator 3a. For this reason, the relationship of the level of the reference voltage V _refb when the input voltage is at the high level and when it is at the low level is opposite to that of the reference voltage generator 3a.

By such an operation, the reference voltage V _refa becomes higher than the reference voltage V _refb when the input voltage is low level, and the reference voltage V _refb when the input voltage is high level.
_refa becomes lower than the reference voltage V _refb . Further, the above-described decrease width ΔV _refa · ΔV _refb is determined by the resistance value of the resistor 8.

Differential amplifiers 5a.5 as current generating means
b is adapted to convert each two sets of signals (voltage) from the differential comparators 4a and 4b into a current. Specifically, the differential amplifiers 5a and 5b are both input 1
When the difference between the pair of signals is smaller than a predetermined value, no current is passed,
When the difference exceeds a predetermined value, current is passed. The outputs of the differential amplifiers 5a and 5b are connected to the cathode of a light emitting diode 1 as a light emitting element, and the currents of the differential amplifiers 5a and 5b are combined and flow through the light emitting diode 1.

In the drive circuit configured as described above, two pulse signals V whose logic levels are opposite to each other based on the input digital signal by the input circuit 2.
_a · V _b is output. On the other hand, the reference voltage generators 3a-3
As described above, the reference voltage V _refa · V _refb whose level is changed according to the logic level of the digital signal is output from _b .

As shown in FIG. 4, in the differential comparator 4a,
The pulse signal V _a changes from low level to high level,
When it changes to the low level again, the pulse signal V _a is compared with the high reference voltage V _refa at the rising edge and with the low reference voltage V _refa at the falling edge. As a result of the comparison,
The differential comparator 4a outputs a positive logic comparison determination signal V _a1 and a negative logic comparison determination signal V _a2 .

On the other hand, in the differential comparator 4b, the pulse signal V
_{Since b} is changed by the pulse signal V _a and opposite logic level, the pulse signal V _b is lower at the fall reference voltage V
_It is compared with _refb and compared with a high reference voltage V _refb at the rising _edge . As a result of the comparison, the differential comparator 4b outputs a positive logic comparison determination signal _Vb1 and a negative logic comparison determination signal _Vb2 .

As described above, the levels of the reference voltages V _refa and V _refb are reversed, so that the comparison / determination signal V _a1 has a time t _S1 phase advanced at the time of rising and a time period at the time of falling relative to the comparison / determination signal V _b1. Go to t _S2 . Further, the comparison determination signal V _a2 has an inverse relationship to the above case at the rising edge and the falling edge, but a similar phase difference occurs with respect to the comparison determination signal V _b2 when the level changes.

From the above operation, the reference voltage generators 3a-3
It can be seen that b and the differential comparators 4a and 4b function as phase difference providing means.

As shown in FIG. 5, in the differential amplifier 5a,
The comparison / determination signals V _a1 and V _a2 are converted into pulse currents I _a, and in the differential amplifier 5 b, the comparison / determination signals V _b1 and V _b2 have a pulse current I _a smaller in amplitude (about 10%) than the pulse current I a. Convert to _b . For example, the pulse current I _a is 20 m
If the amplitude is A, the pulse current I _b has an amplitude of 2 mA. This difference in amplitude is due to the difference in amplification degree between the differential amplifiers 5a and 5b.

The rise of this result, pulse current between the fall of the rise and the pulse current I _b of I _a, it occurs a phase difference between the time t _S1 ', falling a pulse current I _b of the pulse current I _a And a phase difference of time t _S2 'is generated.

At this time, the driving current I _d, which is _{a combination} of the pulse currents I _a and I _b, flows through the light emitting diode 1. The drive current I _d has a positive peaking portion of the peaking amount ΔI _{p1 at} the rising edge and a negative peaking portion of the peaking amount ΔI _{p2 at} the falling edge. Therefore, the light emitting diode 1
The optical output of has a waveform having a similar peaking portion.

As described above, in the drive circuit according to the present embodiment, by combining the pulse currents I _a and I _b having the phase difference, the drive current I _d having the peaking portions at the falling and rising edges is obtained. It has gained. As a result, as shown in FIG. 6, the junction capacitance of the light emitting diode 1 is quickly charged and discharged, and the rising time and the falling time of the light emitting diode 1 can be shortened.
Therefore, the light emitting diode 1 can be driven in a frequency band higher than the original operating frequency of the light emitting diode 1.

[0053] In the figure, t _r represents the rise time until the gain of the light emitting diode 1 is changed from 10% to 90% of the steady-state value, t _f is the gain of the steady-state value 9
The fall time from 0% to 10% is shown.

A current of ΔI _p2 flows through the light emitting diode 1 even when it is turned off. Therefore, the charging / discharging time of the junction capacitance of the light emitting diode 1 can be shortened as compared with the case where no current flows at the time of OFF.

Further, since the peaking amount ΔI _p1 · ΔI _p2 is determined by the amplitude of the pulse current I _a · I _b and the time t _S1 '· t _S2 ', the peaking portion is relatively easily added to the drive current. be able to.

[0056] Further, in this driving circuit, the driving current I and the system for generating a pulse current I _a as the signal component of _d, the drive current I _d the pulse current I as a peaking component of
_Since the system that generates _b is composed of an equivalent circuit, there is almost no phase difference in signal processing between the two systems. Moreover, even if there is a phase difference due to signal processing,
Originally, since the present drive circuit is configured to provide a phase difference between the signals of both systems, the above phase difference does not pose a problem.

Here, a modification of the present embodiment will be described.

As shown in FIG. 7, the drive circuit according to this modification includes an input circuit 2, reference voltage generators 3a and 3b, and drive current generators 10a and 10b, like the drive circuit described above. ing. The drive current generators 10a and 10b have the functions of the differential comparators 4a and 4b and the differential amplifier 5a and 10b.
It also has the function of 5b. Drive current generator 10a
More specifically, as shown in FIG. 8, 10b is a transistor 12 into which the reference voltage from the reference voltage generators 3a and 3b is input to the base via the transistor 11, and a transistor in which the transistor 12 and the emitter are commonly connected. 1
And 3.

The drive current generator 10 having the above structure
In a-10b, the transistor 12, 13 are operated on the basis of the output signal of the amplified reference voltage from the input circuit 2 in the transistor 11, the pulse current I _{a-I b} shown in FIG. 5 is a transistor 13, Flowing through 13. Therefore, like the drive circuit described above, a peaking portion is provided for the drive current I _d flowing through the light emitting diode 1.

In this modification, the drive current generator 10a.1
By using 0b, the configuration of the drive circuit can be simplified.

[Second Embodiment] The following will describe another embodiment of the present invention in reference to FIG. 4, FIG. 5, FIG. 9 and FIG. In the present embodiment, constituent elements having the same functions as those of the first embodiment will be designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 9, the drive circuit according to the present embodiment has an input circuit 2 and differential comparators 14a and 14b.
And differential amplifiers 5a and 5b.

A differential comparator 14a as a phase difference providing means.
14b is a circuit having a hysteresis characteristic in the comparison operation, and receives a set of signals from the positive logic side output and the negative logic side output of the input circuit 2. As shown in FIG. 10, the differential comparators 14a and 14b invert the logical level of the output signal when the logical level of the pair of input signals is inverted and then the level difference between the two signals exceeds a predetermined value. It is designed to let you.

Hysteresis width ΔH _a of the differential comparator 14a
Is larger than the hysteresis width ΔH _b of the differential comparator 14b, and is set so as to generate an appropriate amount of peaking portion similar to that of the drive circuit according to the first embodiment.

Also in the drive circuit configured as described above, as shown in FIG. 4, the comparison determination signals V _a1 and V _b1 are:
A phase difference of time t _S1 occurs when rising, and a phase difference of time t _S2 occurs when falling. In addition, the comparison determination signal V _a2
V _b2 has a relationship opposite to that in the above case at the time of rising and at the time of falling, but a similar phase difference occurs when the level changes.

Further, as shown in FIG. 5, the differential amplifier 5a
The pulse current I _a flowing into the differential amplifier 5b and the pulse current I _b flowing into the differential amplifier 5b have a phase difference of time t _S1 ′ · t _S2 ′. Moreover, the amplitude of the pulse current I _b, the amplitude is smaller than the pulse current I _a. Thereby, the light emitting diode 1
A drive current I _d , which is a combination of the pulse currents I _a and I _b, flows through the drive current I _d . The drive current I _d is provided with peaking portions having peaking amounts ΔI _p1 and I _{p2 at} the rising edge and the falling edge, respectively. Therefore, the light output of the light emitting diode 1 also has a waveform having a similar peaking portion.

As described above, also in the drive circuit according to the present embodiment, the rise time and the fall time of the light emitting diode 1 can be shortened by obtaining the drive current I _d having the peaking portion. Therefore, the light emitting diode 1 can be driven in a frequency band higher than the original operating frequency of the light emitting diode 1.

Further, since the current of ΔI _p2 flows through the light emitting diode 1 even when it is turned off, the charging / discharging time of the junction capacitance of the light emitting diode 1 can be shortened. Further, the adjustment of the peaking amount ΔI _p1 · ΔI _p2 is performed by the pulse current I _a · I.
_This can be done relatively easily by the amplitude of _b and the time t _S1 ′ · t _S2 ′.

[0069] Further, in this driving circuit, the driving current I and the system for generating a pulse current I _a as the signal component of _d, the drive current I _d the pulse current I as a peaking component of
There is almost no phase difference in the signal processing between the systems that generate _b, and even if there is a phase difference due to the signal processing,
If the phase difference for forming the peaking portion is adjusted, the above phase difference does not matter.

The present invention is not limited to the configurations of the drive circuits described in the present embodiment and the first embodiment, and variously modified drive circuits can be applied. Of course.

[0071]

As described above, the drive circuit for a light emitting element according to claim 1 of the present invention outputs a signal having the same logic state as an input digital signal and two signals having the opposite logic states. A signal generating means for generating, a phase difference giving means for giving a phase difference to the change of the logical levels of the two signals so that the negative logic side has a delayed phase, and a change of the logical level given the phase difference by the phase difference giving means. And a current generating means for generating a drive current having the phase difference, and two drive currents from the current generating means are supplied together to the light emitting element.

As a result, since the two drive currents obtained based on the two signals have the phase difference as described above, when the drive currents are also supplied to the light emitting element, the drive currents are A peaking portion is added to the rising edge and the falling edge of the signal component of.

Therefore, when the above drive current is supplied to the light emitting element, the junction capacitance of the light emitting element is quickly charged and discharged, and the rise time and fall time of the light emitting element can be shortened. Also, the light emitting element is turned off.
Since the current flows even at times, the light emission delay can be shortened and the jitter can be reduced. Furthermore, since the amount of peaking is determined by the phase difference,
Unlike the peaking drive method based on the capacitance component, the peaking drive current does not vary due to the variation in the junction capacitance of the light emitting element. Therefore, when the drive circuit is mass-produced, it is not necessary to provide the drive circuit with an adjusting function.

Therefore, if this drive circuit is adopted, not only can the light emitting element be driven in a frequency band higher than the original operating frequency of the light emitting element, but also an optical output with less pulse width distortion and jitter can be obtained. Has the effect.

A light emitting element drive circuit according to a second aspect of the present invention is the light emitting element drive circuit according to the first aspect, wherein the phase difference providing means corresponds to the positive logic side of the two signals. Then, while the level changes in the direction opposite to the change in the logic level of the digital signal, the level changes in the same direction as the change in the logic level of the digital signal corresponding to the negative logic side, and the two change widths are different. This configuration has a reference voltage generator that generates a reference voltage and a comparator that represents the magnitude relationship of two signals with respect to the two reference voltages as a binary signal.

As described above, since the change widths of the two reference voltages are different, the determination levels of the magnitude relationship of the two signals are different, and the two binary signals obtained as a result of the determination have a phase difference. Occurs. Therefore, the phase difference can be easily provided in the binary signal by adjusting the change width of the reference voltage. Therefore, the adjustment of the phase difference between the logical levels of the two signals becomes simpler than when a delay circuit or the like is used. Further, the reference voltage generator as described above,
It can be configured by only slightly changing the differential amplifier and the like, and the circuit does not become complicated.

Therefore, if the above structure is adopted, it is possible to provide the drive circuit for the light emitting element at a low cost and to simplify the manufacture of the drive circuit.

According to a third aspect of the present invention, there is provided a drive circuit for a light emitting element according to the second aspect, wherein the reference voltage generator, the comparator, and the current generating means are each two. 2 with the same characteristics corresponding to the signal
Since it is composed of system circuits, there is almost no phase difference in signal processing between the circuits of both systems, and the influence of such phase difference does not affect the drive current. Further, since the above-mentioned drive circuit is configured to provide a phase difference between the signals between the two systems, even when the above-mentioned phase difference occurs, the phase difference is the same as the logical level of the two signals. It is absorbed by the phase difference. Further, the circuit configuration can be simplified by using the circuits of two systems having the same characteristics.

Therefore, if the above configuration is adopted, it is possible to provide a highly reliable drive circuit.

According to a fourth aspect of the present invention, there is provided a drive circuit for a light emitting element according to the first aspect, wherein the phase difference providing means uses one of two signals as a reference and the other of the two signals as a reference. The magnitude relationship of the two signals is represented by a binary signal that is inverted when the level difference between the two signals becomes larger than a predetermined value, and a comparator that is set to be different for each of the two signals that can be used as a reference is used. It is a configuration that has.

As described above, the two predetermined values are different from each other, so that the timings for determining the magnitude relationship of the two signals are different. Therefore, the phase difference can be easily provided in the binary signal by adjusting the predetermined value. Therefore, the adjustment of the phase difference between the logical levels of the two signals becomes simpler than when a delay circuit or the like is used. Further, the reference voltage generator as in the above-mentioned configuration is not required, and the circuit can be further simplified and the circuit can be simplified.

Therefore, if the above configuration is adopted, it is possible to provide a drive circuit for the light emitting element at a low cost and to simplify the manufacture of the drive circuit.

According to a fifth aspect of the present invention, there is provided a drive circuit for a light emitting element according to the fourth aspect, wherein the comparator and the current generating means have characteristics corresponding to two signals. Since it is composed of circuits of two equal systems, there is almost no phase difference in signal processing between the circuits of both systems, and even if such a phase difference occurs, the phase difference is the same as that of two signals. It is absorbed by the phase difference of the logic level. Moreover, the circuit configuration can be simplified by using two systems of circuits having the same characteristics.

Therefore, if the above configuration is adopted, it is possible to provide a highly reliable drive circuit as in the drive circuit according to the third aspect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a light emitting element drive circuit according to an embodiment of the present invention.

FIG. 2 is a graph showing reference voltages generated by two reference voltage generators in the driving circuit of FIG.

FIG. 3 is a circuit diagram showing a detailed configuration of the two reference voltage generators.

FIG. 4 is a waveform diagram showing a phase relationship of output signals of the differential comparator in the light emitting element drive circuit according to the embodiment and the other embodiment of the invention.

FIG. 5 is a waveform diagram showing waveforms of an output current of a differential amplifier, a drive current of a light emitting diode, and the like in a light emitting element drive circuit according to one embodiment and another embodiment of the present invention.

6 is a graph showing the relationship between the peaking amount and the rise time and fall time of a digital signal in the drive circuit of FIG.

FIG. 7 is a block diagram showing a configuration of a light emitting element drive circuit according to a modification of the embodiment of the present invention.

8 is a circuit diagram showing a detailed configuration of the drive circuit shown in FIG.

FIG. 9 is a block diagram showing a configuration of a light emitting element drive circuit according to another embodiment of the present invention.

10 is a waveform diagram showing the phase relationship of the output signals of the differential comparator in the drive circuit of FIG.

FIG. 11 is a block diagram showing a configuration of a drive circuit for a conventional light emitting element.

FIG. 12 is a block diagram showing the configuration of another conventional drive circuit for a light emitting element.

FIG. 13 is a block diagram showing the configuration of still another drive circuit for a conventional light emitting element.

14 is a waveform chart showing the operation of the drive circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 light emitting diode (light emitting element) 2 input circuit (signal generating means) 3a / 3b reference voltage generator (phase difference giving means) 4a / 4b differential comparator (phase difference giving means) 5a / 5b differential amplifier (current generation) Means) 14a and 14b Differential comparator (Phase difference giving means)

Claims (5)

[Claims] 1. A signal generating means for generating two signals having the same logic state as an input digital signal and an opposite logic state, and a logic of the two signals so that a negative logic side has a delay phase. A phase difference imparting means for imparting a phase difference to the level change; and a current generating means for generating a drive current having the phase difference based on the change in the logical level to which the phase difference imparting means imparts the phase difference, A drive circuit for a light emitting element, characterized in that the two drive currents from the current generating means are combined and supplied to the light emitting element. 2. The phase difference providing means changes the level in the direction opposite to the change of the logic level of the digital signal corresponding to the positive logic side of the two signals, while the digital difference corresponds to the negative logic side. A reference voltage generator that generates two reference voltages whose levels change in the same direction as the change in the logic level of the signals and whose change widths are different, and a binary signal indicating the magnitude relationship between the two signals with respect to the two reference voltages. The light emitting element drive circuit according to claim 1, further comprising: 3. The reference voltage generator, the comparator, and the current generating means are constituted by circuits of two systems having equal characteristics corresponding to two signals, respectively. Light emitting element drive circuit. 4. The phase difference imparting means uses one of the two signals as a reference to represent the magnitude relationship of the other with a binary signal which is inverted when the level difference between the two signals becomes larger than a predetermined value. The light emitting element drive circuit according to claim 1, further comprising a comparator in which two signals whose predetermined values can be used as a reference are set to be different from each other. 5. The drive circuit for a light emitting element according to claim 4, wherein the comparator and the current generating means are composed of circuits of two systems having equal characteristics corresponding to two signals.