JPH09135167A - Phase locked loop circuit device - Google Patents

Phase locked loop circuit device

Info

Publication number
JPH09135167A
JPH09135167A JP7317285A JP31728595A JPH09135167A JP H09135167 A JPH09135167 A JP H09135167A JP 7317285 A JP7317285 A JP 7317285A JP 31728595 A JP31728595 A JP 31728595A JP H09135167 A JPH09135167 A JP H09135167A
Authority
JP
Japan
Prior art keywords
frequency
output
controlled oscillator
voltage controlled
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7317285A
Other languages
Japanese (ja)
Other versions
JP3712141B2 (en
Inventor
Sadao Ishii
佐田夫 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Corp filed Critical Yaskawa Electric Corp
Priority to JP31728595A priority Critical patent/JP3712141B2/en
Publication of JPH09135167A publication Critical patent/JPH09135167A/en
Application granted granted Critical
Publication of JP3712141B2 publication Critical patent/JP3712141B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a phase locked loop circuit device tracking with a frequency less than a self-running oscillating frequency and having a wide frequency lock range by feeding back a difference signal of output signals of 1st and 2nd voltage controlled oscillators to a phase comparator. SOLUTION: The device is provided with a differential amplifier 10 receiving an output signal from a loop filter 3 and a prescribed voltage VREF and with a 2nd voltage controlled oscillator 11 receiving an output signal from the differential amplifier 10 and providing an output of a frequency f2 to a multiplier 5. When an input voltage V1 to the 1st voltage controlled oscillator 4 increases, its output frequency f1 increases and an output frequency f2 of the 2nd voltage controlled oscillator 11 decreases. A voltage outputted from the multiplier 5 has a high frequency including frequency components of f1 +f2 and f1 -f2 and a low pass filter 7 receiving the voltage eliminates the frequency component of f1 +f2 and the frequency component of f1 -f2 appears at an output terminal 9. Then a difference signal of output signals of the 1st and 2nd voltage controlled oscillator 11 is fed back to the phase comparator 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、直交位相変調され
た信号の受信回路等に使用される位相同期ループ装置
で、周波数引込み範囲を拡張した位相同期ループ装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop device used for a receiving circuit for a quadrature phase modulated signal and the like, and to a phase locked loop device having an expanded frequency pulling range.

【０００２】[0002]

【従来の技術】従来の位相同期ループ装置は図４に示す
ようになっている。図において１は入力端子、２は位相
比較器（ＰＣ）、３はループフィルタ、４は電圧制御発
振器（ＶＣ０）、９は出力端子である。入力端子１から
の信号と電圧制御発振動器４からの出力信号が位相比較
器２へ入力され、位相比較器２の出力はループフィルタ
３を介して電圧制御発振器４へ入力される。出力端子９
は電圧制御発振器４の出力端子である。2. Description of the Related Art A conventional phase locked loop device is shown in FIG. In the figure, 1 is an input terminal, 2 is a phase comparator (PC), 3 is a loop filter, 4 is a voltage controlled oscillator (VC0), and 9 is an output terminal. The signal from the input terminal 1 and the output signal from the voltage controlled oscillator 4 are input to the phase comparator 2, and the output of the phase comparator 2 is input to the voltage controlled oscillator 4 via the loop filter 3. Output terminal 9
Is an output terminal of the voltage controlled oscillator 4.

【０００３】次に位相同期ループ装置の動作を説明す
る。入力端子１に入力信号が無い場合、電圧制御発振器
（ＶＣＯ）４はある周波数で自走発振している。入力端
子１に信号が入力されると、位相比較器（ＰＣ）２で
は、入力端子１の入力信号周波数と電圧制御発振器（Ｖ
ＣＯ）４の信号周波数の周波数及び位相差に対応する信
号を発生する。この信号はループフィルタ３に入り高調
波成分が除去され、低周波成分だけが電圧制御発振器
（ＶＣＯ）４の発振周波数を変化させる。電圧制御発振
器（ＶＣＯ）４は、その周波数が周波数引込み範囲であ
れば、位相比較器（ＰＣ）２の出力直流成分が小さくな
るような周波数が発振するように働くため、その発振周
波数は次第に入力端子１に入力されている信号の周波数
と位相に同期する（第１の従来技術）。また別の従来の
位相同期ループ装置は図５に示すようになっている（例
えば特開平５−２９１９４８）。図において、入力端子
１、位相比較器（ＰＣ）２、ループ・フィルタ３、電圧
制御発振器（ＶＣＯ）４、乗算器５、固定発振器６、ロ
ーパスフィルタ（ＬＰＦ）７、レベル変換器８、出力端
子９で構成される。入力端子１は位相比較器（ＰＣ）２
の片方の信号入力と接続され、その出力はループ・フィ
ルタ３の入力と接続され、ループ・フィルタ３の出力は
電圧制御発振器（ＶＣＯ）４の入力と接続され、その出
力は乗算器５の片方の入力と接続される。又、固定発振
器６の出力は乗算器５のもう一方と接続され、乗算器５
の出力はローパスフィルタ７の入力と接続される。更に
ローパスフィルタ７の出力はレベル変換器８の入力と接
続され、その出力は出力端子９及び位相比較器（ＰＣ）
２の一方の入力と接続される。図５に示す構成の位相同
期ループ方式において、始めに入力端子１に信号が無い
場合、電圧制御発振器（ＶＣＯ）４はある周波数で自走
発振している。又、固定発振器６も常に一定周波数の発
振をしており、乗算器５ではこの二つの信号の乗算が行
われ、その二つの信号周波数の和の周波数成分と、差の
周波数成分が出力される。ローパスフィルタ７では、乗
算器出力の周波数成分の内、低い周波数成分である差の
周波数成分のみが通過し、レベル変換器８に入力され
る。 レベル変換器８では信号をクリップして一定振幅
の信号に変換する。本実施例では電圧制御発振器（ＶＣ
Ｏ）４の自走振周波数は２０ＭＨｚ、固定発振器６の発
振周波数は１５ＭＨｚとしてあり、その差の５ＭＨｚの
周波数信号が位相比較器２の片方の入力に加わってい
る。次に入力端子１に信号が入力された場合、位相比較
器（ＰＣ）２では入力端子１の入力信号周波数と、レベ
ル変換器８からの５ＭＨｚの信号の周波数及び位相差に
対応する信号を発生する。この信号は次のループフィル
タ３に入り高周波成分が除去され、低周波成分だけが電
圧制御発振器（ＶＣＯ）４の入力に入り、電圧制御発振
器（ＶＣＯ）４の発振周波数を変化させる。電圧制御発
振器（ＶＣＯ）４は、位相比較器（ＰＣ）２の出力の直
流成分が小さくなるような周波数を発振するように働く
ため、電圧制御発振器（ＶＣＯ）４の発振周波数は、電
圧制御発振器（ＶＣＯ）４の発振周波数−固定発振器６
の発振周波数＝入力端子１の信号周波数に近づいてい
き、最後に差の信号は入力端子１の信号に同期する。こ
の差の周波数信号が出力となる。Next, the operation of the phase locked loop device will be described. When there is no input signal at the input terminal 1, the voltage controlled oscillator (VCO) 4 is self-oscillating at a certain frequency. When a signal is input to the input terminal 1, in the phase comparator (PC) 2, the input signal frequency of the input terminal 1 and the voltage controlled oscillator (V
A signal corresponding to the frequency and phase difference of the signal frequency of (CO) 4 is generated. This signal enters the loop filter 3, the harmonic components are removed, and only the low frequency component changes the oscillation frequency of the voltage controlled oscillator (VCO) 4. The voltage controlled oscillator (VCO) 4 works so as to oscillate at a frequency such that the output DC component of the phase comparator (PC) 2 becomes small if the frequency is within the frequency pull-in range, so that the oscillating frequency is gradually input. It synchronizes with the frequency and phase of the signal input to the terminal 1 (first conventional technique). Another conventional phase locked loop device is shown in FIG. 5 (for example, Japanese Patent Laid-Open No. 5-291948). In the figure, input terminal 1, phase comparator (PC) 2, loop filter 3, voltage controlled oscillator (VCO) 4, multiplier 5, fixed oscillator 6, low-pass filter (LPF) 7, level converter 8, output terminal It is composed of 9. Input terminal 1 is a phase comparator (PC) 2
Of the multiplier 5 is connected to the output of the loop filter 3 and the output of the loop filter 3 is connected to the input of the voltage controlled oscillator (VCO) 4. Connected with the input of. The output of the fixed oscillator 6 is connected to the other side of the multiplier 5,
Is connected to the input of the low pass filter 7. Further, the output of the low-pass filter 7 is connected to the input of the level converter 8, and the output thereof is the output terminal 9 and the phase comparator (PC).
2 is connected to one input. In the phase locked loop system having the configuration shown in FIG. 5, when there is no signal at the input terminal 1 first, the voltage controlled oscillator (VCO) 4 oscillates at a certain frequency. Further, the fixed oscillator 6 also oscillates at a constant frequency at all times, and the multiplier 5 multiplies the two signals, and outputs the frequency component of the sum of the two signal frequencies and the frequency component of the difference. . In the low-pass filter 7, of the frequency components of the multiplier output, only the difference frequency component, which is a low frequency component, passes and is input to the level converter 8. The level converter 8 clips the signal and converts it into a signal having a constant amplitude. In this embodiment, the voltage controlled oscillator (VC
The free-running oscillation frequency of O) 4 is 20 MHz, the oscillation frequency of the fixed oscillator 6 is 15 MHz, and the frequency signal of 5 MHz, which is the difference, is applied to one input of the phase comparator 2. Next, when a signal is input to the input terminal 1, the phase comparator (PC) 2 generates a signal corresponding to the input signal frequency of the input terminal 1 and the frequency and phase difference of the 5 MHz signal from the level converter 8. To do. This signal enters the next loop filter 3, the high frequency component is removed, and only the low frequency component enters the input of the voltage controlled oscillator (VCO) 4 to change the oscillation frequency of the voltage controlled oscillator (VCO) 4. Since the voltage controlled oscillator (VCO) 4 oscillates at a frequency such that the DC component of the output of the phase comparator (PC) 2 becomes small, the oscillation frequency of the voltage controlled oscillator (VCO) 4 is Oscillation frequency of (VCO) -fixed oscillator 6
Oscillation frequency = the signal frequency of the input terminal 1, and finally the difference signal is synchronized with the signal of the input terminal 1. The frequency signal of this difference becomes the output.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、第１の
従来技術では周波数引込み範囲は電圧制御発振器（ＶＣ
Ｏ）４の性能に関係し、また、自走発振周波数以下の周
波数には追従できない問題があった。第２の従来技術で
は電圧制御発振器（ＶＣＯ）４の自走発振周波数以下の
周波数に追従できるが、周波数引込み範囲は第１の従来
技術と同様に狭かった。本発明は自走発振周波数以下の
周波数に追従し広い周波数引き込み範囲を持つ位相同期
ループ装置を提供することを目的とする。However, in the first prior art, the frequency pull-in range is the voltage controlled oscillator (VC).
There was a problem related to the performance of O) 4 and that it could not follow frequencies below the free-running oscillation frequency. In the second conventional technique, it is possible to follow a frequency equal to or lower than the free-running oscillation frequency of the voltage controlled oscillator (VCO) 4, but the frequency pull-in range is narrow as in the first conventional technique. An object of the present invention is to provide a phase locked loop device that follows a frequency below the free-running oscillation frequency and has a wide frequency pull-in range.

【０００５】[0005]

【課題を解決するための手段】上記問題を解決するため
に、本発明は、位相比較器とループフィルタと第１の電
圧制御発振器で構成され、前記位相比較器の入力信号と
前記第１の電圧制御発振器の出力を前記位相比較器で比
較し、前記位相比較器の出力信号を前記ループフィルタ
を通して前記第１の電圧制御発振器へ入力する位相同期
ループ装置において、前記ループフィルタからの出力信
号と一定電圧ＶREF とを入力する差動増幅器と、前記差
動増幅器からの出力信号を入力する第２の電圧制御発振
器と、前記第１の電圧制御発振器と前記第２の電圧制御
発振器の各々の出力信号の差信号を前記位相比較器へフ
ィードバックする手段を設けたものである。また、前記
フィードバックする手段は、前記差信号を分周器を通し
て前記位相比較器へフィードバックするようにしたもの
である。In order to solve the above-mentioned problems, the present invention comprises a phase comparator, a loop filter and a first voltage controlled oscillator, wherein an input signal of the phase comparator and the first voltage controlled oscillator are provided. In the phase locked loop device for comparing the output of the voltage controlled oscillator by the phase comparator and inputting the output signal of the phase comparator to the first voltage controlled oscillator through the loop filter, the output signal from the loop filter is Each of the differential amplifier which inputs the constant voltage V REF , the second voltage controlled oscillator which inputs the output signal from the differential amplifier, the first voltage controlled oscillator and the second voltage controlled oscillator. A means for feeding back the difference signal of the output signals to the phase comparator is provided. Further, the means for feeding back is adapted to feed back the difference signal to the phase comparator through a frequency divider.

【０００６】[0006]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。図１は本発明の位相同期ループ装
置の実施例を示すブロック図である。従来の技術ででて
きた名称と同じものには同一符号をつけ、重複説明を省
略する。従来の技術（図４）と比較して異なる部分は、
ループフィルタ３からの出力信号と一定電圧ＶREF を入
力する差動増幅器１０、差動増幅器１０からの出信号を
入力し、周波数ｆ2 を乗算器５へ出力する第２の電圧制
御発振器１１を備える点にある。入力端子１は位相比較
器２の片方の信号入力と接続され、その出力はループフ
ィルタ３の入力に接続される。ループフィルタ３の出力
は第１の電圧制御発振器の入力と接続され、その出力は
乗算器５の片方の入力と接続される。また、ループフィ
ルタ３の出力は差動増幅器１０の（−）端子にも接続さ
れ、その出力は第２の電圧制御発振器１１の入力と接続
され、その出力は乗算器５のもう一方の入力と接続され
る。差動増幅器１０の（＋）の出力端子は一定の電圧が
印加されている。さらに、乗算器５の出力はローパスフ
ィルタ７の入力に接続され、その出力はレベル変換器８
の入力と接続され、その出力は出力端子９及び位相比較
器（ＰＣ）２のもの一方の入力と接続される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a phase locked loop device of the present invention. The same names as those used in the conventional technique are designated by the same reference numerals, and duplicate description will be omitted. Differences from the conventional technology (Fig. 4) are:
A differential voltage amplifier 10 for inputting an output signal from the loop filter 3 and a constant voltage V REF, and a second voltage controlled oscillator 11 for inputting an output signal from the differential amplifier 10 and outputting a frequency f 2 to a multiplier 5 are provided. There is a point to prepare. The input terminal 1 is connected to one signal input of the phase comparator 2, and its output is connected to the input of the loop filter 3. The output of the loop filter 3 is connected to the input of the first voltage controlled oscillator, and its output is connected to one input of the multiplier 5. The output of the loop filter 3 is also connected to the (−) terminal of the differential amplifier 10, its output is connected to the input of the second voltage controlled oscillator 11, and its output is connected to the other input of the multiplier 5. Connected. A constant voltage is applied to the (+) output terminal of the differential amplifier 10. Further, the output of the multiplier 5 is connected to the input of the low pass filter 7, and its output is the level converter 8
, And its output is connected to the output terminal 9 and one input of the phase comparator (PC) 2.

【０００７】次に、図３は動作の説明図である。図１と
図３を基にして動作の説明をする。第１の電圧制御発振
器４の入力電圧をＶ1 、出力周波数をｆ1 、また第２の
電圧制御発振器１１の出力周波数をｆ2 、周波数引き込
み範囲をｆRNG とし、Ｖ1が０ＶからＶREF まで変化し
たときに出力端子９に現われる周波数の変化する幅とす
る。差動増幅器の片方に印加されている一定の電圧をＶ
REF とする。図２に示すとおり、Ｖ1 が増加すると、ｆ
1 は増加、ｆ2 は減少する。乗算器５の出力する電圧は
ｆ1 ＋ｆ2 、及び、ｆ1 −ｆ2 の周波数を含む高調波
で、ローパスフィルタ７でｆ1 ＋ｆ2 の周波数成分を取
り除けば、出力端子９にはｆ1 −ｆ2 の周波数成分が現
われる。この時のＶ1 とｆ1 −ｆ2 の関係は図３の破線
となる。図６は第２の従来の技術で示された方法での出
力端子９に現れる周波数引込み範囲を示す。Ｖ1 ＝０Ｖ
の時の出力端子９に現われる周波数は第２の従来技術と
等しいが、Ｖ1 ＝ＶREF の時の出力端子９に現われる周
波数は第２の従来技術の場合より大きく、周波数引込み
範囲が拡大する。上記手段によって、前記ループフィル
タの出力信号に対応して、第２の電圧制御発振器の出力
周波数が変化するため、自走発振周波数以下の周波数に
追従し、かつ、広い周波数引き込み範囲を持つようにな
る。Next, FIG. 3 is an explanatory diagram of the operation. The operation will be described with reference to FIGS. 1 and 3. V 1 the input voltage of the first voltage controlled oscillator 4, the output frequency f 1, also f 2 to the output frequency of the second voltage controlled oscillator 11, the frequency acquisition range and f RNG, until V REF V1 from 0V It is defined as a width in which the frequency appearing at the output terminal 9 changes when the frequency changes. The constant voltage applied to one side of the differential amplifier is V
REF . As shown in FIG. 2, when V 1 increases, f
1 increases and f 2 decreases. Output voltage of the multiplier 5 is f 1 + f 2, and, in harmonics including frequency of f 1 -f 2, if rid the frequency components of f 1 + f 2 a low-pass filter 7, the output terminal 9 f 1 A frequency component of -f 2 appears. The relationship between V 1 and f 1 -f 2 at this time is shown by the broken line in FIG. FIG. 6 shows the frequency pull-in range appearing at the output terminal 9 in the method shown in the second prior art. V 1 = 0V
The frequency appearing at the output terminal 9 when is equal to that in the second prior art, but the frequency appearing at the output terminal 9 when V 1 = V REF is larger than that in the second prior art, and the frequency pull-in range is expanded. . By the above means, the output frequency of the second voltage controlled oscillator changes in accordance with the output signal of the loop filter, so that it follows a frequency below the free-running oscillation frequency and has a wide frequency pull-in range. Become.

【０００８】[0008]

【発明の効果】以上述べたように、本発明によれば、前
記ループフィルタの出力信号に対応して、第２の電圧制
御発振器の出力周波数が変化し、自走発振周波数以下の
周波数に追従し、かつ、広い周波数引込み範囲を持つ位
相同期ループ装置が実現できるという効果がある。As described above, according to the present invention, the output frequency of the second voltage controlled oscillator changes in response to the output signal of the loop filter, and follows the frequency below the free-running oscillation frequency. In addition, there is an effect that a phase locked loop device having a wide frequency pull-in range can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明のブロック図FIG. 1 is a block diagram of the present invention.

【図２】 本発明のブロック図FIG. 2 is a block diagram of the present invention.

【図３】 本発明の特性図FIG. 3 is a characteristic diagram of the present invention.

【図４】 第１の従来技術のブロック図FIG. 4 is a block diagram of a first prior art.

【図５】 第２の従来技術のブロック図FIG. 5 is a block diagram of a second prior art.

【図６】 第２の従来技術の特性図FIG. 6 is a characteristic diagram of the second conventional technology.

【符号の説明】[Explanation of symbols]

１ 入力端子 ２ 位相比較器 ３ ループフィルタ ４ 第１の電圧制御発振器（ＶＣＯ） ５ 乗算器 ６ 固定発振器 ７ ローパスフィルタ（ＬＰＦ） ８ レベル変換器 ９ 出力端子 １０ 差動増幅器 １１ 第２の電圧制御発振器（ＶＣＯ） １２ 一定電圧（ＶREF ） １３ 分周器1 Input Terminal 2 Phase Comparator 3 Loop Filter 4 First Voltage Controlled Oscillator (VCO) 5 Multiplier 6 Fixed Oscillator 7 Low Pass Filter (LPF) 8 Level Converter 9 Output Terminal 10 Differential Amplifier 11 Second Voltage Controlled Oscillator (VCO) 12 constant voltage (V REF ) 13 frequency divider

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 位相比較器とループフィルタと第１の電
圧制御発振器で構成され、前記位相比較器の入力信号と
前記第１の電圧制御発振器の出力を前記位相比較器で比
較し、前記位相比較器の出力信号を前記ループフィルタ
を通して前記第１の電圧制御発振器へ入力する位相同期
ループ装置において、 前記ループフィルタからの出力信号と一定電圧ＶREF と
を入力する差動増幅器と、 前記差動増幅器からの出力信号を入力する第２の電圧制
御発振器と、 前記第１の電圧制御発振器と前記第２の電圧制御発振動
器の各々の出力信号の差信号を前記位相比較器へフィー
ドバックする手段と、を設けたことを特徴とする位相同
期ループ装置。1. A phase comparator, a loop filter, and a first voltage-controlled oscillator, wherein an input signal of the phase comparator and an output of the first voltage-controlled oscillator are compared by the phase comparator to obtain the phase. A phase locked loop device for inputting an output signal of a comparator to the first voltage controlled oscillator through the loop filter, a differential amplifier for inputting an output signal from the loop filter and a constant voltage V REF , A second voltage controlled oscillator for inputting an output signal from the amplifier; and means for feeding back the difference signal between the output signals of the first voltage controlled oscillator and the second voltage controlled oscillator to the phase comparator. And a phase-locked loop device. 【請求項２】 前記フィードバックする手段は、前記差
信号を分周器を通して前記位相比較器へフィードバック
するものである請求項１記載の位相同期ループ装置。2. The phase locked loop device according to claim 1, wherein the means for feeding back feeds the difference signal back to the phase comparator through a frequency divider.
JP31728595A 1995-11-10 1995-11-10 Phase-locked loop device Expired - Fee Related JP3712141B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31728595A JP3712141B2 (en) 1995-11-10 1995-11-10 Phase-locked loop device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31728595A JP3712141B2 (en) 1995-11-10 1995-11-10 Phase-locked loop device

Publications (2)

Publication Number Publication Date
JPH09135167A true JPH09135167A (en) 1997-05-20
JP3712141B2 JP3712141B2 (en) 2005-11-02

Family

ID=18086533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31728595A Expired - Fee Related JP3712141B2 (en) 1995-11-10 1995-11-10 Phase-locked loop device

Country Status (1)

Country Link
JP (1) JP3712141B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7054403B2 (en) * 2000-03-21 2006-05-30 Nippon Telegraph And Telephone Corporation Phase-Locked Loop
JP2016005191A (en) * 2014-06-18 2016-01-12 沖電気工業株式会社 Optical phase synchronization loop circuit
CN107395199A (en) * 2017-09-18 2017-11-24 江汉大学 A kind of phase-locked loop circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7054403B2 (en) * 2000-03-21 2006-05-30 Nippon Telegraph And Telephone Corporation Phase-Locked Loop
JP2016005191A (en) * 2014-06-18 2016-01-12 沖電気工業株式会社 Optical phase synchronization loop circuit
CN107395199A (en) * 2017-09-18 2017-11-24 江汉大学 A kind of phase-locked loop circuit
CN107395199B (en) * 2017-09-18 2023-11-24 江汉大学 Phase-locked loop circuit

Also Published As

Publication number Publication date
JP3712141B2 (en) 2005-11-02

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