JPH09130442A - Pi/4 shift qpsk demodulator - Google Patents

Pi/4 shift qpsk demodulator

Info

Publication number
JPH09130442A
JPH09130442A JP28583795A JP28583795A JPH09130442A JP H09130442 A JPH09130442 A JP H09130442A JP 28583795 A JP28583795 A JP 28583795A JP 28583795 A JP28583795 A JP 28583795A JP H09130442 A JPH09130442 A JP H09130442A
Authority
JP
Japan
Prior art keywords
differential
waveform
demodulator
output
shift qpsk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28583795A
Other languages
Japanese (ja)
Inventor
Takehiko Kobayashi
岳彦 小林
Makoto Onishi
誠 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP28583795A priority Critical patent/JPH09130442A/en
Publication of JPH09130442A publication Critical patent/JPH09130442A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a π/4 shift QPSK demodulator having the decoding system to obtain high transmission quality with a circuit compensating waveform distortion caused in a radio wave propagation path in a digital radio receiver adopting the π/4 shift QPSK demodulator. SOLUTION: An input signal is given to a synchronization detection circuit 44, its output is given to a waveform equalizer 42, in which waveform distortion is compensated. The compensated is given to a differential decoder 45, where differential decoding is executed and from which transmission data are outputted. Simultaneously the synchronization detection output is differential- processed by a differential processing unit 46 and the result is an input to a synchronization system circuit 43. Through the constitution above, the effect of waveform distortion caused in a radio wave propagation path is reduced and the decoding system excellent in the S/N characteristic is realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、π/4シフトQP
SK変調方式によるディジタル移動無線に用いる、ディ
ジタル復調方式に関する。
TECHNICAL FIELD The present invention relates to a π / 4 shift QP.
The present invention relates to a digital demodulation method used for digital mobile radio based on the SK modulation method.

【0002】[0002]

【従来の技術】はじめに、π/4シフトQPSK変調方
式について簡単に説明する。
2. Description of the Related Art First, a .pi. / 4 shift QPSK modulation system will be briefly described.

【0003】一般に、ディジタル変調方式においては、
送信しようとするビット列に対応して変調方式に固有の
信号点(シンボル)を設定し、この信号により搬送波を変
調する。π/4シフトQPSK変調方式では、送信ビッ
ト列を2ビットずつ区切り、各ビットパタン”00”
、”01”、 ”11”および ”10”に、それぞ
れ位相量(1/4)π、(3/4)π、(5/4)πお
よび(7/4)πを割り当て、この位相量を1時刻前の
シンボルの位相に加えて当該時刻のシンボルとして変調
を行う。すなわち連続する2シンボル間の位相差に対し
て送信データを割り当てる変調方式である。
Generally, in the digital modulation system,
A signal point (symbol) peculiar to the modulation method is set corresponding to the bit string to be transmitted, and the carrier wave is modulated by this signal. In the π / 4 shift QPSK modulation method, the transmission bit string is divided into two bits and each bit pattern is “00”.
, "01", "11" and "10" are assigned the phase amounts (1/4) π, (3/4) π, (5/4) π and (7/4) π respectively, and the phase amounts Is added to the phase of the symbol one time before, and modulation is performed as the symbol at that time. That is, this is a modulation method in which transmission data is assigned to the phase difference between two consecutive symbols.

【0004】ディジタル移動無線による高速データ伝送
においては、フェージングによる伝送波形の歪みが符号
間干渉を引き起こし、通信の重大な障害となる。フェー
ジングは、送信機からの伝送波が複数の電波伝搬路を経
て移動中の受信機に到達することにより生じる現象であ
り、波形等化はこの影響を軽減するための有力な対策技
術の一つである。実際の波形等化では、受信側が既知で
あるトレーニングシンボル系列を送信し、その受信信号
に対する等化出力とトレーニングシンボル系列の差が最
小になるような適応フィルタを構成し、伝送路の応答を
波形等化器内部で相殺することにより実現される。
In high-speed data transmission by digital mobile radio, distortion of transmission waveform due to fading causes intersymbol interference, which becomes a serious obstacle to communication. Fading is a phenomenon that occurs when a transmitted wave from a transmitter reaches a moving receiver via multiple radio wave propagation paths, and waveform equalization is one of the leading countermeasure techniques to reduce this effect. Is. In actual waveform equalization, the receiving side transmits a known training symbol sequence, and an adaptive filter that minimizes the difference between the equalization output and the training symbol sequence for the received signal is configured to form the waveform of the response of the transmission path. It is realized by canceling out inside the equalizer.

【0005】ここで、トレーニングシンボル系列とは、
予め定められた固定シンボル系列であり、受信側にも既
知となる。これは、送信データに基づいて作成される未
知のシンボル系列とともに送信される。トレーニングシ
ンボル系列生成器は、受信側においてこのトレーニング
シンボル系列を生成するものである。
Here, the training symbol sequence is
It is a predetermined fixed symbol sequence and is known to the receiving side. This is transmitted with an unknown symbol sequence created based on the transmitted data. The training symbol sequence generator is for generating this training symbol sequence on the receiving side.

【0006】波形等化の方式としては、LMS(Lea
st Mean Square)、RLS(Recu
rsive Least Square)、MLSE
(Maximum Likelihood Seque
nce Estimation)等がある。
As a waveform equalization method, LMS (Lea
st Mean Square), RLS (Recu
rsive Least Square), MLSE
(Maximum Likelihood Sequence
nce Estimation).

【0007】一方、ディジタル変調方式を大別すると、
振幅シフトキーイング(ASK)変調、周波数シフトキ
ーイング(FSK)変調、位相シフトキーイング(PS
K)変調等がある。この中のPSK変調の一種であるπ
/4シフトQPSK変調方式は、変調波の振幅が零とな
らないため、レベル変動範囲が限定されており、送信電
力増幅器の非線形による歪みに強いこと、変調において
本質的に差動符号化されるため、構成の簡単な遅延検波
によって容易に復調が行える等の点から、移動通信用の
変調方式として最適とされている。
On the other hand, when the digital modulation methods are roughly classified,
Amplitude shift keying (ASK) modulation, frequency shift keying (FSK) modulation, phase shift keying (PS
K) Modulation etc. Π, which is a type of PSK modulation among them
In the / 4 shift QPSK modulation method, the amplitude of the modulated wave does not become zero, so that the level fluctuation range is limited, it is resistant to the distortion due to the nonlinearity of the transmission power amplifier, and it is inherently differentially encoded in the modulation. Since it is possible to easily demodulate by differential detection with a simple configuration, it is optimal as a modulation system for mobile communication.

【0008】遅延検波器の一構成例を図6に示す。図中
31は帯域通過フィルタ、32,33は周波数混合器、
34は90°移相器、35,36は低域通過フィルタ、
37は遅延素子である。帯域通過フィルタ31を通過し
た受信信号は、遅延素子37によって遅延させた信号の
同相成分および直交成分とそれぞれ周波数混合器32お
よび33によって掛け合わせる。該直交成分は90°移
相器によって生成する。周波数混合器32および33の
出力は、低域通過フィルタ35、36により高周波成分
を除去し、それぞれ同相、直交検波出力を取り出す。
FIG. 6 shows an example of the configuration of the differential detector. In the figure, 31 is a bandpass filter, 32 and 33 are frequency mixers,
34 is a 90 ° phase shifter, 35 and 36 are low pass filters,
37 is a delay element. The received signal that has passed through the band pass filter 31 is multiplied by the in-phase component and the quadrature component of the signal delayed by the delay element 37 by the frequency mixers 32 and 33, respectively. The quadrature component is generated by a 90 ° phase shifter. From the outputs of the frequency mixers 32 and 33, high-frequency components are removed by low-pass filters 35 and 36, and in-phase and quadrature detection outputs are taken out, respectively.

【0009】ここで例えば、π/4シフトQPSK用の
ディジタル復調器として構成する場合、図7に示したよ
うな構成を採った場合を考える。この例は、検波器とし
て、前述の遅延検波器を用いた例である。図中41は図
6に示した遅延検波器、42は任意の方式をとる等化
器、43は同期系回路である。該同期系回路は、クロッ
ク信号、フレーム同期信号等を発生するものである。π
/4シフトQPSK変調の場合、1サンプル時刻前と当
該サンプル時刻のシンボル間に送信データが割り当てら
れているため、復号の際にはシンボル間の差動処理が不
可欠となる。この点、遅延検波は方式的に差動処理が含
まれているため、差動復号器を付加する必要がなく、回
路の簡易性の点で有利である。しかし、遅延検波の出力
は2シンボル間の信号演算の結果であるので、2シンボ
ルにわたる雑音の影響を受けてしまい、この信号を等化
することで等化出力もまた耐雑音の点で不利になる。さ
らに、本来の等化器は伝送波形の歪みの補償を目的とし
ているのに対して、一時刻前との差分波形に対して等化
を行うため、波形等化器内部の構成が複雑になり、処理
量の増大や補償精度の劣化が懸念される。
Now, let us consider a case where the digital demodulator for π / 4 shift QPSK is used, for example. In this example, the above-mentioned delay detector is used as the detector. In the figure, reference numeral 41 is the differential detector shown in FIG. 6, 42 is an equalizer adopting an arbitrary system, and 43 is a synchronous circuit. The synchronization system circuit generates a clock signal, a frame synchronization signal and the like. π
In the case of / 4 shift QPSK modulation, the transmission data is allocated between the symbols of one sample time before and the sample time, so that the differential processing between symbols is indispensable at the time of decoding. In this respect, since differential detection systematically includes differential processing, there is no need to add a differential decoder, which is advantageous in terms of circuit simplicity. However, since the output of the differential detection is the result of the signal operation between two symbols, it is affected by noise over two symbols, and equalization of this signal is also disadvantageous in terms of noise resistance. Become. Furthermore, while the original equalizer aims to compensate for distortion of the transmission waveform, it equalizes the difference waveform from one time before, which complicates the internal configuration of the waveform equalizer. However, there is concern about an increase in processing amount and deterioration of compensation accuracy.

【0010】[0010]

【発明が解決しようとする課題】本発明の目的は、π/
4シフトQPSK方式の復調器に波形等化器を適用する
場合に最適な受信機の構成方法を提供し、効果的にフェ
ージング等による電波伝搬路の歪みを補償し、品質の優
れたディジタル通信を実現することを目的とする。
DISCLOSURE OF THE INVENTION The object of the present invention is π /
We provide an optimal receiver configuration method when applying a waveform equalizer to a 4-shift QPSK demodulator, effectively compensating for distortion of the radio wave propagation path due to fading, etc., and achieving high-quality digital communication. Aim to achieve.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するた
め、本発明のπ/4シフトQPSK復調器は、少なくと
も、π/4シフトQPSKの入力受信信号を同期検波す
る同期検波器と、次段のフェージング補正用の等化器
と、次段のQPSK復合信号を得る差動復合を有する。
In order to achieve the above object, a π / 4 shift QPSK demodulator of the present invention includes at least a synchronous detector for synchronously detecting an input received signal of π / 4 shift QPSK, and a next stage. And an equalizer for fading correction and a differential decoding for obtaining a QPSK composite signal of the next stage.

【0012】この結果、本発明による復調方式によれ
ば、波形歪みの補償精度が高く、伝送品質の耐雑音特性
が向上する。
As a result, according to the demodulation method of the present invention, the waveform distortion compensation accuracy is high and the noise resistance characteristic of the transmission quality is improved.

【0013】[0013]

【発明の実施の形態】図1に本発明の基本的実施例のブ
ロック図を示す。
1 is a block diagram of a basic embodiment of the present invention.

【0014】図中、42は波形等化器、43は同期系回
路、44は同期検波器、45は差動復号器、46は差動
処理器である。入力信号は、同期検波器44を通り、等
化器42で波形歪みが補償される。この信号を差動復合
器45で差動復号して送信データが出力される。同時
に、同期検波出力は差動処理器46で差動処理され、同
期系回路43の入力となる。
In the figure, 42 is a waveform equalizer, 43 is a synchronous system circuit, 44 is a synchronous detector, 45 is a differential decoder, and 46 is a differential processor. The input signal passes through the synchronous detector 44, and the equalizer 42 compensates the waveform distortion. This signal is differentially decoded by the differential decoder 45 and the transmission data is output. At the same time, the synchronous detection output is differentially processed by the differential processor 46 and becomes the input of the synchronous circuit 43.

【0015】ここで、同期検波器44について説明す
る。
Now, the synchronous detector 44 will be described.

【0016】図5は、同期検波器の一構成例を示すブロ
ック図である。図中38は搬送波再生器である。31〜
36の構成要素は先に説明した図6と同じものであり、
機能も同じである。この同期検波方式では、遅延検波方
式における遅延信号の代わりに、搬送波再生器38が生
成する基準搬送波信号を用いる。
FIG. 5 is a block diagram showing an example of the structure of the synchronous detector. In the figure, numeral 38 is a carrier regenerator. 31-
The components of 36 are the same as those of FIG. 6 described above,
The function is also the same. In this synchronous detection system, a reference carrier signal generated by the carrier regenerator 38 is used instead of the delay signal in the differential detection system.

【0017】遅延検波方式と同期検波方式の二検波方式
を比較すると、耐雑音特性は同期検波方式の方が優れ、
回路の簡易さの点では遅延検波方式が有利であるといえ
る。
Comparing the two detection methods of the differential detection method and the synchronous detection method, the synchronous detection method is superior in the noise resistance characteristic.
It can be said that the differential detection method is advantageous in terms of circuit simplicity.

【0018】以下、本発明を適用した実施例を説明す
る。
An embodiment to which the present invention is applied will be described below.

【0019】図2に示す第1の実施例は、等化出力のシ
ンボル判定を行い、そのシンボルから差動復号により送
信データを決定するものである。
In the first embodiment shown in FIG. 2, the symbol determination of the equalized output is performed, and the transmission data is determined from the symbol by differential decoding.

【0020】同図中、44は上記の同期検波器、15は
波形等化器、12はトレーニングシンボル系列生成器、
ここで、トレーニングシンボル系列とは、予め定められ
た固定シンボル系列であり、受信側にも既知となる。こ
れは、送信データに基づいて作成される未知のシンボル
系列とともに送信される。トレーニングシンボル系列生
成器12は、受信側においてこのトレーニングシンボル
系列を生成するものである。
In the figure, 44 is the above synchronous detector, 15 is a waveform equalizer, 12 is a training symbol sequence generator,
Here, the training symbol sequence is a predetermined fixed symbol sequence, which is also known to the receiving side. This is transmitted with an unknown symbol sequence created based on the transmitted data. The training symbol sequence generator 12 generates this training symbol sequence on the receiving side.

【0021】13は差動処理器、14は同期回路、16
は判定器、17は差動復号器である。同期検波器11の
出力はトレーニングシンボル系列生成器12の出力を参
照信号とする等化器15により、歪みが補償される。同
期検波に使用される基準搬送波は、同期検波器11の出
力を13で差動処理して得られた信号から同期回路14
によって作られる。等化器15の出力は、判定器16に
よって4値の判定が行われ、この出力から差動復号器1
7で送信データが決定される。なお、判定器17の判定
境界はシンボル番号の偶奇によって、45°の位相差を
有する二つの判定面を交互に用いる。
13 is a differential processor, 14 is a synchronizing circuit, 16
Is a determiner, and 17 is a differential decoder. The distortion of the output of the synchronous detector 11 is compensated by the equalizer 15 using the output of the training symbol sequence generator 12 as a reference signal. The reference carrier wave used for the synchronous detection is a signal obtained by differentially processing the output of the synchronous detector 11 by the synchronous circuit 14
Made by. The output of the equalizer 15 is four-valued determined by the determiner 16, and the differential decoder 1
The transmission data is determined at 7. It should be noted that the decision boundary of the decision device 17 alternately uses two decision surfaces having a phase difference of 45 ° depending on whether the symbol number is odd or even.

【0022】図3に示す第2の実施例は、等化出力を差
動処理した後に判定を行い、直接送信データを決定する
ものである。
In the second embodiment shown in FIG. 3, the equalized output is differentially processed and then a determination is made to directly determine the transmission data.

【0023】同図中、18は差動処理器、19は判定器
である。11から15の構成要素は図2と同じものであ
り、機能も同じである。等化出力は差動処理器18によ
って一時刻前のシンボルとの差に変換される。この出力
を判定器19によって4値の判定を行い、送信データが
決定される。この場合は図1の判定器16とは異なり、
判定面は一つでよいという特長を持つ。
In the figure, 18 is a differential processor, and 19 is a judging device. The components 11 to 15 are the same as those in FIG. 2 and have the same functions. The equalized output is converted by the differential processor 18 into a difference from the symbol one time before. This output is judged by the judging device 19 into four values, and the transmission data is decided. In this case, unlike the determiner 16 of FIG. 1,
It has the feature that only one judgment surface is required.

【0024】図4に示す第3の実施例は、本発明を任意
の系列推定器を含む構成に適用した例である。
The third embodiment shown in FIG. 4 is an example in which the present invention is applied to a configuration including an arbitrary sequence estimator.

【0025】同図中、20は系列推定器であり、11か
ら14および17の構成要素は図1と同じものであり、
機能も同じである。系列推定器20では送信シンボルを
受信信号から推定して出力する。差動復号器17でこの
推定シンボルを差動復号して送信データを出力する。
In the figure, reference numeral 20 is a sequence estimator, and components 11 to 14 and 17 are the same as those in FIG.
The function is also the same. The sequence estimator 20 estimates a transmission symbol from the received signal and outputs it. A differential decoder 17 differentially decodes this estimated symbol and outputs transmission data.

【0026】[0026]

【発明の効果】本発明による復調方式によれば、波形歪
みの補償精度が高く、伝送品質の耐雑音特性が向上す
る。遅延検波方式を含む復調方式と比較して、検波器と
差動復号器が個別に必要であり、同期系回路のためにさ
らに差動処理器が必要となるが、遅延検波方式でも実際
の回路構成の場合は、局部搬送波発生回路にAFC等を
用いるため、回路規模には大差がない。また、現在のL
SI技術によれば容易に構成が可能である。
According to the demodulation method of the present invention, the accuracy of waveform distortion compensation is high and the noise resistance of transmission quality is improved. Compared to the demodulation method that includes the differential detection method, a separate detector and differential decoder are required, and a differential processor is required for the synchronous system circuit. In the case of the configuration, since the AFC or the like is used for the local carrier wave generation circuit, there is no great difference in circuit scale. Also, the current L
According to the SI technology, the configuration can be easily done.

【0027】本発明によれば、π/4シフトQPSK変
調方式を用いるディジタル無線装置において、QPSK
変調方式と同様の方式を持つ波形等化器を用いることに
より、効果的にフェージング等による電波伝搬路の歪み
を補償し、品質の優れたディジタル通信を実現できる。
According to the present invention, in a digital radio apparatus using the π / 4 shift QPSK modulation system, QPSK
By using a waveform equalizer having the same method as the modulation method, it is possible to effectively compensate for the distortion of the radio wave propagation path due to fading or the like, and realize high-quality digital communication.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の基本的実施例を示すのπ/4シフトQ
PSK用のディジタル復調器の構成ブロック図。
FIG. 1 is a π / 4 shift Q showing a basic embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of a digital demodulator for PSK.

【図2】本発明の第1の実施例を示すπ/4シフトQP
SK用のディジタル復調器のブロック図。
FIG. 2 is a π / 4 shift QP showing a first embodiment of the present invention.
The block diagram of the digital demodulator for SK.

【図3】本発明の第2の実施例を示すπ/4シフトQP
SK用のディジタル復調器のブロック図。
FIG. 3 is a π / 4 shift QP showing a second embodiment of the present invention.
The block diagram of the digital demodulator for SK.

【図4】本発明の第3の実施例を示すπ/4シフトQP
SK用のディジタル復調器のブロック図。
FIG. 4 is a π / 4 shift QP showing a third embodiment of the present invention.
The block diagram of the digital demodulator for SK.

【図5】周知の同期検波方式のブロック図。FIG. 5 is a block diagram of a known synchronous detection system.

【図6】周知の遅延検波方式のブロック図。FIG. 6 is a block diagram of a known differential detection system.

【図7】遅延検波方式を用いたπ/4シフトQPSK用
のディジタル復調器ブロック図。
FIG. 7 is a block diagram of a digital demodulator for π / 4 shift QPSK using a differential detection method.

【符号の説明】[Explanation of symbols]

11 同期検波器、12 トレーニングシンボル系列生
成器、13 差動処理器、14 同期回路、15 波形
等化器、16 判定器、17 差動復号器、18差動処
理器、19 判定器、20 シンボル系列推定器、31
帯域通過フィルタ、32,33 周波数混合器、34
90°移相器、35,36 低域通過フィルタ、37
遅延素子、38 搬送波再生回路、41 遅延検波
器、42波形等化器、43 同期系回路、44 同期検
波器、45 差動復号器、46差動処理器
11 synchronous detector, 12 training symbol sequence generator, 13 differential processor, 14 synchronous circuit, 15 waveform equalizer, 16 decision device, 17 differential decoder, 18 differential processor, 19 decision device, 20 symbols Sequence estimator, 31
Band pass filter, 32, 33 frequency mixer, 34
90 ° phase shifter, 35, 36 low pass filter, 37
Delay element, 38 carrier recovery circuit, 41 delay detector, 42 waveform equalizer, 43 synchronization system circuit, 44 synchronization detector, 45 differential decoder, 46 differential processor

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】π/4シフトQPSK変調方式によるディ
ジタル無線伝送に用いる受信機において、 少なくとも、同期検波後の受信信号の波形歪みを補償す
る波形等化器を有することを特徴とするπ/4シフトQ
PSK復調器。
1. A receiver used for digital radio transmission by a .pi. / 4 shift QPSK modulation system, having at least a waveform equalizer for compensating for waveform distortion of a received signal after synchronous detection. Shift Q
PSK demodulator.
【請求項2】請求項1項記載の復調器において、前記同
期検波後の出力を波形等化し、該波形等化信号をシンボ
ル判定して差動復号することにより送信データを復号す
ることを特徴とする復調器。
2. The demodulator according to claim 1, wherein the output after the synchronous detection is waveform-equalized, and the transmission equalized signal is symbol-judged and differentially decoded to decode the transmission data. And a demodulator.
【請求項3】請求項1項記載の復調器において、前記波
形等化器出力を差動処理し、この信号をシンボル判定す
ることにより送信データを復号することを特徴とする復
調器。
3. The demodulator according to claim 1, wherein the output of the waveform equalizer is differentially processed, and the transmission data is decoded by performing symbol determination on this signal.
【請求項4】請求項2項記載の復調器において、前記同
期検波出力の波形歪みを補償して送信シンボルを推定す
るシンボル系列推定器を用い、推定されたシンボル系列
から差動復号により送信データを復号することを特徴と
する復調器。
4. The demodulator according to claim 2, wherein a symbol sequence estimator for compensating the waveform distortion of the synchronous detection output to estimate a transmission symbol is used, and transmission data is differentially decoded from the estimated symbol sequence. A demodulator which is characterized by decoding.
JP28583795A 1995-11-02 1995-11-02 Pi/4 shift qpsk demodulator Pending JPH09130442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28583795A JPH09130442A (en) 1995-11-02 1995-11-02 Pi/4 shift qpsk demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28583795A JPH09130442A (en) 1995-11-02 1995-11-02 Pi/4 shift qpsk demodulator

Publications (1)

Publication Number Publication Date
JPH09130442A true JPH09130442A (en) 1997-05-16

Family

ID=17696730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28583795A Pending JPH09130442A (en) 1995-11-02 1995-11-02 Pi/4 shift qpsk demodulator

Country Status (1)

Country Link
JP (1) JPH09130442A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7315587B2 (en) 2002-12-26 2008-01-01 Hitachi Kokusai Electric Inc. Demodulation method and apparatus based on differential detection system for π/4 shifted QPSK modulated wave

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7315587B2 (en) 2002-12-26 2008-01-01 Hitachi Kokusai Electric Inc. Demodulation method and apparatus based on differential detection system for π/4 shifted QPSK modulated wave

Similar Documents

Publication Publication Date Title
KR970007362B1 (en) Equalizing device in receiver
JP2715662B2 (en) Method and apparatus for diversity reception of time division signals
US7187736B2 (en) Reducing interference in a GSM communication system
JP2591343B2 (en) Soft decision decoding method by channel equalization
CA2076084C (en) Adaptive mlse-va receiver for digital cellular radio
CA2076123C (en) Decision feedback equalization for digital cellular radio
US6205170B1 (en) Transmission/reception unit with bidirectional equalization
CA2076099A1 (en) Automatic simulcast alignment
US7158770B2 (en) Channel estimation method for a mobile communication system
US7526022B2 (en) Low complexity equalizer
JP4389934B2 (en) Clock recovery circuit
KR100626103B1 (en) Receiver for a digital transmission system
US7991047B2 (en) Method for designing a digital reception filter and corresponding receiving device
Raphaeli A reduced complexity equalizer for OQPSK
JPH09130442A (en) Pi/4 shift qpsk demodulator
JPH0435546A (en) Interference wave eliminating system
CA2202683A1 (en) Adaptive equaliser
KR100958508B1 (en) Interactive frequency correction using training sequence and data bits
JP4438914B2 (en) Radio communication wave demodulator
JP2000349694A (en) Equalization processing device and method
JPH1051363A (en) Viterbi equalizer
JPH08242196A (en) Diversity equalizer
Haas Performance improvement of a discriminator receiver through the implementation of a nonlinear decision
GB2224184A (en) Digital data demodulation
JPH07162348A (en) Automatic equalizer