JPH09130324A - Digital radio communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To discriminate the order, in which signals are branched on the trans mission side, at a high speed on the reception side by transposing signals after bit separation in a prescribed order and performing parallel/serial conversion. SOLUTION: A control circuit 25 takes the error detection pulse of a CRC decoder as the input, and reception of a system 1 of a demultiplexing circuit on the transmission side is discriminated when an error correction pulse is not detected in the case of channel type (CI) bit inversion, but reception of a system 2 is discriminated when the error detection pulse is not detected in the case of no bit inversion. A bit separation circuit 13' separates the CI bit and an attendant control channel bit SA to output 32kb/s data bits after CRC error detection. A switching circuit 26 switches and outputs reception data of transmission/reception equipments 11 and 11' so that the order of input of a demultiplexing circuit 14 coincides with the order of 32kb/s data signals of transmission systems 1 and 2, and they are restored to 64kb/s data in the order, in which they are outputted after parallel/serial conversion on the transmission side, by the demultiplexing circuit 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio access system for connecting a radio base station and a plurality of mobile terminals by dividing a radio line of the same frequency into a plurality of time slots, and more particularly to connecting a plurality of radio lines at the same time. A mobile data terminal having a transmission rate N times (N is an integer of 2 or more) the basic transmission rate assigned to the mobile terminal using a plurality of bursts between the radio base station and the mobile terminal. The present invention relates to a wireless communication device that enables wireless access.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional digital wireless communication apparatus for wirelessly accessing a data terminal N times the number of wirelessly transmitted data signals by simultaneously using a plurality of bursts. This configuration is a PHS (Personal Handyphone System) that performs time-division multiplexing of 4 time slots per radio frequency and allows mobile terminals to access the public line network.
1 shows an example of the wireless communication device. The configuration is such that two data transmission lines of 32 kb / s are used to access the data terminal 1 of 64 kb / s to the public network 2 using a wireless transmission line.

64 transmitted from the public network 2 to the data terminal 1
The kb / s data signal is input to the demultiplexing circuit 4 and 32 k
It is separated into b / s2 series. A bit addition circuit 5 adds a channel type bit (CI) and an associated control channel (SA) bit, and CRC-encodes the CRC encoder 6. A TDMA circuit 7 multiplexes a 32 kb / s3 sequence information data signal and a control slot by time division using 8 time slots for transmission and reception. Two 32 kb / s data signals of two sequences are assigned to two time slots and are sequentially assigned to slot number i and slot number j.

Reference numeral 8 is a base station transmitter / receiver,
10 'is an antenna, 11 and 11' are mobile station transceiver devices, and one mobile station radio device performs data transmission of 32 kb / s. The data output of the mobile station transmitter / receiver 11 is input to the CRC decoder 12 and error detection is performed, and the bit separation circuit 13 separates the channel type bit (CI) and the associated control channel (SA) bit added on the transmission side. Similarly, the data output of the mobile station transmitter / receiver 11 ′ is input to the CRC decoder 12 ′, error detection is performed, and the bit separation circuit 1
Channel type bit (C
I) and associated control channel (SA) bits are separated. The output data signals of the bit demultiplexing circuits 13 and 13 'are input to the demultiplexing circuit 14 and subjected to parallel-serial conversion in the order of slot number i and slot number j to 64 kb /
s data.

FIG. 6 shows a slot configuration for PHS communication, in which a transmission 4 time slot and a reception 4 time slot are configured in a 5 ms frame. 32k since 16 unique words and 160 information bits can be transmitted when 1 time slot is used as a communication slot
An information data signal of b / s can be transmitted. Therefore, if two time slots are used simultaneously, 64 kb / s
Data transmission. The data signal is supposed to be transmitted after being encoded by the cyclic code (CRC) on the transmitting side, and the channel type bit (C
I) 4 bits, 16 bits of ancillary control channel (SA) attached to a speech channel, and 180 bits of 160 bits of transmission data are CRC-coded as information bits to 16 bits.
Redundant bits are added and transmitted.

FIG. 7 is an explanatory view showing signal conversion of a conventional configuration, in which an input 64 kb / s data signal is serial-parallel converted into two series of 32 kb / s data signals and a channel type bit for classifying a communication channel. (CI) with control bit and CRC redundancy bit added to TDMA
It is input to the circuit and transmitted using 2 time slots.
FIG. 7 shows an example in which two time slots of time slot number 1 and time slot number 2 are sequentially assigned. 64k transmitted on the receiving side by parallel-to-serial conversion in the order in which two time slots were received and transmitted
Return to b / s data signal.

[0007]

The TDMA system is a system in which a plurality of mobile stations access the same wireless device in a time division manner. In general, the allocation to each slot cannot be controlled by the network side and the terminal side, and it is difficult for the receiving side to detect which time slot the transmitting side has transmitted when performing parallel-to-serial conversion, so communication is started. In order to do so, it is necessary to transmit the training signal to the transmission data in advance and detect the order of the parallel line data signal on the receiving side. In FIG. 7, it is not possible for the mobile terminal side to know whether the transceiver 11 and the transceiver 11 ′ are receiving the slot 1 and the slot 2, and therefore a training signal is transmitted when the line is connected and the transceiver 11 and the transceiver 11 ′ are received. There is a need for a sequence for determining which of the data is branched first in the serial-to-parallel conversion on the transmission side and switching the input of the demultiplexing circuit 14 to input the data to restore the data signal on the transmission side after the parallel-serial conversion.

Further, since the radio frequency is arranged so as not to be affected by interference from other radio base stations and mobile stations, if the frequency and time slot once assigned are also interfered with by other radio stations. Since the order of time slots may be changed due to channel switching, the training signal must be transmitted during communication, and data transmission is interrupted during this period.

An object of the present invention is, in a wireless transmission system in which an input data signal is branched into N and transmitted via an N line, the order in which a reception signal is branched at a transmitting side using CRC error detection and correction without transmitting a training signal. It is an object of the present invention to provide a digital wireless communication device which can make a high-speed determination with no interruption of data transmission during communication.

[0010]

According to the present invention, any one of channel type bits (CI) added in a wireless transmission system in which an input data signal is serial-parallel converted, branched into N and transmitted through an N line. Inverts the bits, CRC-encodes them with the data bits, adds redundant bits, restores the channel type bits to normal bits, and sends
A digital wireless communication device without disconnection of transmission data is provided because the reception side can judge at high speed the order of branching after serial-parallel conversion on the transmission side using RC error detection and the transmission data signal is used during communication. To do.

On the transmitting side, a 1: N serial-parallel conversion circuit for branching an input signal into an N line of a transmission rate signal of 1 / N, and a channel type (CI) bit added to an N-branch output to add a channel type (CI). CI) means for inverting any of the bits that can be changed by the N-branch output, and CR
A means for restoring the inverted channel type (CI) bit after the C coding and an arbitrary channel type (C
I) Means for inverting the bit and CRC error detection of the signal after the inversion, and if an error occurs, change the channel type (CI) inversion bit and which number line the receiving line branches on the transmitting side. After determining, the input of the multiple conversion input signal is arranged in order, the serial-to-serial conversion is performed, and the signal on the transmission side is reproduced.

In the wireless communication apparatus of the present invention, the channel type (CI) bit added to the signal branched to the N line is inverted and CRC-coded by inverting the bit which is different in the N line and based on the inverted bit in the wireless section. It is returned and transmitted, and the receiving side detects the inverted bit from the CRC error detection to determine the serial parallel N-branch output number on the transmitting side, arranges in the order of input and inputs to the multiple branch circuit, and determines the line order for parallel-serial conversion. Therefore, it is not necessary to transmit a training signal to the transmission data, so that the transmission speed is high and the transmission data can be detected while being transmitted even when the channel is switched, so that the data transmission is not interrupted.

[0013]

FIG. 1 shows a first embodiment of the present invention. This configuration shows an example of a PHS (Personal Handy Phone System) wireless communication device that performs time division multiplexing of four time slots per one radio frequency to access a mobile terminal to a public line network. The configuration is such that two data transmission lines of 32 kb / s are used to access the data terminal 1 of 64 kb / s to the public network 2 using a wireless transmission line.

64 is transmitted from the public network 2 to the data terminal 1.
The kb / s data signal is input to the demultiplexing circuit 4 and 32 k
The b / s data signal is serial-parallel converted into two series. One of the branched outputs is added with a channel type (CI) bit by the bit addition circuit 5, the bit inversion circuit 21 inverts only one bit of the channel type (CI) bit, for example, the leading bit, and CRC encoding is performed by the CRC encoder 6. After that, the bit inversion circuit 22 restores the channel type (CI) bit inverted in the inversion circuit 21 to the original code. Similarly, the channel output (CI) bit is added to the other of the branched outputs by the bit addition circuit 5 ′ and CRC encoded by the CRC encoder 6 ′, as in the conventional device.

Numeral 7 is a TDMA circuit, which is a two-system 32 kb
The / s data signal is assigned to the time slots of slot number i and slot number j, is input to the base station transmitting / receiving circuit 8 as a modulated data signal, and is transmitted as a radio signal from the antenna 9.

Reference numerals 10 and 10 'are mobile station antennas, 11 and 11' are mobile station transceivers, and one mobile station transceiver transmits data at 32 kb / s. The data output of the mobile station transmitter / receiver 11 is the channel type (CI).
The bit inverting circuit 23 inputs the bit inverting circuit 23 to the transmitting side
Invert the same bit that was inverted with, and switch 2
4 is input. The switch 24 uses the channel type (C
I) The output of the bit inversion circuit 23 and the signal before inversion are selectively switched and input to the CRC encoder 12 to detect an error. When the control circuit 25 receives the error detection pulse of the CRC decoder and inverts the channel type (CI) bit and receives the error correction pulse without detecting the error correction pulse, the control circuit 25 transmits the 1-system (slot) of the demultiplexing circuit on the transmission side. i) is received, and if the error detection pulse is not detected without bit inversion, it is determined that the second system (slot j) is received. The bit separation circuit 13 detects the channel type (C
I) bit and associated control channel bit SA are separated and a 32 kb / s data bit is output.

The data output of the mobile station transmitter / receiver 11 'is input to the channel type (CI) bit inversion circuit 23', and the same bit as the bit inverted by the bit inverter 21 on the transmission side is inverted, and the switch 24 '. Entered in. The switch 24 ′ is a channel type (CI) bit inverting circuit 2
The output of 3'and the signal before inversion are selectively switched and input to the CRC encoder 12 'to detect an error. Control circuit 25 is CRC
The error detection pulse of the decoder is input and the channel type (C
I) When bit-inverted and error-correction pulse is not detected and can be received, it is judged that the 1st system (slot i) of the demultiplexing circuit on the transmission side is received, and error detection is performed without bit-inverted. If no pulse is detected, it is determined that the second system (slot j) is being received. Bit separation circuit 13 '
Outputs a 32 kb / s data bit by separating the channel type (CI) bit and the associated control channel bit SA after detecting the CRC error.

The switching circuit 26 receives the reception data of the transmission / reception device 11 and the reception of the transmission / reception device 11 'so that the input order of the demultiplexing circuit 14 is the transmission 1-system 32 kb / s and the transmission 2-system 32 kb / s data signals. The data can be switched and output, and the demultiplexing circuit 14 can restore the data of 64 kb / s in the order of parallel-serial conversion on the transmission side and output.

FIG. 2 is an explanatory view showing the signal conversion of the present invention. At the transmitting side, an input 64 kb / s data signal is converted from serial to parallel into two series of 32 kb / s data signals, one of which is 32 kb / s. A channel type bit (CI) and a CRC redundant bit for classifying a call channel are added to the data signal, and a channel type bit (CI) and C for classifying the call channel are added to the other 32 kb / s data signal.
A CRC redundant bit obtained by inverting the I bit and CRC encoding is added to the TDMA circuit and transmitted using two time slots. FIG. 2 shows an example in which two time slots of time slot number 2 and time slot number 3 are sequentially assigned. The channel type CI of 2 slots is a bit indicating a communication channel (TCH), and is the same as the conventional configuration. The receiving side judges whether the transmission path is 1-system or 2-system depending on whether it receives 2 time slots, inverts the channel type (CI), and detects a CRC error, and performs parallel-serial conversion in order to transmit 64 kb.
/ S Return to data signal.

FIG. 3 shows in detail the slot determination method of the present invention. 32 kb converted from serial to parallel on the transmitting side
/ S data signal 160 bits is added with a channel type (CI) bit indicating TCH, and then the data signal 160 bits is CRC-coded including the channel type (CI) and associated control channel and 16 bits of redundant bits are added. Input to TDMA. At the time of this CRC encoding, the channel type (CI) bit is inverted and encoded, and is restored to the original channel type (CI) bit on the transmission path. FIG.
Shows the case where the leading bit of the channel type (CI) is inverted.

On the receiving side, it is possible to determine from the channel type (CI) display that the channel is a communication channel as in the conventional case, and the leading bit of the channel type (CI) is determined by whether or not the channel type (CI) bit is inverted when an error is detected. An error correction pulse can be detected at the position. In the other 32 kb / s data transmission line, as in the conventional configuration, the channel type (CI) bit is not CRC-inverted at the time of transmission but is CRC-encoded and received, so that the error correction is performed in the state that the channel type (CI) bit is not inverted. Since no pulse is output, it is possible to determine which of the 32 kb / s received data of two lines is to be used for parallel / serial conversion.

FIG. 4 shows a second embodiment of the present invention, in which the transmitting side assigns a plurality of sequences of multiple branch outputs to a channel type (CI).
The control circuit 25 uses the fact that the bit position where different bits are inverted is CRC-encoded and transmitted, and the receiving side detects the error correction pulse of the result of CRC decoding at the inverted bit position on the transmitting side. Different from the first embodiment, it is possible to distinguish a plurality of streams by detecting the order of the stream branched from the signal on the transmitting side. When 1-bit error correction is adopted as the CRC code, the 1-bit error bit position can be detected, so the 4-bit channel type (C
When I) bits are adopted, it is possible to distinguish up to four series of data transmission paths.

[0023]

As described above, according to the present invention, since the transmission data rate is higher than the transmission rate of the wireless line, the transmission data rate is converted from serial to parallel and the data is transferred using the N line. Side reverses the channel type (CI) bit and then CRC-encodes and transmits, CRC error detection and transmission on the receiving side, and the inverted bit on the transmitting side is transmitted by the error detection pulse to the i-th demultiplexing circuit on the transmitting side. It is an apparatus for reproducing the input data signal by performing high speed parallel-serial conversion on the receiving side to determine that it is the second.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a signal conversion operation of the present invention.

FIG. 3 is a diagram illustrating a signal detection operation of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing a conventional configuration.

FIG. 6 is a diagram illustrating a TDMA communication slot.

FIG. 7 is a diagram illustrating a signal conversion operation of a conventional configuration.

[Explanation of symbols]

 1 data terminal 2 public network 4 multiple branching circuit 5, 5'bit addition circuit 6, 6 'CRC encoder 7 TDMA circuit 8 base station transceiver device 9, 10, 10' antenna 11, 11 'mobile station transceiver device 12, 12 'CRC decoder 13 bit separation circuit 14 multiple branch circuit 21,21', 22, 22 'bit inversion circuit 24 switch 25 control circuit 26 switching circuit

Claims (2)

[Claims] 1. A wireless communication system for wirelessly connecting a wireless base station and a plurality of mobile terminals, wherein a plurality of wireless circuits are provided between the mobile data terminal and the wireless base station according to the data transmission rate of the mobile terminal. In the wireless access method in which the wireless base station (CS) installed in the micro cell and the wireless base station can communicate with each other in the wireless access method in which the data transmission speed of the wireless line is multiple times by simultaneously allocating A mobile station (PS) within the wireless base station, and the wireless base station transmits the downlink transmission data signal transmitted from the network to the mobile station to a plurality of transmission data rates by serial-to-parallel conversion and transmits to a plurality of wireless lines. A demultiplexing circuit that parallel-serial converts a plurality of upstream transmission data signals separated and transmitted by the mobile station to interface with the signal speed of the network, The Shin side channel type to transmit the data signal demultiplexing circuit outputs a plurality of sequences that serial-parallel conversion (CI)
And a bit addition circuit for adding a plurality of channel types (C
I) A bit inversion circuit that inverts a predetermined bit determined by a wireless line among a plurality of wireless line transmission data signals differently, and an error correction that encodes a transmission data signal and a channel type (CI) bit as information bits A bit inversion circuit that inverts the channel type (CI) bit that is inverted with the encoder and returns it to the original state, a TDMA circuit that demultiplexes by time division as a wireless modulation signal, and a transmission data signal that is modulated and converted into a wireless signal and transmitted. And a transmission / reception circuit and an antenna for receiving a plurality of wireless lines on the receiving side, and a bit that inverts any bit of the channel type (CI) bits of the reception data signal of the plurality of wireless lines. Inversion circuit, switcher for selecting and outputting data signal with or without bit inversion, CRC error correction decoder, channel type A bit separation circuit for separating separate (CI) bits, a switch circuit for switching and outputting a plurality of series of input data signals, and a demultiplexing circuit for sequentially selecting a plurality of data signals and performing parallel-serial conversion to the data rate of the terminal. , A control circuit for controlling the selection of the switch circuit depending on the presence or absence of a CRC error correction pulse, and bit inversion for all combinations of bit inversion positions at which the channel type (CI) bits of the reception data of a plurality of lines are inverted at the transmission side. The above steps are repeated, and it is determined by the combination that the error detection pulse of the error correction decoder disappears, which of the multiple outputs of the transmission side demultiplexing circuit is, and the signal after bit separation is branched by the transmission side demultiplexing circuit. By rearranging in the order in which they are arranged and performing parallel-to-serial conversion by the demultiplexing circuit, the original data signal sequence is expanded. Digital radio communication system and converting. 2. A radio base station, wherein a downlink transmission data signal transmitted from a network to a mobile station is serial-parallel converted and separated into a plurality of transmission data rates and transmitted to a plurality of wireless lines.
A demultiplexing circuit that multiplexes the upstream transmission data signals that are separated and transmitted by the mobile station and interfaces with the signal speed of the network, and the transmission side outputs transmission data of multiple series that have been serial-parallel converted by the demultiplexing circuit. A bit addition circuit for adding a channel type (CI) to a signal, and a bit inverting circuit for inverting a predetermined bit of a plurality of channel type (CI) bits that is determined by a wireless line differently for a plurality of wireless line transmission data signals , An error correction encoder that encodes a transmission data signal and a channel type (CI) bit as information bits, a bit inverting circuit that inverts an inverted channel type (CI) bit to restore it, and time division as a radio modulation signal TDM circuit for demultiplexing with Tx, a transmission / reception circuit for modulating / demodulating a transmission data signal and converting it into a radio signal, and an antenna The receiving side includes an antenna for transmitting and receiving a plurality of wireless lines, a transmission / reception circuit, a CRC error correction decoder, a bit separation circuit for separating channel type (CI) bits, and a plurality of series of input data. A switch circuit that switches and outputs signals, a demultiplexer circuit that sequentially selects a plurality of data signals and performs parallel-to-serial conversion to the data rate of the terminal, and a channel type that is inverted from the error correction pulse of the error correction decoder on the transmission side ( And a control circuit for determining the CI) bit, and determines which of the multiple outputs of the transmission side demultiplexing circuit the channel type (CI) bit inverted on the transmission side is determined from the error correction pulse of the error correction decoder. Then, the signals after bit separation are rearranged in the order in which they were branched by the demultiplexing circuit on the transmission side, and parallel-serial conversion is performed by the demultiplexing circuit. Digital radio communication apparatus characterized by multiplexing into data signal sequence.