JPH09106267A - Liquid crystal display device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a high picture quality display capable of obtaing a sufficient contrast characteristic even when signal drivers whose output dynamic ranges are particularly small are used in a TFT liquid crystal display. SOLUTION: A counter electrode drive circuit 410 driving counter electrodes 425 being electrodes of one side of liquid crystal 427 of a pixel part is provided in this device and a voltage of not less than dynamic ranges of signal drivers is impressed on the liqiud crystal by constituting the counter electrode drive circuit 410 so as to fetch the high-order bit data of respective pixel display data and to select and outout either counter electrode voltage levels of plural levels according to the high-order bit data and by utilizing the potential difference between voltage levels to be outputted by the signal drivers and the counter electrode voltage level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and a driving method for a liquid crystal display that displays a high quality image.

[0002]

2. Description of the Related Art Conventional thin film transistors (Thin F)
As described in JP-A-63-237095, a liquid crystal display using an ilm Transistor (hereinafter referred to as a TFT) is used for displaying data on a TFT liquid crystal panel in which pixel portions made of TFTs and liquid crystals are arranged in a matrix. Display is performed by applying a corresponding gradation voltage.

A conventional TFT liquid crystal display is shown in FIG.
This will be described with reference to FIGS. In order to simplify the description, a case of monochrome 8 gradations will be described. FIG. 1 is a block diagram of a conventional liquid crystal display device, and 100 is a signal bus for transferring display data and display control signals supplied from a display control unit (not shown) such as a system, for example, a personal computer or a workstation. Is a liquid crystal controller, 102 is a signal bus for transferring display data and liquid crystal drive signals to be supplied to the pixel electrode drive circuit, 103 is a signal bus to be supplied to the scanning circuit, and 104 is a liquid crystal alternating signal (hereinafter referred to as M Signal), 105 is a pixel electrode drive circuit that supplies a drive voltage to the pixel electrode section selected by the scanning circuit, and 106 is a row-by-row selection among a plurality of pixel electrode sections formed in a matrix. A scanning circuit, 107 is a power supply circuit, and 108 is a TFT liquid crystal panel. In the present invention, the level of the M signal is assumed to switch every horizontal period.

In the pixel electrode drive circuit 105, 109
Is a memory circuit for sequentially fetching and storing display data transferred by the signal bus 102, 110 is a data bus for transferring the display data stored by the memory circuit 109, and 111 is simultaneously fetching and storing display data transferred by the data bus 110. Storage circuit, 112 is a data bus for transferring display data stored in the storage circuit 111, and 113 is a data bus 11
2 is a grayscale voltage generation circuit that receives the display data transferred and generates a grayscale voltage, and 114 is the pixel electrode drive circuit 10.
At the output terminal of 5, the drain voltage Vd which is the gradation voltage is set to T
It is a drain bus supplied to the FT liquid crystal panel.

In the scanning circuit 106, 115 is a shift register, 116 is a data bus for transferring the data output from the shift register, 117 is a level shifter for converting the voltage level of the data output by the shift register, 118
Is a gate bus for supplying an output terminal of the scanning circuit 106 and a gate voltage Vg for sequentially selecting pixels for one horizontal line.

In the output of the power supply circuit 107, reference numeral 119 is a power supply bus for supplying a power supply voltage to the scanning circuit 106, and 120.
Is a power supply bus for supplying a power supply voltage to the pixel electrode drive circuit 105, and 121 is a power supply bus for supplying a power supply voltage to the counter electrode of the TFT liquid crystal panel 108. TFT liquid crystal panel 10
8, the drain bus 114 and the gate bus 118 intersect in a matrix, and the intersection is TF which is a switching element.
T122 and the liquid crystal 123 form a pixel portion.

The gate electrode 118 of the TFT 122 is connected to the gate bus 118, and the drain electrode thereof is connected to the drain bus 114. The source electrode 124 of the TFT 122 is one electrode of the liquid crystal 123. The other electrode of the liquid crystal 123 is a counter electrode 125, which is connected to the power supply bus 121. The counter electrode 125 is used for the liquid crystal 12 of all pixel portions.
It is common to the three.

FIG. 2 shows a conventional gray scale voltage applying operation by focusing on one vertical column of a liquid crystal display, and shows how the display lines are switched over time. Vg1 is the gate voltage Vg indicated by the gate signal on the first line of the gate bus 118, and Vg2 is the gate bus 1
Gate voltage V indicated by the gate signal of the second line of 18
g and Vgon are selected voltage levels, and Vgoff is a non-selected voltage level. The dynamic range of the drain voltage Vd is Vdw, in which the drain voltage of the gradation level corresponding to the display data is output.

Vcom is a voltage waveform of the counter electrode 125,
VcomP is a positive voltage value applied to the counter electrode 125, VcomN is a negative voltage value applied to the counter electrode 125, and the counter electrode voltage Vcom is a voltage level serving as a reference for the voltage applied and held to the liquid crystal 123. Is. FIG.
FIG. 4 shows a voltage-luminance characteristic diagram of a TFT liquid crystal panel.

The operation will be described again with reference to the drawings. The liquid crystal controller 101 converts the display data and the display control signal transferred by the signal bus 100 into display data and a liquid crystal drive signal for driving the liquid crystal display device. Then, the display data and the liquid crystal drive signal supplied to the pixel electrode drive circuit 105 are transferred by the signal bus 102, the liquid crystal drive signal supplied to the scanning circuit 106 is transferred by the signal bus 103, and the signal supplied to the power supply circuit 107 is M. Transfer with signal 104. The pixel electrode drive circuit 105 sequentially captures and stores the display data transferred by the signal bus 102 in the storage circuit 109.

When the pixel electrode drive circuit 105 finishes capturing the liquid crystal display data for one horizontal line, it stores the liquid crystal display data in the storage circuit 111 in synchronization with the display control signal transferred by the signal bus 102. The gradation voltage generation circuit 113 generates a drain voltage Vd corresponding to the liquid crystal display data for one horizontal line, and outputs it to the drain bus 114. The pixel electrode drive circuit 105 generates a drain voltage,
The scanning circuit 106 sequentially applies the selection voltage to the gate bus 118 in synchronization with the output to the drain bus 114.

The scanning circuit 106 includes a shift register 115.
Of the TFT 12 in the liquid crystal panel 108 is generated by the level shifter 117 by inputting the display control signal transferred by the signal bus 103 to sequentially generate a pulse as a reference of the gate voltage.
2 is converted into a voltage (selection voltage level: Vgon, non-selection voltage level: Vgoff) that causes the selection state and the non-selection state, and is output to the gate bus 118. Therefore, the selection voltage Vgon of the gate bus 118 is sequentially applied for one horizontal period as shown in FIG. Then, by repeating this for one frame period, all the TFTs 122 are selected.

Further, as shown in FIG. 2, every time the scanning circuit 106 switches the selection line, the counter electrode voltage Vcom also switches between VcomP and VcomN (hereinafter, the counter electrode voltage is converted to AC).

Further, as can be seen from FIG. 3, when the counter electrode voltage Vcom is the positive level VcomP, a negative voltage, that is, a negative drain voltage with respect to the counter electrode voltage is applied to the liquid crystal 123 in the pixel portion. Maximum potential difference Vrm
s2- and the minimum potential difference Vrms1-. In addition, when the counter electrode voltage Vcom is a negative level VcomN, when
As shown in, the liquid crystal 123 in the pixel portion is applied with a positive voltage, that is, a positive drain voltage with respect to the counter electrode voltage, and the maximum potential difference Vrms2 + and the minimum potential difference Vrms1 +.
Becomes

Then, in order to obtain a desired brightness, the output is switched line by line so that the drain voltage Vd also obtains a desired potential difference with the counter electrode 125 in synchronization with the alternating voltage of the counter electrode ( That the drain voltage is alternating). For example, in order to obtain the maximum brightness, when the counter electrode voltage is VcomP of the positive polarity level, the drain voltage Vd
Is the minimum value, and the counter electrode voltage is Vcom at the negative level.
When N, the drain voltage Vd has the maximum value. As a result,
It becomes possible to alternately apply positive and negative voltages for each line. As a result, the positive and negative voltages are evenly distributed over the entire screen, and flicker does not occur.

[0016]

In the liquid crystal display device described in the prior art, the maximum luminance and the minimum luminance are obtained in the voltage luminance characteristic when the dynamic range of the drain voltage Vd output from the pixel electrode driving circuit 105 is Vdw. It is configured to be. It is expected that demands for the liquid crystal display device to be compatible with multimedia, such as moving image display and multicolor display, will increase in the future. If multi-color display, that is, an attempt to increase the number of gradations in each primary color, it is necessary to finely control the voltage in the voltage-luminance characteristic diagram shown in FIG. However, in order to make it resistant to voltage fluctuations and temperature changes, it is desirable to use a liquid crystal material having a smooth luminance gradient with respect to voltage changes. Further, in order to realize moving image display, it is necessary to use a high-speed response liquid crystal material, but the high-speed response liquid crystal material generally has a property that the inclination of luminance is smooth with respect to a change in voltage.

However, when using a liquid crystal material having a smooth luminance gradient with respect to a change in voltage, that is, a liquid crystal material having an applied voltage width larger than that of the conventional one, which can obtain the maximum luminance to the minimum luminance, the conventional pixel electrode driving circuit is used. Then, the maximum brightness or the minimum brightness cannot be obtained, and it becomes difficult to obtain a sufficient contrast. Therefore, it is necessary to increase the amplitude of the drain voltage Vd output from the pixel electrode drive circuit 105 in a liquid crystal material in which the change in brightness (slope) is smooth with respect to the change in voltage, and a circuit process that can generate the amplitude is used. There is a need. Therefore, configuring the pixel electrode drive circuit 105 having a wide dynamic range Vdw can be considered as one solution, but there is a problem that the manufacturing cost becomes high.

Therefore, it is an object of the present invention to provide a drive circuit for a liquid crystal display device which can obtain a sufficient contrast at a low cost. Further, a specific object of the present invention is to use a pixel electrode drive circuit having a narrow dynamic range Vdw of the drain voltage Vd without using the circuit process of the pixel electrode drive circuit for widening the dynamic range Vdw of the drain voltage Vd. It is an object of the present invention to provide a drive circuit of a liquid crystal display device which can obtain a sufficient contrast.

Another specific object of the present invention is to provide a drive circuit of a liquid crystal display device which can obtain a sufficient contrast even if a liquid crystal material having a smooth luminance gradient with respect to a voltage change is used. Is.

[0020]

In order to achieve the above object, according to the present invention, a plurality of pixel portions each including a pixel electrode portion, a liquid crystal and a counter electrode are provided, and voltages corresponding to the same display data are simultaneously supplied. A liquid crystal panel having a plurality of pixel section columns, pixel electrode driving means for converting pixel electrode driving data generated from input display data to pixel electrode driving voltages, and supplying the pixel electrode driving voltage to the plurality of pixel section columns; The counter electrode drive data generated from the input display data is converted into a counter electrode drive voltage, and the counter electrode drive means is supplied to the plurality of pixel unit columns.

Further, the driving circuit of the liquid crystal display device of the present invention comprises a scanning means for selecting one of the plurality of pixel electrode portions of the pixel portion column at the same time, and the plurality of pixel electrode portions are respectively provided. , A pixel electrode and a switching element for supplying the pixel electrode drive voltage to the pixel electrode when selected from the scanning means.

Further, the counter electrode driving means of the present invention stores the same number of data as the number of pixel section columns to which the pixel electrode driving means simultaneously supplies the pixel electrode driving voltage, and the storing means. It is characterized in that it has counter electrode moving means constituted by selecting means for selecting and outputting a counter electrode drive voltage according to the data.

Further, the pixel electrode driving means of the present invention simultaneously supplies different pixel electrode driving data to a plurality of pixel portion columns, and the counter electrode driving means supplies different counter electrode driving data to a plurality of pixel portion columns. The feature is that they are supplied at the same time.

Further, the pixel electrode driving means of the present invention and the counter electrode driving means separate the same display data from each other and output the generated pixel electrode driving voltage and the counter electrode driving voltage to the liquid crystal panel at the same time. It is characterized by.

Further, the pixel electrode driving means and the counter electrode driving means of the present invention output according to an alternating signal for controlling the periodic application of positive and negative voltages to the liquid crystal. It is characterized in that the pixel electrode drive voltage and the counter electrode drive voltage are changed.

Further, the counter electrode driving means of the present invention takes in an AC signal for controlling application of positive and negative voltages to the liquid crystal as pixel data to generate a liquid crystal counter voltage. It is a feature.

Further, the voltage range in which the maximum brightness and the minimum brightness of the liquid crystal of the present invention are obtained is wider than the voltage change range of the pixel electrode drive voltage and the voltage change range of the counter electrode drive voltage, respectively. It is characterized in that it is substantially equal to the change range of the potential difference between the voltage and the counter electrode drive voltage, and is smaller than the maximum potential difference between the pixel electrode drive voltage and the counter electrode drive voltage.

Further, the counter electrode driving means of the present invention divides the brightness range according to the voltage applied to the liquid crystal into two or more areas, and supplies the counter electrodes to each counter electrode according to the brightness area. It is characterized in that the drive voltage is changed.

Further, according to the driving method of the liquid crystal display device having a plurality of pixel portions for controlling the liquid crystal by the electric field generated between the pixel electrode and the counter electrode of the present invention, the input display data is used as the pixel electrode driving data. , An electric field generated between the pixel electrode and the liquid crystal counter electrode by dividing the counter electrode drive data into the pixel electrode drive data, supplying the pixel electrode drive data to the pixel electrode, supplying the counter electrode drive data to the counter electrode, It is characterized in that the liquid crystal is driven by.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In this embodiment,
A black-and-white 16-gradation liquid crystal panel of 640 horizontal dots × 480 vertical dots will be described. FIG. 4 is a configuration diagram of the liquid crystal display device of the present invention. The same components as those in FIG. 1 have the same reference numerals. 401 is a signal bus for transferring display data and display control signals supplied from a display control unit (not shown) such as a personal computer or a workstation, 402 is a liquid crystal controller, 403 is pixels to be supplied to a pixel electrode drive circuit. A signal bus for transferring the electrode driving data and the liquid crystal driving signal, and a signal bus 406 for transferring the counter electrode driving data and the liquid crystal driving signal supplied to the counter electrode driving circuit.

In this embodiment, 4-bit display data representing 16 gradations per pixel is transferred by the signal bus 401, and the liquid crystal controller 402 transfers the lower 3 bits of the display data by the signal bus 403 as pixel electrode drive data. , Signal bus 406 with the most significant bit as counter electrode drive data
Shall be transferred in. Regardless of the transfer method of the signal bus 401, parallel transfer or serial transfer may be used. In the case of serial transfer, the liquid crystal controller 402 performs serial-parallel conversion. 4
Reference numeral 09 is a power supply circuit, 410 is a counter electrode drive circuit which is a main part of the present invention, and 411 is a TFT liquid crystal panel.

Although omitted in the description of the conventional example, the drain bus 114 has signal lines corresponding to the number of display dots in the horizontal direction of the liquid crystal display (640 in this embodiment). It is expressed as 1-141-640. In the output of the power supply circuit 409, reference numeral 424 is a power supply bus that supplies a power supply voltage to the counter electrode drive circuit 410. Although described later in detail, the power supply circuit 409 supplies four levels of power supply voltage to the counter electrode drive circuit 410 in this embodiment.

Reference numeral 425 denotes an output terminal of the counter electrode drive circuit 410, which is a counter electrode bus for supplying the counter electrode voltage Vcom to the TFT liquid crystal panel 411. The counter electrode bus 425 has signal lines corresponding to the number of display dots (640 in this embodiment) in the horizontal direction of the liquid crystal display, and are expressed as 425-1 to 425-640 in order to distinguish them.

In the TFT liquid crystal panel 411, the drain bus 114, the counter electrode bus 425 and the gate bus 118 intersect in a matrix. A TFT 426, which is a switching element, is provided at the intersection, a gate bus 118 is connected to the gate electrode of the TFT 426, and a drain bus 114 is connected to the drain electrode. A source electrode 428 of the TFT 426 serves as one electrode for applying a voltage to the liquid crystal 427, and a counter electrode bus 425 is connected to the other counter electrode 429 for applying a voltage to the liquid crystal 427. Therefore, in this embodiment, the signal lines of the counter electrode bus 425 are common to the pixel portions arranged in the vertical direction, and the different signal lines are connected to the pixel portions arranged in the horizontal direction.

The pixel portions arranged in the vertical direction and to which the signal lines of the counter electrode bus 425 are commonly connected are referred to as a pixel portion column. Further, in the present invention, an electrode portion that applies a voltage to the liquid crystal 427 through the TFT 426 is referred to as a pixel electrode portion.

FIG. 5 is an explanatory diagram of the operation of the pixel electrode drive circuit 105. CL1 is a horizontal synchronizing signal, CL2 is a display data synchronizing clock signal, Data is display data, and Vd1 is a drain voltage indicated by the drain bus 114-1. Vd, Vd
2 is a drain voltage Vd indicated by the drain bus 114-2. CL1 and CL2 are included in the signal bus 401 or are generated by the liquid crystal controller 402 from a control signal sent through the signal bus 401. In this embodiment, the dynamic range of Vd1 and Vd2 is V
Let dw.

FIG. 6 is an explanatory diagram of the operation of the scanning circuit 106.
FLM is a vertical synchronizing signal, Vg1 is a gate bus 118-
1 is a gate voltage waveform, Vg2 is a gate voltage waveform of the gate bus 118-2, Vgon is a selection voltage level for selecting the pixel electrode portion, and Vgoff is a non-selection voltage level. F
The LM is also included in the signal bus 401, or is generated by the liquid crystal controller 402 from a control signal sent via the signal bus 401.

FIG. 7 is a block diagram of the counter electrode drive circuit 410, in which 701 is a memory circuit for sequentially fetching and storing counter electrode drive data transferred by the signal bus 406, and 702 is data for transferring the data stored in the memory circuit 701. bus,
Reference numeral 703 denotes a storage circuit that simultaneously captures and stores the data transferred by the data bus 702 in the CL1, 704 a data bus that simultaneously transfers the data stored in the storage circuit 703, 705 a level shifter, and 706 a level shifter 7.
M signal after voltage conversion of the M signal 104 in 05, 707
Is the data after voltage conversion by the level shifter 705, 70
8 is an inverting gate circuit, 709 is an M signal obtained by inverting the M signal 706 by the inverting gate circuit 708, 711 is a decoding circuit, 710 is a decoder per output, 712 is a signal bus for outputting the decoding result of the decoding circuit, and 713 is The voltage selection circuit 714 is a voltage selector per one output terminal.

FIG. 8 is an explanatory diagram of the operation of the counter electrode drive circuit. Data is counter electrode drive data sent one after another on the signal bus 406, M is an M signal 104, Vcom1da.
ta is data of the first dot in the horizontal direction of the above Data, and Vcom2Data is data of the second dot of the same. Vcom1 is the voltage waveform of the counter electrode bus 425-1 generated according to Vcom1Data, which is the counter electrode voltage corresponding to the pixel electrode section driven by the drain bus 114-1, and Vcom2 is the counter electrode bus 425-2 generated according to Vcom2Data. The counter electrode voltage corresponding to the pixel electrode portion driven by the drain bus 114-2 becomes the voltage waveform of

VcomPH, VcomPL, VcomN
H and VcomNL are power supply voltages supplied by the power supply bus 424. VcomPH and VcomPL are positive counter electrode voltage levels. VcomPH is a high level voltage and Vco.
mPL is a low level voltage. VcomNH, Vco
mNL is a negative counter electrode voltage level, VcomNH is a high level voltage, and VcomNL is a low level voltage. Here, it is assumed that the difference between the high level voltage and the low level voltage is larger than the dynamic range Vdw of the drain voltage Vd indicated by the drain bus 114. In addition, M, Vcom1Data, Vcom2Da shown in this figure
ta and the like indicate the first and subsequent lines of a certain frame.

FIG. 9 shows the drain voltage Vd and the gate voltage V
6 shows a timing chart of the counter electrode voltage Vcom, and the state of the voltage applied to the liquid crystal 427. FIG. 10 is a voltage-luminance characteristic diagram of the liquid crystal 427, in which the horizontal axis represents the voltage applied to the liquid crystal 427 and the vertical axis represents the luminance. In the present embodiment, a normally white liquid crystal will be described in which the lower the voltage applied to the liquid crystal, that is, the closer the drain voltage Vd is to the counter electrode voltage Vcom, the higher the brightness, that is, the higher the light transmittance.

The operation will be described in detail with reference to FIGS. The liquid crystal controller 402 sends the display data and the display control signal transferred by the signal bus 401 to the display data and the liquid crystal drive signal (CL1,
CL2, M signal 104). Then, the lower 3 bits of the pixel electrode drive data and the liquid crystal drive signal of the display data of 4 bits for each pixel transferred by the signal bus 401 are supplied to the pixel electrode drive circuit 105 via the signal bus 403.
The liquid crystal drive signal supplied to the scanning circuit 106 is supplied to the signal bus 10.
3, the power supply circuit 409, the counter electrode drive circuit 410
The M signal 104 supplied to the
The counter electrode drive data of the most significant bit of the 4-bit display data of each pixel and the liquid crystal drive signal (CL1,
CL2) via the signal bus 406 to the counter electrode drive circuit 4
Supply to 10.

The pixel electrode drive circuit 105 includes a signal bus 40.
The pixel electrode drive data transferred in 3 is sequentially fetched and stored in the memory circuit 109 by the synchronized clock signal CL2 as shown in FIG. 5, and the stored display data is sequentially output. When the storage circuit 109 finishes loading the display data for one horizontal line, that is, when the display data for one horizontal line of 640 dots appears on the signal bus 110, the stored display data is simultaneously processed for one horizontal line by the horizontal synchronizing signal CL1. Captured in the memory circuit 111. The display data stored in the storage circuit 111 is transferred to the gradation voltage generation circuit 113 via the signal bus 112, and in the gradation voltage generation circuit 113, the drain voltages Vd1 to Vd6 corresponding to the display data for each pixel.
40, and the drain buses 114-1 to 114-64
Output to 0.

In the present embodiment, since each pixel corresponds to 3-bit pixel electrode drive data, the gradation voltage generating circuit 113 has one of eight levels of drain voltage (the minimum level is VdL1 and the maximum level is VdL8). Is output. Further, the gradation voltage generation circuit 113 inverts the correspondence relationship between the display data and the drain voltage for each line by using the M signal 104 and outputs the same, as in the conventional example. Specifically, the voltage of VdL1 and VdL8 is M as the gradation voltage corresponding to the display data designating the maximum brightness.
The signals 104 are alternately output. VdL2 as the gradation voltage corresponding to the display data specifying the second luminance
And the voltages of VdL7 are alternately output according to the M signal 104.

The pixel electrode drive circuit 105 outputs the drain voltage V
In synchronization with generating d and outputting it to the drain bus 114, the scanning circuit 106 sequentially applies the gate voltage Vgon to any one of the gate buses 118. Scanning circuit 10
6, the shift register 115 sequentially generates a pulse as a reference of the gate voltage based on the display control signal CL1 (horizontal synchronizing signal) transferred by the signal bus 103, and the level shifter 117 causes the TFT 4 in the liquid crystal panel 411 to generate a pulse.
The voltage at which 26 is in the selected or non-selected state (selected voltage level:
Vgon, non-selected voltage level: Vgoff) and output to the gate bus 118.

This operation will be described with reference to FIG. 6. When the vertical synchronizing signal FLM transferred by the signal bus 103 becomes high level and the horizontal synchronizing signal CL1 is inputted, the gate of the first line of the gate bus 118 is gated. The voltage Vg1 becomes the selection voltage level Vgon, and the other gate line voltages Vg become the non-selection level Vgoff. When the vertical synchronizing signal FLM becomes low level and the horizontal synchronizing signal CL1 is input, the gate voltage Vg1 of the first line of the gate bus 118 becomes the non-selection voltage level Vgoff, and the gate voltage Vg2 of the second line of the gate bus 118. Is the selection voltage level V
gon.

Thus, every time CL1 is input, the selection voltage level Vgon of the gate bus 118 is sequentially applied for one horizontal line period. Then, by repeating this for one frame period, all the lines can be selected while being switched, and the drain voltage Vd transferred from the drain bus 114 can be applied to the liquid crystal 427.
By applying the non-selection voltage Vgoff to the gate bus 118, the grayscale voltage applied to the liquid crystal 427 is held.

Next, the operation of the counter electrode drive circuit 410 will be described with reference to FIGS. 7 and 8. The counter electrode voltage drive circuit 410 sequentially takes in the counter electrode drive data transferred by the signal bus 406 to the memory circuit 701 by the clock signal CL2 also transferred by the signal bus 406, stores the same, and sequentially outputs the stored display data. . Memory circuit 70
When 1 has taken in the display data for one horizontal line,
That is, when display data for one horizontal line of 640 dots appears on the data bus 702, the stored display data is simultaneously stored for one horizontal line by the horizontal synchronizing signal CL1 in the storage circuit 703.
Take in. The display data stored in the storage circuit 703 is voltage-converted by the level shifter 705 via the data bus 704 and transferred to the decoding circuit 711 via the signal bus 707.

Decode circuit 711 and voltage selection circuit 713
The operation 1) will be described from the first line to the fourth line with reference to FIGS. 7 and 8. The first line is M signal 104
Is low level, and the level shifter 705 and the inverting circuit 7
Since the M signal 709 via 08 becomes high level, in the decoding circuit 711 and the voltage selection circuit 713, one of the negative counter electrode voltage levels: VcomNH, VcomNL is selected. The first line is the display data Vc
Since om1data is "1" and Vcom2data is "0", VcomNH is valid for Vcom1, and Vcom
2 operates so that VcomNL becomes valid.

In the second line, the M signal 104 is at a high level, and the M signal 706 via the level shifter 705 is also at a high level. Therefore, in the decoding circuit 711 and the voltage selection circuit 713, the positive counter electrode voltage level: Vcom
Either PH or VcomPL is selected. In the second line, the display data Vcom1data is "1", Vco
Since m2data is "0", Vcom1 is VcomPL
Becomes valid, and Vcom2 operates so that VcomPH becomes valid.

In the third line, the M signal 104 is at a low level and the M signal 709 via the level shifter 705 and the inverting circuit 708 is at a high level, so that the decode circuit 711 and the voltage selection circuit 713 have a negative polarity. Counter electrode voltage level: either VcomNH or VcomNL is selected. The third line is display data Vcom1
Since data is "0" and Vcom2data is "1", Vc
VcomNL is valid for om1 and Vc for Vcom2
Operates so that omNH is valid.

In the fourth line, the M signal 104 is at a high level and the M signal 706 via the level shifter 705 is also at a high level. Therefore, in the decode circuit 711 and the voltage selection circuit 713, the positive counter electrode voltage level: Vcom
Either PH or VcomPL is selected. On the 4th line, the display data Vcom1data is "0", Vco
Since m2data is "1", Vcom1 is VcomPH
Becomes valid, and Vcom2 operates so that VcomPL becomes valid. The description of the subsequent lines is omitted.

Here, the effective value of the voltage applied to the liquid crystal when the counter electrode voltage Vcom reaches each voltage level is shown in FIG.
This will be described with reference to FIGS.

FIG. 9 shows the effective voltage values applied to the liquid crystals on the second and third lines in the same situation as in FIG. In the second line, M signal 10
4 is at a high level, and at this time, the gradation voltage generation circuit 1
13 outputs VdL1 if the pixel electrode drive data is the lowest luminance display data, and VdL8 if it is the highest luminance display data. Further, Vcom1 is a voltage level VcomP.
And the voltage applied to the liquid crystal 427 is VdL1
(At the lowest brightness) to VdL8 (at the highest brightness) Vc
Since it becomes omPL, the minimum value Vrms1- and the maximum value Vr
It becomes ms2-. Similarly, Vcom2 is a voltage level Vc
and the voltage applied to the liquid crystal 427 is Vd.
Since VcomPH is for L1 (at the lowest brightness) to VdL8 (at the highest brightness), the minimum value is Vrms3- and the maximum value is Vrms4-.

Therefore, as shown in FIG. 10, the effective voltage value Vr
Display of a high luminance region in the voltage luminance characteristic of the liquid crystal can be realized in the region of ms1- to Vrms2-, that is, in the dynamic range Vdw of the drain voltage Vd when the counter electrode voltage Vcom is VcomPL, and the effective voltage value Vrms3-.
To Vrms4-, that is, the counter electrode voltage is Vc
With the dynamic range Vdw of the drain voltage Vd at the time of omPH, it is possible to realize the display in the low luminance region in the voltage luminance characteristic of the liquid crystal.

In the third line, the M signal 104 is at low level, and at this time, the gradation voltage generating circuit 113
Outputs VdL8 if the pixel electrode drive data is the lowest luminance display data, and VdL1 if it is the highest luminance display data. Further, Vcom1 is the voltage level VcomNL, and the voltage applied to the liquid crystal 427 is VdL8 (at the lowest brightness) to VdL1 (at the highest brightness) with respect to VcomNL, so the minimum value Vrms3 + and the maximum value Vrms.
It becomes 4+. Similarly, Vcom2 is a voltage level Vcom
It is NH, and the voltage applied to the liquid crystal 427 is Vcom.
Since VdL8 (at the lowest brightness) to VdL1 (at the highest brightness) with respect to NH, the minimum value Vrms1 + and the maximum value Vr
It becomes ms2 +.

Therefore, as shown in FIG. 10, the effective voltage value Vr
It is possible to realize display in a high luminance region in the voltage luminance characteristic of the liquid crystal in the region of ms1 + to Vrms2 +, that is, in the dynamic range Vdw of the drain voltage Vd when the counter electrode voltage is VcomNH, and to display the effective voltage value Vrms3 + to Vrms3 +
ms4 + area, that is, the counter electrode voltage is VcomNL
With the dynamic range Vdw of the drain voltage Vd at that time, display in a low brightness region can be realized in the voltage brightness characteristic of the liquid crystal.

As described above, the electric field between the pixel electrode and the counter electrode is periodically inverted by the M signal, and AC driving of the liquid crystal can be realized. Therefore, as shown in FIG. 10, a liquid crystal material having a gradual luminance change with respect to the voltage, that is, a liquid crystal having a voltage level width from the maximum luminance to the minimum luminance wider than the dynamic range Vdw of the drain voltage Vd output from the pixel electrode drive circuit 105. Even if the material is used, sufficient contrast can be obtained.

Further, the counter electrode drive circuit 410 can set VcomPH and VcomPL to all the counter electrode buses 425 independently of each other, similarly to the pixel electrode drive circuit 105. Therefore, the pixel electrode drive circuit having the dynamic range Vdw can be set. Even when 105 is used, Vcom for each pixel
According to the voltage level of, the display of the high brightness area and the low brightness area can be realized at the same time.

Further, in the past, the pixel electrode drive circuit 105 was used.
Gradation levels that can be generated (8 levels in this embodiment)
However, in the present embodiment, the counter electrode voltage Vcom output from the counter electrode drive circuit 410 is represented.
Since the positive and negative polarity voltage levels can be set to two levels, the same pixel electrode drive circuit 105 can be used to generate gradation voltages of positive and negative levels of 16 levels. That is, the number of displayable gray scales can be increased by using the pixel electrode drive circuit that has been conventionally used.

Further, if the present embodiment is applied without limiting the pixel electrode drive circuit 105 to eight gradations, the number of gradations that is twice the number of gradation levels that the pixel electrode drive circuit can generate can be generated. Further, the counter electrode voltage of the present embodiment is not limited to the positive polarity 2 level and the negative polarity 2 level, but is increased to increase the number of gray scale levels of 2 that can be generated by the pixel electrode drive circuit.
It is possible to generate more than double the number of gradations,
A liquid crystal material whose luminance changes more slowly than that shown in FIG.
That is, sufficient contrast can be obtained even when using a liquid crystal material that requires a voltage level width twice or more than the drain voltage dynamic range Vdw that can be generated by the pixel electrode drive circuit from the maximum brightness to the minimum brightness. .

Therefore, as a second embodiment, an example using the counter electrode drive circuit 410 capable of generating the counter electrode voltage Vcom having four levels of positive polarity and four levels of negative polarity will be described. The counter electrode driving circuit 410 of the first embodiment inputs the most significant bit data of display data and the M signal, and the counter electrode voltage levels (VcomPH, Vc) are two levels in both positive polarity and negative polarity.
omPL and VcomNH, VcomNL), whereas the second embodiment uses a counter electrode drive circuit 410.
Receives the upper 2-bit data of the display data and the M signal, and has four levels of the counter electrode voltage levels (VcomP4, VcomP3, VcomP2, V) for both positive and negative polarities.
comP1 and VcomN4, VcomN3, Vcom
N2, VcomN1) is generated.

This will be described with reference to FIGS. 11, 12, 13, and 14. FIG. 11 is a block diagram of the counter electrode drive circuit 410 according to the present embodiment. Reference numeral 1101 is a storage circuit for sequentially fetching and storing the upper 2 bits of the counter electrode drive data transferred by the signal bus 406, and 1102 is stored in the storage circuit 1101. A data bus 1103 for transferring data, a storage circuit 1103 for simultaneously capturing and storing the data transferred by the data bus 1102 in the CL1, and 1104 a storage circuit 1
A data bus for simultaneously transferring the data stored in 103,
1105 is a level shifter and 1106 is a level shifter 11.
M signal after voltage conversion of M signal 104 in 05, 110
7 is the data after voltage conversion by the level shifter 1105,
Reference numeral 1108 denotes an inverting gate circuit, 1109 denotes an M signal 1106.
M signal 1111 inverted by the inverting gate circuit 1108
Is a decoding circuit, 1110 is a decoder per output,
Reference numeral 1112 is a signal bus for outputting the decoding result of the decoding circuit, 1113 is a voltage selection circuit, and 1114 is a voltage selector per output terminal.

FIG. 12 is an explanatory diagram of the operation of the counter electrode drive circuit. Data is counter electrode drive data sent one after another on the signal bus 406, M is an M signal 104, Vcom1da.
ta-bit0 is Vcom1Data-bit, which is data of bit 0 of the first dot in the horizontal direction in the above Data.
Similarly, 1 is data of bit 1. Vcom-1 is V
counter electrode bus 425 generated according to comData
With a voltage waveform of −1, a counter electrode voltage corresponding to the pixel electrode section driven by the drain bus 114-1 is obtained, and VcomP
4 to VcomP1 is a positive counter electrode voltage level, Vc
omP4 is the highest voltage and VcomP1 is the lowest voltage.
VcomN4 to VcomN1 are negative counter electrode voltage levels, VcomN4 is the voltage with the highest absolute value, VcomN
1 is the voltage with the lowest absolute value.

FIG. 13 is a timing chart of the drain voltage Vd, the gate voltage Vg, and the counter electrode voltage Vcom, showing the state of the voltage applied to the liquid crystal 427. FIG. 14 is a voltage-luminance characteristic diagram of the liquid crystal 427, in which the horizontal axis represents the voltage applied to the liquid crystal 427 and the vertical axis represents the luminance. In the present embodiment, a normally white liquid crystal will be described in which the lower the voltage applied to the liquid crystal, that is, the closer the drain voltage Vd is to the counter electrode voltage Vcom, the higher the brightness, that is, the higher the light transmittance.

The counter electrode voltage drive circuit 410 shown in FIG.
The two-bit counter electrode drive data transferred by the signal bus 406 is sequentially fetched and stored in the memory circuit 1101 by the clock signal CL2 also transferred by the signal bus 406, and the stored display data is sequentially output. Storage circuit 11
01 completes fetching the display data for one horizontal line, that is, one horizontal line 640 on the data bus 1102.
Minute display data appears, the stored display data is stored in the storage circuit 110 at the same time for one horizontal line by the horizontal synchronization signal CL1.
Take in 3. The display data stored in the storage circuit 1103 is subjected to voltage conversion by the level shifter 1105 via the data bus 1104 and transferred to the decoding circuit 1111 via the signal bus 1107.

Decode circuit 1111 and voltage selection circuit 11
The operation of 13 will be described with reference to FIG. When the M signal 104 is at a high level, the M signal 1106 via the level shifter 1105 is also at a high level. Therefore, in the decoding circuit 1111 and the voltage selection circuit 1113, the positive counter electrode voltage levels: VcomP1, VcomP2, Vco.
Either mP3 or VcomP4 is in the selected state. Counter electrode drive data Vcom1Data-bit1, bi
When t0 is “11”, VcomP1 is valid, and the counter electrode drive data Vcom1Data-bit1 and bit0 are set.
Is "10", VcomP2 is valid. When the counter electrode drive data Vcom1Data-bit1, bit0 is "01", VcomP3 is valid, and the counter electrode drive data Vcom1Data-bit1, bit0 is "0".
When 0 ", VcomP4 operates so as to be valid.

Similarly, when the M signal 104 is at low level,
Since the M signal 1109 that has passed through the level shifter 1105 and the inverting circuit 1108 becomes high level, the decoding circuit 11
11 and the voltage selection circuit 1113, negative counter electrode voltage levels: VcomN1, VcomN2, VcomN.
3 or VcomN4 is selected. When the counter electrode drive data VcomData-bit1, bit0 is "11", VcomN1 is valid for Vcom1, and VcomData-bit1, bit0 is "10".
, VcomN2 becomes valid and VcomData-
When bit1 and bit0 are "01", VcomN3 is valid, and when VcomData-bit1 and bit0 are "00", VcomN4 is valid.

Here, the effective voltage value applied to the liquid crystal when the counter electrode voltage Vcom reaches each voltage level is shown in FIG.
3 and FIG. 14 will be described. Note that Vcomdata that generates each Vcom in FIG. 13 is different from the description in FIG. 12. On the first line, M signal 10
4 is at a low level, and at this time, the gradation voltage generation circuit 1
13 outputs VdL8 if the pixel electrode drive data is the lowest luminance display data, and VdL1 if it is the highest luminance display data. Furthermore, V generated from Vcomdata
com1 is the voltage level VcomN1, and the liquid crystal 427
The voltage applied to VcomL1 is VdL8 with respect to VcomN1.
(At the lowest brightness) to VdL1 (at the highest brightness),
The minimum value Vrms1 + and the maximum value Vrms2 + are obtained. Similarly, Vcom2 generated from Vcomdata is the voltage level VcomN3, and the voltage applied to the liquid crystal 427 is VdL8 (at the lowest luminance) to VcomN3.
Since it is VdL1 (at maximum brightness), the minimum value Vrms5
+, The maximum value Vrms6 +.

In the second line, the M signal 104 is at high level, and at this time, the gradation voltage generating circuit 113
Outputs VdL1 if the pixel electrode drive data is the lowest luminance display data, and VdL8 if it is the highest luminance display data. Furthermore, Vco generated from Vcomdata
m1 is the voltage level VcomP1, and the voltage applied to the liquid crystal 427 is from VdL1 (at the lowest luminance) to VdL8.
Since VcomP1 with respect to (at the time of maximum brightness), the minimum value Vrms1- and the maximum value Vrms2- are obtained. Similarly,
Vcom2 generated from Vcomdata is the voltage level VcomP3, and the voltage applied to the liquid crystal 427 is VdL1 (at the lowest brightness) to VdL8 (at the highest brightness).
VcomP3 with respect to the minimum value Vrms5
−, The maximum value Vrms6−.

In the third line, the M signal 104 is at a low level, and at this time, the gradation voltage generating circuit 113
Outputs VdL8 if the pixel electrode drive data is the lowest luminance display data, and VdL1 if it is the highest luminance display data. Furthermore, Vco generated from Vcomdata
m1 is the voltage level VcomN2, and the voltage applied to the liquid crystal 427 is VdL8 (at the lowest brightness) to VdL1 (at the highest brightness) with respect to VcomN2, and therefore has the minimum value Vrms3 + and the maximum value Vrms4 +. Similarly, V
Vcom2 generated from comdata is the voltage level VcomN4, and the voltage applied to the liquid crystal 427 is
VdL8 (at the lowest brightness) to VcomL for VcomN4
Since it is 1 (at the time of maximum brightness), it has a minimum value Vrms7 + and a maximum value Vrms8 +.

In the fourth line, the M signal 104 is at a high level, and at this time, the gradation voltage generating circuit 113
Outputs VdL1 if the pixel electrode drive data is the lowest luminance display data, and VdL8 if it is the highest luminance display data. Furthermore, Vco generated from Vcomdata
m1 is a voltage level VcomP2, and the voltage applied to the liquid crystal 427 is from VdL1 (at the minimum luminance) to VdL8.
Since it is VcomP2 with respect to (at the time of maximum brightness), it has a minimum value Vrms3- and a maximum value Vrms4-. Similarly,
Vcom2 generated from Vcomdata is the voltage level VcomP4, and the voltage applied to the liquid crystal 427 is VdL1 (at the lowest brightness) to VdL8 (at the highest brightness).
Therefore, the minimum value Vrms7
-, The maximum value Vrms8-.

Therefore, as shown in FIG. 14, the effective voltage value Vr
Display of the region from ms1 + to Vrms2 +, that is, the first region in the voltage-luminance characteristic of the liquid crystal can be realized in the dynamic range Vdw of the drain voltage Vd when the counter electrode voltage is VcomN1. Similarly, the effective voltage value Vrms3
The area from + to Vrms4 +, that is, the counter electrode voltage is V
display of the second luminance region in the voltage luminance characteristic of the liquid crystal can be realized with the dynamic range Vdw of the drain voltage Vd at the time of comN2, and the effective voltage value Vrms5 + to Vrm
The region of s6 +, that is, the display of the second luminance region in the voltage luminance characteristic of the liquid crystal can be realized in the dynamic range Vdw of the drain voltage Vd when the counter electrode voltage is VcomN3, and the region of the voltage effective value Vrms7 + to Vrms8 +, that is, The display of the second luminance region in the voltage luminance characteristic of the liquid crystal can be realized within the dynamic range Vdw of the drain voltage Vd when the counter electrode voltage is VcomN4. The same applies when the counter electrode voltage is VcomP1 to VcomP4.

Therefore, the pixel electrode drive circuit 105 has a liquid crystal material having a gradual change in luminance with respect to a voltage as shown in FIG. 14, that is, a voltage level width from the maximum luminance to the minimum luminance.
Dynamic range vd of drain voltage Vd output by
Even when a liquid crystal material wider than w is used, sufficient contrast can be obtained. Further, in the second embodiment as well, similarly to the first embodiment, the counter electrode drive circuit 410 independently sets the counter electrode value Vco in all the counter electrode buses 130.
Since m can be set, the dynamic range V
Even when the dw pixel electrode drive circuit 105 is used, display of each luminance region can be realized at the same time according to the voltage level of Vcom for each pixel.

Further, conventionally, the pixel electrode drive circuit 105 is used.
Gradation levels that can be generated (8 levels in this embodiment)
However, in the present embodiment, the counter electrode voltage Vcom output from the counter electrode drive circuit 410 is represented.
Since the positive voltage and the negative voltage can be set to four levels, the same pixel electrode drive circuit 105 can be used to generate gradation voltages of positive and negative levels of 32 levels. Further, if the present embodiment is applied without limiting the pixel electrode driving circuit 105 to eight gradations, the number of gradations that is twice the number of gradation levels that the pixel electrode driving circuit can generate can be generated.

Although 16 gradations and 32 gradations have been described in the above embodiment, the total number of gradations can be further increased by increasing the number of gradations of each of the pixel electrode drive circuit and the counter electrode drive circuit. . Specifically, 256 gradations are required for each primary color for full-color display. For that purpose, 16 gradations of the pixel electrode driving circuit × 16 gradations of the counter electrode driving circuit, similarly 32 gradations × 8 gradations ( Or vice versa), similarly, a combination of 64 gradations × 4 gradations (or vice versa) can be considered. By increasing either of the gradation numbers, more gradations (the number of colors in the case of color) can be achieved.

The first and second embodiments have been described on the premise that the display data transferred by the signal bus 100 is a digital signal, but the first embodiment corresponds to the case where the pixel electrode drive circuit is analog-processed. The third embodiment will be described.

FIG. 15 is a block diagram of the third embodiment.
Reference numeral 501 is a PC, a system bus of the WS main body, 1502 is a display controller, 1503 is a display memory, 1504 is a display memory bus, 1505 is a signal bus for transferring upper bit digital data of display data and a display control signal, 150
Reference numeral 6 is a signal bus for transferring a lower bit digital data of the display data and a clock synchronized with the display data. Fifteen
Reference numeral 07 is an analog / digital conversion circuit for converting digital display data into analog display data, and 1508 is a signal bus for transferring the analog display data. Reference numeral 1509 denotes a liquid crystal controller, 1510 denotes a signal bus for transferring analog display data and a liquid crystal drive signal supplied to the pixel electrode drive circuit, and in the present embodiment, the upper bits of the display data transferred by the signal bus 1505 are set to the signal bus 406. Shall be transferred.

Reference numeral 1511 is a pixel electrode drive circuit. In the pixel electrode drive circuit 1511, 1512 is the signal bus 1.
A sampling circuit that sequentially captures and stores analog display data transferred at 510, a data bus 1513 that transfers the analog display data stored at the sampling circuit 1512, and a reference circuit 1514 that simultaneously captures and stores analog display data transferred at the data bus 1513. A hold circuit, 1515 is a data bus for transferring analog display data stored in the hold circuit 1514, 1516 is an amplifier circuit for inputting and amplifying analog display data transferred by the data bus 1515, and 117 is a pixel electrode driving circuit 1511. Drain voltage Vd which is the gradation voltage at the output terminal of
Is a drain bus for transferring to the TFT liquid crystal panel.

The liquid crystal controller 1509 corresponds to the signal bus 1
The display data and the display control signal transferred at 505 and 1508 are converted into display data and a liquid crystal drive signal for driving the liquid crystal display device. When the transfer speed of the analog display data transferred by the signal bus 1508 is faster than the sampling speed of the sampling circuit 1512 of the pixel electrode drive circuit 1511, serial / parallel conversion is performed and the analog display data is transferred by the signal bus 1510. Pixel electrode drive circuit 1511
Displays the display data transferred by the signal bus 1510 into the sampling circuit 1412 sequentially by the clock signal CL2 synchronized with the display data as described in FIG. Then, the pixel electrode drive circuit 1511 transfers the analog display data stored in the sampling circuit 1512 to the signal bus 1513.

When the sampling circuit 1512 finishes capturing the analog display data for one horizontal line, that is,
When the analog display data for one horizontal line appears on the signal bus 1513, the stored analog display data is simultaneously held for one horizontal line by the horizontal synchronizing signal CL1.
Take in 14. The analog display data stored in the hold circuit 1514 is sent to the amplifier circuit 1 via the signal bus 1515.
The analog display data is transferred to 516 and amplified by the amplifier circuit 1516 to generate a drain voltage, which is output to the drain bus 117. The operation of the counter electrode drive circuit 410 and the operation of applying a voltage to the liquid crystal 427 are the same as those in the first embodiment.

Therefore, even when the pixel electrode drive circuit 1511 that handles analog display data is used, a liquid crystal material having a gradual change in brightness as in the first embodiment, that is, a pixel electrode drive circuit from maximum brightness to minimum brightness. Even if a liquid crystal material that requires a voltage level width twice or more than the drain voltage dynamic range Vdw that can be generated is used, sufficient contrast can be obtained. In the present embodiment, all the display data may be converted into analog and sent out, and once digitized on the liquid crystal display side, only the most significant bit which becomes the pixel electrode drive data may be separated and analogized again. Alternatively, all the display data may be digitized and sent out, and the liquid crystal display device side may separate the most significant bit to be the pixel electrode drive data and then analogize it.

In each of the above-described embodiments, a black and white liquid crystal panel having 640 dots in the horizontal direction and 480 dots in the vertical direction has been described, but this is an example, and even if the number of dots in the horizontal direction and the number of dots in the vertical direction change. Needless to say, the present invention can be similarly applied. Further, in each of the above-described embodiments, the normally white liquid crystal has been described in which the lower the applied voltage of the liquid crystal, that is, the closer the drain voltage Vd is to the counter electrode voltage Vcom, the higher the brightness, that is, the higher the light transmittance is. On the contrary, even when the normally black liquid crystal having a lower brightness, that is, a lower light transmittance, is used as the drain voltage Vd is closer to the counter electrode voltage Vcom, it can be similarly realized. That is, the relationship between the drain voltage Vd and the display data and the relationship between the drain voltage Vd and the counter electrode voltage and the display data may be reversed.

In each of the above embodiments, the monochrome display is explained. However, color display is also possible by providing the above-mentioned configuration for each of the RGB three primary colors. In this case, the interface between the liquid crystal display device of the present invention and the display control unit of a personal computer or the like may be the same as the conventional interface.

Further, in color display, by providing an offset value for each primary color to the counter electrode drive voltage in advance, it is possible to provide a color correction function. To be more specific, in the configuration of FIG. 7, the Vcom 424 is prepared in advance by changing the value little by little and several sets are made, and a register for storing the correction value for each color is provided. When displaying, a correction value is set from a display control unit such as a personal computer, and Vcom4 is set for each color using the correction value.
The correction becomes possible by selecting one set of 24. Or
The Vcom 424 is made in fine steps, and a voltage having a certain value among them is selected as a set by the correction value. A voltage value may be selected from the set of voltages according to the counter electrode drive data. If the same set of correction values are effective for the same primary color,
Color correction is possible.

[0086]

As described above, according to the present invention, the voltage brightness characteristic for obtaining a sufficient contrast characteristic is wider than the output dynamic range width of the pixel electrode driving circuit for generating the gradation voltage. Even if the liquid crystal material is used, it is possible to control the voltage level of the counter electrode for each pixel, so that it is possible to obtain sufficient contrast and the number of gradations by using the pixel electrode drive circuit. is there.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a conventional liquid crystal display device.

FIG. 2 is an explanatory diagram of a conventional gradation voltage applying operation.

FIG. 3 is a voltage-luminance characteristic diagram of a TFT liquid crystal panel.

FIG. 4 is a configuration diagram of a liquid crystal display device of the present invention.

FIG. 5 is an explanatory diagram of the operation of the pixel electrode drive circuit of the present invention.

FIG. 6 is an explanatory diagram of the operation of the scanning circuit of the present invention.

FIG. 7 is a block diagram of a counter electrode drive circuit according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram of an operation of the counter electrode drive circuit according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram of a grayscale voltage applying operation according to the first embodiment of the present invention.

FIG. 10 is a voltage-luminance characteristic diagram in the first example of the present invention.

FIG. 11 is a block diagram of a counter electrode drive circuit according to a second embodiment of the present invention.

FIG. 12 is an explanatory diagram of the operation of the counter electrode drive circuit according to the second embodiment of the present invention.

FIG. 13 is an explanatory diagram of a grayscale voltage applying operation according to the second embodiment of the present invention.

FIG. 14 is a voltage / luminance characteristic diagram in the second example of the present invention.

FIG. 15 is a device configuration diagram in a third embodiment of the liquid crystal display device of the present invention.

[Explanation of symbols]

100 ... Signal bus, 101 ... Liquid crystal controller, 102 ... Signal bus, 1
03 ... signal bus, 104 ... M signal,
105 ... Pixel electrode driving circuit, 106 ... Scanning circuit,
107 ... Power supply circuit, 108 ... TFT liquid crystal panel, 109 ... Storage circuit, 110 ... Data bus, 111 ... Storage circuit, 112 ... Data bus, 113 ... Gradient voltage generating circuit, 114 ... Drain bus, 115 ... Shift register, 116 … Data bus,
117 ... Level shifter, 118 ... Gate bus,
119 ... Power bus, 120 ... Power bus,
121 ... power bus, 122 ... TFT,
123 ... Liquid crystal, 124 ... Source electrode,
401 ... Signal bus, 402 ... Liquid crystal controller, 403 ... Signal bus, 406 ... Signal bus, 409 ... Power supply circuit, 410 ...
Counter electrode drive circuit, 411 ... TFT liquid crystal panel, 422 ... Power supply bus, 423 ... Power supply bus, 424 ... Power supply bus, 425
... Counter electrode bus, 426 ... TFT,
427 ... Liquid crystal, 428 ... Source electrode,
429 ... Counter electrode, 701 ... Memory circuit,
702 ... Data bus, 703 ... Storage circuit,
704 ... Data bus, 705 ... Level shifter, 706 ... M signal, 707 ... Data,
708 ... Inversion gate circuit, 709
... M signal, 710 ... Decoding circuit, 711 ... Decoder, 712 ... Signal bus, 713 ... Voltage selection circuit, 714
... voltage selector 1101, ... memory circuit,
1102 ... data bus, 1103 ... memory circuit,
1104 ... Data bus, 1105 ... Level shifter, 1106 ... M signal, 1107 ... Data, 1108 ... Inversion gate circuit, 1
109 ... M signal, 1110 ... Decoding circuit, 1111 ... Decoder, 111
2 ... Signal bus, 1113 ... Voltage selection circuit,
1114 ... Voltage selector.

Front page continued (72) Inventor Yasuyuki Kudo 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Toshio Futami 3300, Hayano, Mobara-shi, Chiba Hitachi Ltd. Electronic Devices Within the business unit

Claims (10)

[Claims] 1. A liquid crystal panel comprising a plurality of pixel portions each comprising a pixel electrode portion, a liquid crystal and a counter electrode, and a plurality of pixel portion rows to which voltages corresponding to the same display data are simultaneously supplied, and an input display. Pixel electrode drive data generated from the data is converted into a pixel electrode drive voltage and supplied to the plurality of pixel unit columns, and counter electrode drive data generated from the input display data is driven by the counter electrode. A driving circuit for a liquid crystal display device, comprising: a counter electrode driving unit that converts the voltage into a voltage and supplies the pixel unit column with the counter electrode. 2. A driving circuit of the liquid crystal display device includes a scanning unit that simultaneously selects one of the plurality of pixel electrode portions of the pixel portion column, and each of the plurality of pixel electrode portions includes a pixel. 2. The drive circuit for a liquid crystal display device according to claim 1, comprising an electrode and a switching element which supplies the pixel electrode drive voltage to the pixel electrode when selected by the scanning means. 3. In the counter electrode driving means, a storage means for storing the same number of data as the number of pixel portion columns to which the pixel electrode driving means simultaneously supplies the pixel electrode driving voltage, and the data stored in the storage means. 3. The drive circuit for a liquid crystal display device according to claim 1, further comprising a counter electrode moving means configured by a selecting means for selecting and outputting a counter electrode driving voltage according to the counter electrode driving voltage. 4. The pixel electrode driving means simultaneously supplies different pixel electrode driving data to a plurality of pixel portion columns, and the counter electrode driving means simultaneously supplies different counter electrode driving data to a plurality of pixel portion columns. 4. The drive circuit for a liquid crystal display device according to claim 1, wherein the drive circuit is a liquid crystal display device. 5. The pixel electrode driving means and the counter electrode driving means separate the same display data from each other, and simultaneously output the generated pixel electrode driving voltage and the counter electrode driving voltage to the liquid crystal panel. The drive circuit for the liquid crystal display device according to claim 1. 6. The pixel electrode driving means and the counter electrode driving means output pixel electrode driving in response to an alternating signal for controlling application of a positive polarity voltage and a negative polarity voltage to the liquid crystal periodically. 6. The drive circuit for a liquid crystal display device according to claim 1, wherein the voltage and the counter electrode drive voltage are changed. 7. The counter electrode driving means takes in an alternating signal for controlling application of positive and negative voltages to the liquid crystal as pixel data to generate a liquid crystal counter voltage. A drive circuit for a liquid crystal display device according to claim 1. 8. The voltage range in which the maximum brightness and the minimum brightness of the liquid crystal are obtained is wider than the voltage change range of the pixel electrode drive voltage and the voltage change range of the counter electrode drive voltage, respectively. 8. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is substantially equal to a change range of a potential difference from a counter electrode drive voltage and smaller than a maximum potential difference between the pixel electrode drive voltage and the counter electrode drive voltage. Drive circuit. 9. The counter electrode driving means divides a brightness range corresponding to a voltage applied to the liquid crystal into two or more regions, and a counter electrode driving voltage supplied to each counter electrode is supplied in accordance with the brightness region. 9. The drive circuit for a liquid crystal display device according to claim 1, wherein the drive circuit is changed. 10. A driving method of a liquid crystal display device comprising a plurality of pixel portions for controlling liquid crystal by an electric field generated between a pixel electrode and a counter electrode, wherein input display data is pixel electrode drive data, It is divided into counter electrode drive data, the pixel electrode drive data is supplied to the pixel electrode, the counter electrode drive data is supplied to the counter electrode, and an electric field generated between the pixel electrode and the liquid crystal counter electrode is used. A method for driving a liquid crystal display device, which comprises driving a liquid crystal.