JPH09102023A - Information recording medium and communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the clock of several to ten and several MHz from the carrier of communication within the law regulation of a weak radio wave and to operate a microprocessor. SOLUTION: A parallel tuning circuit 301 receives MF two-phase modulation signal. A clock generation circuit constituted by a full wave rectifying circuit 103 which full-wave-rectifies the received two phase modulation signal, a binarization circuit 115 binarizing the output of the full wave rectifying circuit, a phase comparison circuit 116 connected to the binarization means, a low pass filter 117 connected to the phase comparison means, a voltage control oscillator 18 oscillating the clock based on the output voltage of the low pass filter and a frequency-dividing circuit 119 which frequency-divides the output clock of the voltage control oscillator by N generates the continuous clock pulse of an HF band frequency, which is phase-synchronized with the carrier of a reception signal and which is N-times. Then, the microprocessor 121 operates by the clock pulse generate by the clock pulse generation means 307.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable data storage medium having a wireless communication function.

[0002]

2. Description of the Related Art In recent years, a batteryless wireless card has been developed as a portable data storage medium having a wireless communication function.
It is starting to be put to practical use. These wireless cards have built-in hard logic and non-volatile memory,
Generally, a small amount of low-speed intermittent communication is performed.

In order to realize high functionality, high speed processing, security enhancement, etc. of this batteryless wireless card, it is desired to mount a microprocessor in the wireless card. In this case, As a clock of the microprocessor, a clock of several MHz to several HMz is desired.

In the case of a conventional batteryless wireless card, several tens of K
Although the clock and power supply for internal operation are generated from the received carrier wave of Hz to several 100 KHz, several tens of KHz to several 10 KHz
Number of MH required for CPU from 0 KHz received carrier wave
It was difficult to obtain a clock of z to tens of HMz.

Further, in the case of the conventional batteryless wireless card, since the clock for internal operation is generated from the carrier wave of intermittent communication, it is impossible to obtain the continuous clock required for the CPU. Therefore, there is a problem that the microprocessor cannot be mounted in the batteryless wireless card.

[0006]

As described above, the present invention operates a microprocessor by obtaining a continuous clock of several MHz to several HMz from a received carrier wave in a data storage medium having a wireless communication function. It is what

[0007]

In order to solve the above problems, the present invention provides a receiving means for receiving a medium wave two-phase modulation signal and a carrier wave of the receiving signal based on the carrier wave of the receiving signal of the receiving means. According to the present invention, there is provided an information storage medium comprising means for generating phase-synchronized continuous clock pulses having a frequency of a short-wave band of N times and a microprocessor operated by the clock pulse generated by the clock pulse generating means. In the above, the microprocessor is operated by generating continuous clock pulses having a short-wave band frequency of N times that is phase-locked with the carrier wave of the received signal.

The present invention further comprises a frequency dividing means for dividing the clock pulse generated by the clock pulse generating means by N.
The information storage medium is provided with means for demodulating the two-phase phase-modulated signal received by the receiving means on the basis of the N-divided clock pulse generated by the frequency dividing means. In the present invention, the generated clock pulse is generated. Is divided by N, and the two-phase modulation signal received by the receiving means is demodulated based on this N divided clock pulse.

Further, according to the present invention, the frequency dividing means for dividing the clock pulse generated by the clock pulse generating means by 2N and the 2N divided clock pulse divided by 2N by the frequency dividing means are subjected to the medium wave two-phase phase. The information storage medium is provided with a transmitting means for transmitting data as a carrier of a modulated signal. The present invention divides the generated clock pulse by 2N,
The 2N-divided clock pulse divided by 2N is used as a carrier wave of the medium wave two-phase phase modulation signal to transmit data.

Furthermore, in the present invention, the clock pulse generating means is full-wave rectifying means for performing full-wave rectification of the received two-phase phase modulated signal, and binarization for binarizing the output of this full-wave rectifying circuit. A circuit, a phase comparison circuit connected to the binarization means, a low-pass filter connected to the phase comparison means, a voltage-controlled oscillator that generates a clock based on the output voltage of the low-pass filter, and the voltage-controlled oscillator. And a frequency dividing circuit for frequency-dividing the output clock of N. The phase comparing means divides the phase of the output clock only when one of the rising edge and the falling edge of the binarized output pulse output from the binarizing means is present. A phase comparison is performed with the output pulse of the frequency circuit, and the phase comparison output is supplied to the voltage controlled oscillator through a low pass filter so that the phase comparison output signal is transmitted to the carrier wave of the two-phase modulated wave signal. Synchronized, it is obtained so as to generate the continuous clock N multiplying.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a configuration of a wireless card system using a wireless card as a data storage medium of the present invention.

As shown in FIG. 2, this wireless cart system comprises a wireless card reader / writer 200 as a data processing device and a wireless card 300 as a data storage medium having a portable wireless communication function. ing.

The wireless card reader / writer 200 is for performing reading and writing commands to the wireless card 300, processing read data, transmitting write data, and the like. A credit driver 203, a transmitting antenna 201, a receiving antenna 202, a receiving amplifier 205, a demodulation circuit 206, an operating unit 209 display unit 208 such as a keyboard, and a power supply unit 210 mainly including a battery for supplying power to each unit. , And an interface 211 connected to an external device (not shown).

The wireless card 300 decodes commands from the wireless card reader / writer 200, writes data, transmits data, and the like. As will be described later, it includes a loop-shaped antenna coil as a transmission / reception antenna and a tuning capacitor. Parallel tuning circuit (reception means) 301, power supply generation section (power supply generation means) 302, demodulation section (demodulation means) 3
03, a modulator (modulator) 304, a controller 305, a nonvolatile memory 306 including an EEPROM or the like as a memory, and a clock generator (clock generator) 3.
07 and the like.

Next, the wireless card reader / writer 200
The operation of the wireless card 300 will be described. First, reading of data from the wireless card 300 will be described. Control unit 20 of wireless card reader / writer 200
A read command is generated at 7 and sent to the modulator 204.
The modulation unit 204 modulates the command with an arbitrary modulation method,
Send to the sending driver 203. The driver 203 amplifies the modulated signal to an intensity sufficient to radiate the modulated signal, and the amplified signal is supplied to the transmitting antenna 201.

The signal supplied to the transmitting antenna 201 is radiated into space, and the parallel tuning circuit 301 of the wireless card 300.
Received at. The received signal is demodulated by the demodulation unit 303,
It is sent to the control unit 305, where command analysis is performed. As a result, when the content of the command is decoded as read, the control unit 305 reads predetermined data from the non-volatile memory 306 in which the card data is stored and sends it to the modulation unit 304. The modulator 304 modulates the card data and supplies it to the parallel tuning circuit 301.

The signal supplied to the parallel tuning circuit 301 is radiated into space and is received by the receiving antenna 202 of the wireless card reader / writer 200. The received signal is sent to the receiving amplifier 205, and the amplifier 205 amplifies the received signal and then sends it to the demodulation unit 206, where it is demodulated. The demodulated signal is sent to the control unit 207, where predetermined data processing is performed.

If necessary, data can be displayed on the display unit 208 and data can be input on the operation unit 209. Next, writing of data to the wireless card will be described. The control unit 207 of the wireless card reader / writer 200 generates a write command and write data and supplies the write command and write data to the modulation unit 204. The modulation unit 204 modulates a command and data by an arbitrary modulation method, and the transmission driver 2
Send to 03. The driver 203 amplifies the modulated signal to an intensity sufficient to radiate the modulated signal, and the amplified signal is supplied to the transmitting antenna 201.

The signal supplied to the transmitting antenna 201 is radiated into space, and the parallel tuning circuit 301 of the wireless card 300.
Received at. The received signal is demodulated by the demodulation unit 303,
It is sent to the control unit 305, where command analysis is performed. As a result, when the content of the command is decrypted, the control unit 305 writes the write data sent after the write command to a predetermined address of the non-volatile memory 306.

The power generation unit 302 of the wireless card 300 is
A power supply required in the wireless card is generated based on a signal received by the parallel tuning circuit 301. Further, the clock generation unit 307 in the wireless card 300 generates a clock necessary for the operation of each unit according to the signal received by the parallel tuning circuit 301, and the clock is the demodulation unit 3.
03, modulator 304, and controller 305 (each circuit described later).

Next, referring to FIGS. 1 to 4, the wireless card 3 will be described.
The internal configuration and operation of 00 will be described. FIG. 1 is FIG.
3 shows an internal configuration of the wireless card 300 of the present invention shown in FIG.

Parallel tuning circuit 301 of wireless card 300
Is a loop antenna coil 1 as a transmitting / receiving antenna
01 and the tuning capacitor 102, the transmitting antenna 201 of the wireless card reader / writer 200.
It receives the two-phase phase-modulated wave signal (frequency f0) from the device and also transmits the two-phase phase-modulated wave signal with the carrier frequency of f0 / 2 by the driver described later. Carrier frequency f0 of the received two-phase modulated wave signal in order to efficiently secure the
Is configured to tune in.

The power supply generation unit 302 includes the parallel tuning circuit 3
The two-phase phase modulated wave signal from the wireless card 30
A full-wave rectification circuit 103 for generating a power supply for supplying the entire circuit within 0, and full-wave rectifying the two-phase phase-modulated wave signal from the parallel tuning circuit 301. A smoothing stabilization circuit 111 that smoothes the full-wave rectified output using a smoothing capacitor, and a voltage monitoring circuit 112 that monitors the voltage of the generated power output from the smoothing stabilization circuit 111.

Two full-wave rectifier circuits, a first full-wave rectifier circuit 104 and a second full-wave rectifier circuit 105, are provided in the full-wave rectifier circuit 103. The output of 104 is supplied to the smoothing and stabilizing circuit 111.

From the transmitting antenna 201 of the wireless card reader / writer 200, the medium frequency, for example, the carrier frequency f 0 =
When data is transmitted by a two-phase modulation signal at 200 KHz, the voltage across the antenna coil as an induced voltage has a waveform as shown by b in FIG. 3 at both ends of the loop antenna coil 101 of the wireless card 200 as an information storage medium. can get.

The induced voltage b is full-wave rectified by the first full-wave rectifier circuit 104 in the full-wave rectifier circuit 110 to form a waveform shown by a chain line in FIG. It is input to 111 and smoothed to obtain a stabilized DC voltage having a waveform c shown in FIG. 3, and this DC voltage c is supplied to each circuit section in the wireless card 100.

The power generation here is performed as long as the two-phase modulation signal is received, and a predetermined power supply voltage can be obtained. The voltage monitoring circuit 112 monitors the DC voltage c and outputs “1” when the voltage (2.7 V) at which each circuit in the wireless card 300 can be sufficiently operated, and outputs “1”. "0" is output when the voltage becomes lower than the voltage at which the operation of each circuit cannot be performed sufficiently.

The demodulation section 303 includes the parallel tuning circuit 301.
Demodulates the two-phase phase modulated wave signal received by
It is composed of a binarization circuit 113 and a demodulation circuit 114. The binarization circuit 113 is the parallel tuning circuit 301.
Is a circuit that binarizes the received binary phase-modulated wave signal, and the output of the binarization circuit 113 is supplied to the demodulation circuit 114.

The demodulation circuit 114 demodulates the output of the binarization circuit 113 by performing synchronous detection with the clock pulse obtained by the clock generation unit 307 described later and the output of the binarization circuit 113.

Next, the clock generation unit 307 causes the second full-wave rectifier circuit 10 of the full-wave rectifier circuit 103 as shown in FIG.
The binarization circuit 115, the phase comparison circuit 116, the low pass filter 117, and the low pass filter 1 that binarize the output of
The voltage controlled oscillator 118 that oscillates a clock according to the output voltage of 17 and the output clock of the voltage controlled oscillator 118
It is composed of a frequency divider 119 that divides the frequency and a frequency divider 120 that divides the output clock of the frequency divider 119 into two and four.

Along with the output voltage d of the second full-wave rectification circuit 105 of the full-wave rectification circuit 103 shown in FIG. 3, the slice level voltage o of the full-wave rectification output voltage d shown by the dotted line in FIG.
Is input to the binarization circuit 115, and binarization is performed by the binarization circuit 115 to obtain a full-wave rectification binarization output C.

In this binarized output C, the carrier frequency of the received two-phase modulation signal is f0 = 200 KHz,
A pulse of C = 2 × 200 KHz = 400 KHz is obtained. However, as shown in FIG. 3, since the transmission of the limited frequency band is performed at the transition between the phases of the information bits “1” and “0” of the two-phase phase modulation signal, all of these are transmitted. The pulse having the wave rectified binary output C = 400 KHz is missing.

The full-wave rectification binarized output C of the binarization circuit 115 is supplied to the PLL circuit. That is, a PLL (phase locked loop) circuit is composed of a phase comparator 116, a low-pass filter 117, and a voltage-controlled oscillator 118 that controls the oscillation frequency by the output voltage of the low-pass filter 117, and the full-wave of the binarization circuit 115. The rectified binary output C = 400 KHz is used as a reference input pulse of the phase comparator 116, and the output of the voltage controlled oscillator 118 is phase-divided by the frequency dividing circuit 119 by 10 at the rising edge of the binary output C. A comparison is made and this phase comparator 11
The output of 6 is supplied to the voltage controlled oscillator 118 via the low-pass filter 117, thereby forming a PLL circuit.

The PLL circuit constitutes a phase locked loop, and as a result, the full-wave rectified binary output C = 400.
Voltage controlled oscillator 118 phase-locked to a kHz pulse
Output pulse e = 10 × 400 KHz = 4 MHz is obtained.

Here, as described above, the full-wave rectification binary output C is partially missing, and a configuration example of the phase comparison circuit 116 suitable for the pulse which is partially missing. Is shown in FIG. 4, and the operation waveforms of each part of the phase comparison circuit 116 are shown in FIG.

The phase comparator 116 has the full-wave rectification binarized output C = 400 KH of the binarization circuit 115 as described above.
z is the reference input pulse of the phase comparator 116,
The output e of the voltage controlled oscillator 118 is phase-compared with the output f divided by 10 by the frequency dividing circuit 119.
As shown in FIG. 4, flip-flops 401, 402,
403, a NAND circuit 404, an AND circuit 405, and a charge pump circuit 505.

In the flip-flop 401, the full-wave rectification binarized output C is connected to the CK terminal, and the output of the smoothing and stabilizing circuit 111 is connected to the D terminal. As shown in FIG. It is set by the rise of the digitized output C, and the Q output becomes "1".

In the flip-flop 402, the output of the flip-flop 401 is connected to the D terminal, and the output of the voltage-controlled oscillator 118 is connected to the CK terminal by the frequency dividing circuit 119.
The divided output f is connected.

Therefore, as shown in FIG. 5, the flip-flop 401 is set, and the Q output becomes "1". Then, the divided output f rises, so that the flip-flop 402 is set and the Q output becomes "1". become.

Further, the Q output of the flip-flop 402 is inverted by the inverter 407, and
Since it is connected to the reset terminal of No. 1, the flip-flop 401 is reset by the rise of the Q output of the flip-flop 402 as shown in FIG.

Further, as shown in FIG. 5, the flip-flop 402 is turned on by the rise of the divided output f after the flip-flop 401 is reset.
Q output of 1 is set and Q of flip-flop 402
The output becomes "0".

The flip-flop 403 is set with respect to the Q output of the flip-flop 402 at the falling edge of the frequency-divided output f, so that the output is a half cycle of the frequency-divided output f.

The NAND circuit 404 is a flip-flop 4.
A NAND (g) of the Q output of 01 and the inverted output of the flip-flop 402 is output, and this output is supplied to the charge pump circuit 406.

The AND circuit 405 also outputs the AND (h) of the Q output of the flip-flop 402 and the inverted output of the flip-flop 403, and this output is supplied to the charge pump circuit 406.

In the charge pump circuit 406, when the output of the NAND circuit 405 is "0", the current flows in the i direction of FIG. 4, and when the output of the AND circuit 405 is "1", the current is Since it flows in the j direction in FIG. 4, the output of the phase comparison circuit 106 has a waveform as indicated by k in FIG.

In such a phase comparison circuit 116, when the phase difference between the full-wave rectification binarized output C and the frequency-divided 10 output d is large, the output of the NAND circuit 405 is turned on for a long time, The interval of the high potential of the output k becomes large. On the contrary, when the phase difference between the full-wave rectification binarized output C and the divide-by-10 output d is small, the time during which the output of the NAND circuit 405 is turned on becomes short, and the width of the high potential of the output k becomes small. Get smaller.

On the other hand, the output of the AND circuit 405 becomes constant depending on the pulse interval of the 10-divided output d regardless of the phase shift between the full-wave rectified binary output C and the 10-divided output d. In the phase comparison circuit 116 described above, the phase comparison is performed only when the rising edge of the pulse of the full-wave rectified binarized output C exists, so that stable operation can be performed.

The output k of the phase comparison circuit 116 is supplied to the low-pass filter 117 as shown in FIG. 1, and the low-pass filter 117 holds a predetermined voltage based on the output k of the phase comparator 116.

That is, when the interval of the high potential and the interval of the low potential of the output k of the phase comparator 116 are the same (the phase of the full-wave rectification binarized output C and the frequency-divided output 10 are the same), The output voltage of the low pass filter 117 is kept constant.
Further, the interval of the high potential of the output k of the phase comparator 116 is larger than the interval of the low potential (1 is larger than the full-wave rectification binary output C.
When the phase of the 0-divided output d is delayed), the output voltage of the low-pass filter 117 rises and the voltage-controlled oscillator 11
8 will oscillate a higher frequency clock.

With such a configuration of the phase-locked loop circuit, as shown in FIG. 3, even if the transition portion of the phase of the information bit is missing, it can be generated as a continuous pulse. Output pulse e
By inputting = 4 MHz as the clock of the microprocessor 121 described later, high-speed processing and high-performance processing can be performed.

Frequency division output of frequency division circuit 119 f = 400
The KHz pulse is input to the frequency divider 120, and the frequency divider 12
The frequency is divided by 2 by 0 and supplied to the demodulation circuit 114. Since the phase of the pulse of this frequency-divided output m = 200 KHz is synchronized with the carrier frequency f0 of the received two-phase modulation signal f = 200 KHz, the demodulation circuit 114 synchronizes with the output of the binarization circuit 113 of the two-phase modulation signal. By performing detection,
Can demodulate.

The frequency divider 120 frequency-divides the 10-frequency-divided output d = 400 KHz pulse of the frequency-dividing circuit 119 into four, and divides this 4-frequency-divided output n = 100 KHz pulse into two phases from the radio card 100. It can be used as the carrier frequency of the phase modulation signal.

Transmission can be performed by placing the antenna coil 101 in a heavy frame through the driver 104. The series of operations described above can continue to generate power as long as it continues to receive the two-phase modulation signal. It generates the multiplied clock that is phase-synchronized with the received carrier wave and uses it as the clock for the microprocessor. Can be processed.

The control unit 305 is the microprocessor 12
1, a ROM (RAM) 122, a serial / parallel conversion circuit 123, and a serial / parallel conversion circuit 124. The received signal demodulated by the demodulation circuit 114 is converted into a parallel signal by the serial / parallel conversion circuit 123. , To the microprocessor 121.

The microprocessor 121 operates on the basis of the 4 MHz clock output from the voltage controlled oscillator 118, analyzes the received command based on the program stored in the ROM 122, and EEP as a storage means.
Data is read from the non-volatile memory 106 including a ROM and data is written to the non-volatile memory 106.

When transmitting, the data read from the non-volatile memory 106 is converted into serial data by the serial / parallel conversion circuit 124. Note that the microprocessor 121 uses the voltage monitoring circuit 112 described above.
When “1” is supplied as the monitoring output of (the voltage (2.7) which can sufficiently operate each circuit in the wireless card 300.
V)), the system is cleared and the system enters the operating state, and when "0" is supplied (when the voltage of each circuit in the wireless card 300 is below the voltage at which the operation cannot be performed sufficiently). Clears the system and stops the operation.

The above-mentioned modulation section (modulation means) 304 is composed of a modulation circuit 125 and a driver 126, and the modulation circuit 125 converts the transmission data converted into serial data by the serial-parallel conversion circuit 124 into the frequency divider 12 described above.
A pulse having a frequency division ratio of 0 divided by 4 (g = 100 KHz) is used as a carrier frequency of the two-phase phase modulation signal and is modulated by a predetermined modulation method.
Supply to

Then, the signal supplied to the parallel tuning circuit 301 is radiated into space, and the wireless card reader / writer 2
00 reception antenna 202 is received. Under the legal regulation of weak radio waves that does not require a radio license, the mid-wave band of several 100 KHz is more advantageous than the short-wave band of several MHz in wirelessly transmitting predetermined power.

That is, when the wavelength of the power source is λ, the electric field intensity at the point of λ / 2π is regulated in accordance with the legal regulation, and the electric field intensity is reduced by 1/3 of the distance. The longer, ie the lower the power transmission frequency, the more advantageous.

As described above, in the above-described embodiment of the present invention, when the batteryless radio card generates power from the received two-phase modulation signal, the radio communication is performed in the medium wave band, which is advantageous for power transmission. Then, a short-wave frequency clock was generated to enable high-speed processing in the card.

That is, the phase is synchronized with the carrier frequency of the two-phase modulation signal, the missing portion is also generated as a continuous wave, and the generated continuous wave is multiplied by n to be used as the clock of the built-in microprocessor. Since this is done, the microprocessor can operate at high speed, and at the same time, it becomes possible to transmit the two-phase modulation signal. In addition, since the microprocessor can be built in the batteryless wireless card, it is possible to enhance functionality and enhance high-speed processing security.

[0062]

As described above, according to the present invention,
Within the legal regulation of weak power supply, several MHz to 1 from the carrier wave of communication
It is possible to obtain a clock of 0 to several HMz, and it is possible to incorporate a microprocessor into an information storage medium and operate it.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a wireless card 300.

FIG. 2 is a block diagram showing a schematic configuration of a wireless card system.

FIG. 3 is a waveform diagram for explaining an operation in the wireless card 300.

FIG. 4 is a circuit diagram showing a configuration of a phase comparison circuit.

FIG. 5 is a waveform diagram for explaining the operation of the phase comparison circuit.

[Explanation of symbols]

 200 wireless card / reader / writer 300 wireless card 301 parallel tuning circuit 302 power supply generation unit 305 control unit 306 non-volatile memory 307 clock generation unit 103 full-wave rectification circuit 115 binarization circuit 116 phase comparison circuit 117 low-pass filter 118 voltage-controlled oscillator 119 divider circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location G06K 17/00 G06F 1/00 330E H04B 7/26 H04B 7/26 E

Claims (10)

[Claims] 1. A receiving means for receiving a medium-wave two-phase modulation signal, and a continuous clock pulse of N-multiplied shortwave band frequency which is phase-locked with the carrier wave of the received signal on the basis of the carrier wave of the received signal of the receiving means. An information storage medium characterized by having a means for performing and a microprocessor operated by the clock pulse generated by the clock pulse generating means. 2. The information storage medium according to claim 1, wherein the clock pulse generated by said clock pulse generating means is divided by N, and the N divided clock generated by this dividing means. An information storage medium having demodulation means for demodulating a two-phase modulation signal received by the reception means based on a pulse. 3. The information storage medium according to claim 1, wherein the clock pulse generated by the clock pulse generating means is divided by 2N, and the dividing means divides by 2N to divide by 2N. An information storage medium, comprising: a transmission unit that transmits data by using a clock pulse as a carrier wave of a medium-wave two-phase modulation signal. 4. The information storage medium according to claim 1, wherein the clock pulse generation means is a full-wave rectification means for performing full-wave rectification of the received two-phase phase modulation signal, and the full-wave rectification means. A binarization circuit for binarizing the output of the circuit, a phase comparison circuit connected to this binarization means, a low-pass filter connected to this phase comparison means, and a clock based on the output voltage of this low-pass filter. It is composed of a voltage-controlled oscillator to be generated and a frequency dividing circuit for dividing the output clock of the voltage-controlled oscillator by N, and the phase comparison means has the rising or falling edge of the binarized output pulse outputted from the binarizing means. Only when one of the edges is present, a phase comparison is performed with the output pulse of the frequency dividing circuit, and the phase comparison output is supplied to the voltage controlled oscillator through a low pass filter. An information storage medium, which generates a N-multiplied continuous clock that is phase-synchronized with a carrier of the two-phase modulated wave signal. 5. Receiving means for receiving a first medium-wave modulated signal, power generation means for rectifying the first medium-wave modulated signal received by the receiving means to generate power, and the receiving means. Means for generating, based on the carrier wave of the first medium-wave modulated signal received in step S1, a continuous clock pulse having a N-multiplied short-wave band frequency in phase with the carrier wave of the first medium-wave modulated signal; An information storage medium, comprising: a microprocessor that operates by the clock pulse generated in 1 .; and a transmitting unit that transmits by a second medium-wave modulated signal. 6. Receiving means for receiving a medium-wave two-phase modulation signal, and generating a continuous clock pulse of N-multiplied short-wave band frequency phase-locked with the carrier wave of the received signal on the basis of the carrier wave of the received signal of the receiving means. Means, a microprocessor operated by the clock pulse generated by the clock pulse generating means, a frequency dividing means for dividing the clock pulse generated by the clock pulse generating means by N, and the frequency dividing means. Demodulation means for demodulating the two-phase phase-modulated signal received by the receiving means based on the generated N-divided clock pulse; and dividing means for dividing the clock pulse generated by the clock pulse generation means by 2N. Transmitting means for transmitting data as a carrier wave of a medium-wave two-phase phase modulation signal using a 2N-divided clock pulse divided by 2N by the dividing means. Information storage medium characterized by having. 7. A medium-wave two-phase phase-modulated signal is received, and based on the received carrier wave of the received signal, a continuous clock pulse of N-multiplied shortwave band frequency that is phase-locked with the carrier wave of the received signal is generated, and this generation is performed. A communication method characterized in that a microprocessor is operated by the generated clock pulse. 8. A medium-wave two-phase phase-modulated signal is received, and based on the received carrier wave of the received signal, a continuous clock pulse of N-multiplied short-wave band frequency that is phase-locked with the carrier wave of the received signal is generated, and this generation is performed. The communication is characterized by operating a microprocessor by the generated clock pulse, dividing the generated clock pulse by N, and demodulating the received two-phase modulation signal based on the N divided clock pulse. Method. 9. A medium-wave two-phase phase-modulated signal is received, and a continuous clock pulse having a frequency of N times the shortwave band, which is phase-locked with the carrier of the received signal, is generated based on the received carrier of the received signal. The microprocessor operates by the generated clock pulse, divides the generated clock pulse by 2N, and transmits the data by using the 2N-divided 2N-divided clock pulse as the carrier wave of the medium-wave two-phase phase modulation signal. A communication method characterized by the above. 10. A first medium-wave modulated signal is received, the received first medium-wave modulated signal is rectified to generate a power supply, and the power is generated based on a carrier wave of the received first medium-wave modulated signal. Generate a continuous clock pulse of N-multiplied shortwave band frequency that is phase-synchronized with the carrier of the first medium-wave modulated signal, operate the microprocessor with this generated clock pulse, and transmit with the second medium-wave modulated signal. A communication method characterized by performing.