JPH0897712A - Pll circuit - Google Patents

Abstract

PURPOSE: To allow the circuit to cope with lots of oscillated frequencies by providing only one kind each of integrated circuit and reference oscillator by providing a write control circuit whose content is revised with a signal from an external terminal to a nonvolatile memory used to set a frequency division ratio of the PLL circuit. CONSTITUTION: An output of a reference oscillator 51 is given to an oscillator 53, which generates a reference oscillating frequency. The reference oscillating frequency is frequency-divided by a 1st frequency divider 54 to be a comparison use reference oscillating frequency. Furthermore, an output of a variable frequency oscillator 64 is frequency-divided by a 2nd frequency divider 56 and the phase of the resulting signal is compared with the phase of an output of the 1st frequency divider 54 at a phase comparator 57. The setting value of the frequency division ratio of the 2nd frequency divider 56 is stored in a rewritable nonvolatile memory 60 and the setting value of the frequency division ratio of the 2nd frequency divider 56 is stored in the rewritable nonvolatile memory 60 via a write control circuit 61 from an external terminal 62 in a product assembly process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit used in an oscillator circuit of mobile communication equipment and the like.

[0002]

2. Description of the Related Art In recent years, mobile communication fields utilizing radio waves such as mobile phones, cordless phones, remote controllers, and data transmission have been expanding. Among them, M which switches many frequencies
There are a CA type system and a system in which a single frequency is sufficient. Among them, the latter PLL circuit relating to the field of use of a single frequency will be described.

As shown in FIG. 4, a conventional PLL circuit has 1
In one integrated circuit 13, the input terminal 2 of the reference oscillator 1, the oscillator 3 connected to this input terminal 2, the first frequency divider 4 connected to the output of this oscillator 3, and the variable frequency oscillator 12 Input terminal 5 to which output is supplied, and this input terminal 5
Of the second frequency divider 6 connected to the phase divider 7 for comparing the output of the second frequency divider 6 with the output of the first frequency divider 4; A charge pump circuit 8 connected to the output, an output terminal 9 to which the output of the charge pump circuit 8 is connected, and a mask memory 10 provided for setting the frequency division ratio of the second frequency divider 6. It was configured with and. Further, the output terminal 9 was connected to the input of the variable frequency oscillator 12 via a low pass filter (hereinafter referred to as LPF) 11.

The operation of the PLL circuit configured as above will be described below. The output of the reference oscillator 1 is input to the oscillator 3 in one integrated circuit 13 to generate a reference oscillation frequency, which is divided by the first frequency divider 4 to become the reference oscillation frequency for comparison. The output of the variable frequency oscillator 12 is frequency-divided by the second frequency divider 6, and the first frequency divider 4
And the phase comparator 7 performs phase comparison. This output is direct current (hereinafter referred to as DC) by the charge pump circuit 8.
Converted to voltage. And this DC voltage is output terminal 9
To the variable frequency oscillator 12 through the LPF 11 to form a PLL circuit. Here, the second frequency divider 6
The set value of the frequency division ratio is set in the mask memory 10 and is fixed.

The oscillation frequency of the variable frequency oscillator 12 is determined as in (Equation 1).

[0006]

[Equation 1]

In another PLL circuit, as shown in FIG. 5, the input terminal 22 of the reference oscillator 21 and the oscillator 23 connected to the input terminal 22 are provided in one integrated circuit 31.
The input terminal 24 to which the output of the variable frequency oscillator 30 is supplied
And a frequency divider 25 connected to the input terminal 24, a phase comparator 26 for comparing the output of the frequency divider 25 with the output of the oscillator 23, and a phase comparator 26 connected to the output of the phase comparator 26. It has a charge pump circuit 27 and an output terminal 28 to which the output of the charge pump circuit 27 is connected. The output of the output terminal 28 was connected to the input of the variable frequency oscillator 30 via the LPF 29.

The operation of the PLL circuit configured as above will be described below. The output of the reference oscillator 21 is connected to the oscillator 23 to generate a reference oscillation frequency, which becomes the comparison reference oscillation frequency. In addition, the variable frequency oscillator 30
The output of is divided by the frequency divider 25, and the phase is compared with the output of the oscillator 23 by the phase comparator 26. Then, the output is converted into a DC voltage by the charge pump circuit 27, and is supplied from the output terminal 28 to the input of the variable frequency oscillator 30 through the LPF 29. Here, the frequency divider 25 has a fixed frequency division ratio.

The oscillation frequency of the variable frequency oscillator 30 is determined as in (Equation 2).

[0010]

[Equation 2]

[0011]

However, in such a conventional configuration, the oscillation frequency of the variable frequency oscillator 12 or 30 by the PLL circuit is fixed. To change this frequency: That is, in the example of FIG. 4, it is necessary to change the mask memory 10 that sets the frequency division ratio of the second frequency divider 6 of the PLL circuit. This means that it is necessary to prepare as many integrated circuits 13 as the required number of oscillation frequencies. Moreover, in the example of FIG. 5, the frequency of the reference oscillator 21 must be changed. Therefore, the number of types of reference oscillators 21 is required as many as the required oscillation frequencies. That is, each time the specification is changed, the integrated circuit 13 is newly started,
Alternatively, there is a problem that the reference oscillator 21 must be separately prepared.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a PLL circuit which can cope with a large number of oscillation frequencies if only one type of integrated circuit or reference oscillator is prepared. It is a thing.

[0013]

To achieve this object, the memory for setting the frequency division ratio of the PLL circuit of the present invention is a writable non-volatile memory, and the memory is provided with a signal from an external terminal. A write control circuit capable of changing the contents of the memory is provided.

[0014]

With this structure, the write control circuit can set the contents of the nonvolatile memory to meet the new specifications. That is, since the frequency division ratio written in the nonvolatile memory can be arbitrarily set by the user using the write control circuit, even if the oscillation frequency of the variable frequency oscillator is changed, the nonvolatile memory If only one type of integrated circuit and one type of reference oscillator are prepared by simply changing the frequency division ratio to be written in, a PLL circuit that can handle a large number of oscillation frequencies can be obtained.

[0015]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a PLL circuit according to an embodiment of the present invention. In FIG. 1, the PLL circuit of the present invention includes an input terminal 52 of a reference oscillator 51 in one integrated circuit 65,
The oscillator 53 connected to the input terminal 52, the first frequency divider 54 connected to the output of the oscillator 53, the input terminal 55 to which the output of the variable frequency oscillator 64 is supplied, and the input terminal 55 The connected second frequency divider 56, a phase comparator 57 for comparing the phase of the output of the second frequency divider 56 and the phase of the output of the first frequency divider 54, and this phase comparator 57. Of the charge pump circuit 58, an output terminal 59 to which the output of the charge pump circuit 58 is connected, a non-volatile memory 60 connected to the second frequency divider 56, and the non-volatile memory. A write control circuit 61 connected to 60 and an external terminal 62 connected to the write control circuit 61.

The operation of the PLL circuit configured as above will be described below. The output of the reference oscillator 51 is connected to the oscillator 53 to generate a reference oscillation frequency.
This reference oscillation frequency is divided by the first frequency divider 54 to become the comparison reference oscillation frequency. The output of the variable frequency oscillator 64 is frequency-divided by the second frequency divider 56, and the phase of the output of the first frequency divider 54 is compared by the phase comparator 57. This output is DC by the charge pump circuit 58.
It is converted into a voltage and output from the output terminal 59. The signal from the output terminal 59 is an LP provided outside the integrated circuit 65.
It is input to the variable frequency oscillator 64 through F63 and the PLL
It constitutes the circuit.

The set value of the dividing ratio of the second divider 56 is stored in the rewritable nonvolatile memory 60, and the set value of the dividing ratio of the second divider 56 is the product. Is written in the non-volatile memory 60 from the external terminal 62 through the write control circuit 61 in the step of incorporating as.
If the non-volatile memory 60 is, for example, a fuse type memory, the manufacturing cost of the integrated circuit 65 and the writing circuit in the above process can be facilitated.

In FIG. 1, the second frequency divider 56 is shown as a block that divides the frequency by M, but it may be a pulse swallow frequency divider. In this case, it is known in various documents that the input frequency characteristic of the second frequency divider 56 can be improved.

The oscillation frequency of the variable frequency oscillator 64 is determined as in (Equation 3).

[0021]

[Equation 3]

With the above configuration, even when the oscillation frequency fosc of the variable frequency oscillator 64 needs to be changed, the setting value of the frequency division ratio written in the non-volatile memory 60 is changed so that it can be written in the process. Therefore, even if the frequency of the variable frequency oscillator 64 is changed, another PLL integrated circuit 65 is provided for each oscillation frequency fosc.
The reference oscillator 51 does not have to be prepared. Further, since the PLL circuit included in the integrated circuit 65 and the reference oscillator 51 can be used as a common component, the management cost can be reduced.

Although the nonvolatile memory 60 is of the fuse type, a general write circuit can be used if an electrically writable memory is used.

If the non-volatile memory 60 is a erasable type, the oscillation frequency f due to a sudden change in specifications of the product
It is possible to change osc even after the product is assembled.

Further, if a memory is also provided in the first frequency divider 54 and the frequency division ratio of the first frequency divider 54 is set, the oscillation frequency interval of the variable frequency oscillator 64 can be set arbitrarily. That is, since the step frequency of the variable frequency oscillator 64 can be arbitrarily set, it is possible to improve spurious interference and stabilization time when the power of the PLL circuit is turned on by changing the reference frequency for comparison.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a PL in the second embodiment of the present invention.
It is an L circuit. In FIG. 2, the PLL circuit of the present invention is
The input terminal 72 of the reference oscillator 71 is provided in one integrated circuit 87.
An oscillator 73 connected to the input terminal 72, a first frequency divider 74 connected to the output of the oscillator 73, and an input terminal 75 to which the output of the variable frequency oscillator 86 is supplied.
And a second frequency divider 76 connected to this input terminal 75
The output of the second frequency divider 76 and the first frequency divider 7
4 and a charge pump circuit 7 connected to the output of the phase comparator 77.
8, an output terminal 79 to which the output of the charge pump circuit 78 is connected, a non-volatile memory 80 connected to the second frequency divider 76, and a write control circuit 81 connected to the non-volatile memory 80. And this write control circuit 8
1 and a plurality of data write terminals 8 connected to the switching circuit 84, respectively.
2 and a selection terminal 83. The switching circuit 84 is also connected to the frequency division ratio setting terminal of the second frequency divider 76. That is, the difference from the configuration of FIG. 1 is that one of the data write terminals 82 is the selection terminal 83,
The switching terminal 84 is configured to switch the connection destination of the data writing terminal 82 by the selection terminal 83.

The operation of the PLL circuit configured as above will be described below. The output of the reference oscillator 71 is connected to the oscillator 73 to generate a reference oscillation frequency, which is input to the first frequency divider 74 and divided to become the comparison reference oscillation frequency. The output of the variable frequency oscillator 86 is frequency-divided by the second frequency divider 76, and the output of the first frequency divider 74 is phase-compared by the phase comparator 77. Then, it is converted into a DC voltage by the charge pump circuit 78 and output from the output terminal 79. The signal output from the output terminal 79 passes through the LPF 85 and is input to the variable frequency oscillator 86 to form a PLL circuit.

The setting of the frequency division ratio of the second frequency divider 76 is stored in the rewritable non-volatile memory 80, and this content is written in the step of being incorporated as a product.
At this time, one of the data write terminals 82 is connected to the selection terminal 8
Depending on the voltage level of the selection terminal 83, whether the data writing terminal 82 is a data writing terminal for writing to the nonvolatile memory 80 or whether it is connected to an arbitrary bit of the second frequency divider 76 is selected. Switching circuit 84
It is configured to be selected by.

With the above configuration, if the voltage level of the selection terminal 83 is written to the non-volatile memory 80 when the voltage level is "H" level, the data write terminal 82 is switched when the voltage level is "L" level. It is possible to directly connect to any bit of the second frequency divider 76, for example, the lower bit. In this case, the frequency division ratio of the second frequency divider 76 can be set by the voltage level applied to the data write terminal 82 without changing the content written to the nonvolatile memory 80. That is, the oscillation frequency can be changed very easily by cutting or short-circuiting the pattern of the printed circuit board on which the integrated circuit 87 is mounted. Further, if the data write terminal 82 is connected to a switch provided on the product, the oscillation frequency f can be obtained even when the product is used.
It is possible to change osc. Therefore, it is possible to reduce interference due to the same frequency. Although the data write terminal 82 at the “L” level is connected to the lower bit of the second frequency divider 76, it may be connected to an intermediate bit. In this case, for example, when a bidirectional communication device is configured, if the level of the data write terminal 82 is switched between transmission and reception, and the oscillation frequency fosc at reception is shifted by the intermediate frequency of the receiver to oscillate, the transmitter and The local oscillator of the receiver can be shared, and the cost can be reduced and the size can be reduced.

As for the level of the selection terminal 83, the "H" level is used for data writing, but when the level is "L",
Data may be written. In this case, the selection terminal 83 is connected to the power supply (“H” level) with a resistor or the like on the circuit (which can be incorporated in the integrated circuit 87), and the selection terminal 83 is shorted to the “L” level with a jig or the like during writing. By doing so, the writing state can be selected, and the process equipment can be simplified. Further, as in the first embodiment, a memory is also provided in the first frequency divider 74, and a part of the write terminal 82 is connected to the bit of the first frequency divider 74, whereby the frequency step can be changed. It will be easier.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows the PL in the third embodiment of the present invention.
It is an L circuit. In FIG. 3, the PLL circuit of the present invention is
The input terminal 9 of the reference oscillator 91 is included in one integrated circuit 105.
2, an oscillator 93 connected to the input terminal 92, a first frequency divider 94 connected to the output of the oscillator 93,
The input terminal 103 of the variable frequency oscillator 104, the variable frequency oscillator 104 connected to the input terminal 103, the first output terminal 106 to which the output of the variable frequency oscillator 104 is supplied, and the output of the variable frequency oscillator 104. A second frequency divider 95 connected to the second frequency divider 95 and the second frequency divider 95.
Is compared with the output of the first frequency divider 94, the charge pump circuit 97 connected to the output of the phase comparator 96, and the output of the charge pump circuit 97. Connected second output terminal 98 and non-volatile memory 99 connected to the second frequency divider 95.
And a write control circuit 100 connected to the nonvolatile memory 99, and an external terminal 101 connected to the write control circuit 100. That is, FIG.
The difference from the above configuration is that the variable frequency oscillator 104 is built in the integrated circuit 105.

The operation of the PLL circuit configured as above will be described below. The output of the reference oscillator 91 is connected to the oscillator 93 to generate a reference oscillation frequency, which is divided by the first frequency divider 94 to become the comparison reference oscillation frequency. Further, the frequency generated by the variable frequency oscillator 104 is divided by the second frequency divider 95, and the first frequency divider 9
4 and the phase comparator 96 performs phase comparison. Then, the output is converted into a DC voltage by the charge pump circuit 97 and output from the second output terminal 98. The output of the second output terminal 98 passes through the LPF 102 provided outside the integrated circuit 105, and again via the input terminal 103 provided in the integrated circuit 105, and then the variable frequency oscillator 104.
To form a PLL circuit. The setting of the frequency division ratio of the second frequency divider 95 is stored in the rewritable nonvolatile memory 99, and the content thereof is written in the process.

With the above configuration, a plurality of frequencies can be generated by the built-in variable frequency oscillator 104 by one integrated circuit 105 according to the preset value of the second frequency divider 95. Therefore, the integrated circuit 105 allows the local oscillator to be configured with a small number of parts, and thus the cost and the size can be reduced.

The selection terminal shown in the second embodiment can be introduced. Moreover, by incorporating a buffer amplifier and a power amplifier as needed, it can be used for a PLL circuit for transmission.

[0037]

As described above, according to the present invention, the memory for setting the division ratio is a writable non-volatile memory, and the content of the memory can be changed by a signal from an external terminal. The configuration is such that a write control circuit is provided. Therefore, with this configuration, the write control circuit can set the content of the non-volatile memory to meet the new specifications. That is, since the frequency division ratio written in the nonvolatile memory can be arbitrarily set by the user using the write control circuit, even if the oscillation frequency of the variable frequency oscillator is changed, the nonvolatile memory A PLL circuit capable of coping with a large number of oscillation frequencies can be obtained by preparing only one type of integrated circuit and one type of reference oscillator simply by changing the frequency division ratio to be written in.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a PLL circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a PLL circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional PLL circuit.

FIG. 5 is another block diagram of a conventional PLL circuit.

[Explanation of symbols]

 51 Reference Oscillator 52 Input Terminal 53 Oscillator 54 First Frequency Divider 55 Input Terminal 56 Second Frequency Divider 57 Phase Comparator 58 Charge Pump Circuit 59 Output Terminal 60 Nonvolatile Memory 61 Write Control Circuit 62 External Terminal 64 Variable Frequency Oscillator 65 Integrated circuit

Claims (3)

[Claims] 1. An integrated circuit comprises an input terminal of a reference oscillator, an oscillator connected to the input terminal, a first divider connected to the output of the oscillator, and an output of a variable frequency oscillator. A supplied input terminal, a second frequency divider connected to the input terminal, and a phase comparator for comparing the output of the second frequency divider and the output of the first frequency divider, A charge pump circuit connected to the output of the phase comparator, an output terminal connected to the output of the charge pump circuit, and a memory provided to set the frequency division ratio of the second frequency divider. The memory is a writable non-volatile memory, and this memory is provided with a write control circuit whose content can be changed by a signal from an external terminal.
LL circuit. 2. The external terminal comprises a plurality of terminals for writing data and a selection terminal, and the selection terminal connects the terminal for writing the data to a write control circuit or a second frequency divider. Item 2. The PLL circuit according to item 1. 3. An input terminal of a reference oscillator, an oscillator connected to the input terminal, a first frequency divider connected to the output of the oscillator, and an input terminal of the variable frequency oscillator in one integrated circuit. A variable frequency oscillator connected to the input terminal, and a first output to which the output of the variable frequency oscillator is supplied.
A second frequency divider connected to the output terminal of the variable frequency oscillator, the output of the second frequency divider and the first frequency divider.
A phase comparator for comparing with the output of the frequency divider, a charge pump circuit connected to the output of the phase comparator, a second output terminal connected to the output of the charge pump circuit, and the second And a memory provided to set the frequency division ratio of the frequency divider of the above, wherein the memory is a writable non-volatile memory, and the content of which is changeable by a signal from an external terminal A PLL circuit provided with a control circuit.