JPH0895898A - Direct memory access device and data transfer device - Google Patents

Abstract

PURPOSE: To provide a direct memory access device which can be widely used and is expandable and can reduce the overhead of data transfer and a data transfer device equipped with the direct memory access device. CONSTITUTION: As for a DMAC 250 which calculates the addresses of the acquisition destination and transfer destination of data to be transferred by sequentially executing an instruction string stored in an instruction memory 201, a decoder 202 outputs a standby period and branch conditions specified by a standby and branch instruction to a standby counter 208 and a condition decision part 209 when the decoder 202 decodes the standby and branch instruction. The standby counter 208 counts the standby period and the condition decision part 29 decides the branch conditions. A program counter 205 performs branching to a branch destination address stored in a branch address part 210 when the branch conditions are established during the standby period, and counts the address of an instruction following the standby and branch instruction when it is not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is preferably provided in, for example, a parallel computer system in which a plurality of processor elements share and process a user program, and a processor that executes the user program (hereinafter, simply referred to as a processor). The present invention relates to a direct memory access device that directly transfers data without the control of the above) and a data transfer device including the direct memory access device.

[0002]

2. Description of the Related Art In recent years, the processing speed of a single processor has been dramatically improved. However, in the entire system including the processor, the data transfer speed between the processors and the communication speed with the external device are slower than the processing speed of the processor. it dose not connect. Therefore, in order to improve the performance of the entire system, it is necessary to improve the communication performance and functions with the memory and external devices.
However, it is difficult to improve the performance of this part as compared with the processor alone, and many studies are currently being made.

FIG. 9 is a block diagram showing a schematic configuration of a conventional parallel computer system. This parallel computer system includes a plurality of processor elements (hereinafter abbreviated as PE) 901 (1) to 901 connected to a network 930.
(N). PE901 (1) to PE901
Since (n) is equivalent, only PE901 (1) will be described.

The PE 901 (1) is a processor 910,
A memory 911, a local bus 912 and a data transfer device 913 are provided. A processor 910, a memory 911,
The data transfer devices 913 mutually transfer data via the local bus 912. For example, PE901 (1)
Array operations such as PE901 (2), 901 (3),
..., 901 (n) are shared and calculated. Therefore, when the calculation results of the other PEs 901 (2), 901 (3), ..., 901 (n) are required, the network 93 described later is used.
Transfer data to each other via 0. Processor 910
According to the program in the memory 911.
The arithmetic processing is executed on the data.

FIG. 10 shows PE901 (1) to PE901.
It is a block diagram which shows the structure of the network 930 which transmits the data between (n). Network 930 is PE
It transfers data mutually transferred between 901 (1) to PE901 (n). Specifically, the network 930 is
Buffers F11 to Fnn configured by a FIFO (First In First Out) memory are arranged in a grid and connect PE901 (1) to PE901 (n) to each other.

The data transfer device 913 sends data to be transferred to another PE 901 through the network 930.
(2), ..., 901 (n), and other PE9
01 (2), ..., 901 (n) to the network 930
The data is received through and stored in the memory 911. Specifically, at the time of data transmission, the data is transferred from the memory 911 to any of the buffers F11 to F1n, and at the time of data reception, the data is transferred from any of the buffers F11 to Fn1 to the memory 911.

In the parallel computer system as described above, since the frequency of data transfer is high, efficient data transfer is required. Therefore, a DM that transfers data between the external device and the memory 911 without going through the processor 910.
A (direct memory access) is known. In this case, a separate DMAC (Direct Memory Access Device) is required. DMAC is a local bus 912
HOLD request signal for monopolizing the bus, a bus control signal for controlling writing / reading (R / W) to / from the memory 911,
It creates addresses for data acquisition and transfer. The DMAC is generally realized by dedicated hardware, but in this case, the expandability of the DMAC is low, and it is difficult to flexibly deal with the specification change of the parallel computer system. Therefore, mass production cannot be expected and it is difficult to reduce the cost. Therefore, it is considered to configure a programmable DMAC using a general-purpose microprocessor.

Generally, the address calculation is performed by the following processing procedure. The instruction sequence shown below is written in a high-level language (Fortran) and is not an instruction sequence that is actually executed by a microprocessor, but the algorithm is the same, so it is illustrated. for i = 0, ii for j = 0, jj address = BA + OFS * i + j where BA is the base address, OFS is the offset,
ii and jj indicate the count range of the counter. Here, the offset is a predetermined value for jumping to a different address area.

"For i = 0, ii" means that the following instruction is repeated while incrementing the value of i from "0" to "ii". Also, "for j =
0, jj "means that the following instruction is repeated while counting up the value of j from" 0 "to" jj ". “Address = BA + OFS * i + j” is a value obtained by multiplying the base address by the offset by the value i.
This means that the address is obtained by adding the value of j.

In this way, "address = BA + O"
One address is calculated each time the FS * i + j ″ instruction is repeatedly executed. For example, BA = 1000, ii.
= 4, jj = 3, OFS = 100, address = 1
000,1001,1002,1003,1100,1
101, 1102, 1103, 1200, 1201, ...
Are sequentially calculated. Thus, in the address generation in the DMAC, the iterative process is performed with high frequency.

Further, the DMAC is provided with the buffers F11 to Fnn except when the interrupt processing is performed by the data reception signals from the buffers F11 to Fnn on the network 930.
The addresses nn are sequentially generated, and the presence or absence of data in the buffers F11 to Fnn designated by the addresses is searched. If there is data to be transferred in the searched buffers F11 to Fnn, a transfer destination address is generated. To transfer. If there is no data to be transferred, it is necessary to generate the addresses of the other buffers F11 to Fnn and search for the presence or absence of data in the buffers F11 to Fnn designated by the addresses. This corresponds to the branch processing in the instruction string execution.

FIG. 11 is a diagram showing an instruction sequence of the microprocessor. FIG. 11A shows an instruction string for branch processing, and FIG. 11B shows an instruction string for iterative processing. In each of these, the left is a static instruction sequence written as a program, and the right is a dynamic instruction sequence indicating the execution order. At the time of branching shown in FIG. 11A, the branch instruction is "B.
"BEQ L1" means jump to L1 if the condition is satisfied, and execute the next instruction without skipping if the condition is not satisfied. Condition determination is before the BEQ instruction, that is, the result of the SUB instruction. Determined by where:
If the result of the SUB instruction is not "0", the condition is not satisfied, and the subsequent AND instruction is executed next. If the result of the SUB instruction is "0", the condition is satisfied, and the next branch destination OR
Execute an instruction.

At the time of repetition shown in FIG.
The cc instruction controls the repeat loop. "DBcc
D1 L1 ″ executes D1-1, and if the result is “0” or more, branches to L1. D1 is the stored contents of the data register. D1-1 means that “1” is subtracted from the storage content of D1, and the subtraction result is stored in D1. In order to perform the repetitive processing a desired number of times, "the desired number of repeated times minus one" is stored in D1 in advance, and the label L1 is attached to the beginning of the loop. Here, L1 is attached to the AND instruction, and “2” is stored in D1. As a result, as shown in the right part of FIG. 11B, the three instructions of the AND instruction, the OR instruction, and the DBcc instruction can be repeated three times.

[0014]

However, when the address generation for the direct memory access is performed by the dedicated microprocessor for executing the above-mentioned instruction sequence, the address generation operation is performed by a predetermined instruction sequence. Actions that cannot be described cannot be performed. That is, conditional branching and repetitive processing can be performed only by the instruction sequence shown in the example of the conventional microprocessor.

For example, in the case where the processor as described above waits for a certain period of time and if it is desired to perform a process of branching at that time when a condition is satisfied during the waiting period, the process shown in FIG. SUB instruction and BEQ shown in a)
You will program a sequence of instructions that repeats the instructions. However, in the branch instruction, the condition is only determined at one time point when the SUB instruction is executed. Even if the condition is satisfied between the SUB instruction and the next SUB instruction, the next SUB instruction is executed. It cannot move to a branch until it is executed. Data transfer devices often handle data sent asynchronously. In this case, the data transfer device needs to wait for the data to be acquired to be stored in the acquisition destination. However, in the above-described standby operation, the overhead occurs between the satisfaction of the condition and the execution of the next SUB instruction. However, there is a problem that the data transfer efficiency is deteriorated. Therefore, the data transfer device requires conditional branching different from the conventional one.

Further, in a direct memory access device used especially in a parallel computer, since the frequency of repetitive processing in address calculation is high, it is necessary to perform this repetitive processing in a short time. For example, in the case of repeating the process using the DBcc instruction shown in FIG.
As shown on the right side of FIG. 11B, DBc
The c instruction is executed. Therefore, it is desirable that the DBcc instruction be executed in the shortest possible time. In contrast,
Since the DBcc instruction includes two processes, an operation of D1-1 and a determination of whether D1 is “0” or more, the DBcc instruction requires a longer execution time than other simple operation instructions. To do. Therefore, if the repetitive processing is performed by such a program, there is a problem that an overhead is generated for each repetitive processing.

In view of the above problems, it is an object of the present invention to provide a programmable direct memory access device and a data transfer device which are excellent in versatility and expandability and can reduce the overhead associated with data transfer. To do.

[0018]

In order to achieve the above object, a direct memory access device of the present invention according to claim 1 reads an instruction memory for storing a transfer program and one instruction from the instruction memory for decoding. When a predetermined branch instruction is decoded, the execution includes a decoder that outputs a waiting period determined by the branch instruction, a branch condition, and a branch destination, and an execution unit that executes the instruction decoded by the decoder. When the branch condition is satisfied during the waiting period, the instructions are sequentially executed from the branch destination instruction in the instruction memory, and when the branch condition is not satisfied during the waiting period, the branch is executed after the waiting period ends. From the instruction after the instruction,
It is characterized by executing an instruction.

According to another aspect of the present invention, there is provided a direct memory access device according to the present invention, wherein an instruction memory for storing a transfer program and one instruction from the instruction memory are read and decoded, and a predetermined repeated instruction is decoded. , A decoder that outputs the number of repetitions and the number of instructions determined by the repeated instruction, an execution unit that executes the instruction decoded by the decoder, and the number of executed instructions up to the number of instructions determined by the repeated instruction An instruction number counter for sequentially pointing to an instruction in the instruction memory, and an instruction fetch unit for pointing to the decoder the instruction to be read next based on the count of the instruction number counter when the repetitive instruction is being executed; The count end count of the number counter is counted up to the repeat count specified by the repeat command. The instruction fetch unit indicates the instruction next to the repetitive instruction each time the count of the instruction counter ends, and when the count of the number counter ends, a predetermined number of instructions following the repetitive instruction. Characterized by pointing to the next instruction in the sequence.

Further, in the direct memory access device according to the present invention as defined in claim 3, when the instruction memory for storing the transfer program and one instruction from the instruction memory are read and decoded, and a predetermined branch instruction is decoded, , When the waiting period determined by the branch instruction, the branch condition, and the branch destination are output and the predetermined repeat instruction is decoded,
A decoder that outputs the number of repetitions and the number of instructions, an execution unit that executes the instructions decoded by the decoder, an instruction number counter that counts the number of executed instructions up to the number of instructions designated by the repeated instruction, and an instruction memory The instruction to be read next to the decoder based on the branch condition when the branch instruction is executed and based on the count of the instruction number counter when the repeat instruction is executed. The instruction fetch unit includes a pointing instruction fetch unit and a count counter that counts the count end count of the instruction count counter up to the repeat count designated by a repeat instruction, and the instruction fetch unit includes a waiting period when the branch instruction is being executed. If a branch condition is met, the instruction is sequentially pointed to from the instruction at the branch destination in the instruction memory, and the instruction waits. If the branch condition is not satisfied during the interval, after the waiting period ends, the instruction is sequentially pointed to from the instruction next to the branch instruction, and when the repeat instruction is being executed, the instruction is counted every time the instruction counter counts. It is characterized in that it points to the instruction next to the repeat instruction, and at the end of counting of the number of times counter, points to the next instruction of a predetermined number of instruction sequences following the repeat instruction.

Further, in the direct memory access device according to the present invention as defined in claim 4, the execution part according to claim 1, claim 2 or claim 3 is a register, a calculation part for performing address calculation, and the calculation part. And a timing counter that counts the number of addresses calculated by and outputs a timing signal for each predetermined count number.

Further, in the data transfer apparatus of the present invention according to claim 5, the data input via the first port, the second port, the third port, and the third port. A first buffer for temporarily storing data, a second buffer for temporarily storing data input through the second port, and an address in a memory in which data to be transferred is stored to generate the first buffer. Data from the address via the port of No. 3, stored in the first buffer, and an address in the memory where the data stored in the second buffer is to be written is generated, and the third port is generated. A third direct memory access device for outputting a control signal to write data to the address in the memory via, and generating an address of a device storing data to be transferred. A second direct memory access device for reading data from the device via the second port and outputting a control signal to store the data in the second buffer; and data stored in the first buffer. A first direct memory access device for generating an address of a buffer to be written and outputting a control signal to write data to the buffer via the first port, the first, second and third The direct memory access device is the direct memory access device according to claim 1, claim 2, claim 3, or claim 4.

[0023]

According to the present invention, in the direct memory access device according to claim 1, the decoder reads and decodes the transfer program stored in the instruction memory one by one, and the execution unit is Execute the decoded instruction. Further, when the decoder decodes a predetermined branch instruction, it outputs the waiting period, branch condition, and branch destination determined by the branch instruction, and the execution unit stores in the instruction memory when the branch condition is satisfied during the waiting period. The instructions are sequentially executed from the branch destination instruction, and when the branch condition is not satisfied during the waiting period, the instructions are sequentially executed from the instruction next to the branch instruction after the waiting period ends.

Therefore, for example, up to immediately before the branch instruction in the instruction memory, an instruction string for calculating the address of one device is stored, whereby the execution unit receives the address of the acquisition destination of the data to be transferred. To calculate. Also,
The branch condition is that "there is data to be transferred in the device specified by the address calculated immediately before". Further, immediately after the branch instruction, an instruction sequence for calculating the address of another device is stored, and an instruction sequence for calculating the address of the data transfer destination is stored at the branch destination. As a result, “When you look at the presence / absence of data in one device, if there is no data in that device, you wait for the arrival of data for a predetermined time, and if the data arrives during the waiting time, read that data. Then, it is transferred to the transfer destination, and if not, go to see if there is data in another device. "

According to the present invention, in the direct memory access device according to the second aspect, when the decoder decodes the predetermined repeat instruction, the decoder outputs the repeat count and the instruction number defined by the repeat instruction. . The instruction number counter counts the number of executed instructions up to the number of instructions determined by the repetitive instruction. The count counter counts the count end count of the instruction count counter up to the repeat count designated by the repeat command. The instruction fetch unit points to an instruction next to the repetitive instruction each time the count of the instruction counter ends, and points to a next instruction of a predetermined number of instruction sequences following the repetitive instruction when the count of the number of times counter ends. The execution unit executes the instruction decoded by the decoder according to the instruction of the instruction fetch unit.

As described above, the instruction counter counts the number of executed instructions up to the number of instructions to be repeatedly executed,
Since the number counter counts the count end number of the instruction number counter up to the number of repetitions, the direct memory access device only executes the predetermined repeating instruction once, and the execution unit does not count the number of instructions and the number of repetitions. A predetermined number of instructions can be repeatedly executed a predetermined number of times. Therefore, the overhead in the repetitive processing of the direct memory access device is reduced, and the address calculation and data transfer operation can be performed with high efficiency.

Further, according to the present invention, in the direct memory access device according to claim 3, the decoder is
When the transfer program stored in the instruction memory is read and decoded one by one, and a predetermined branch instruction is decoded, a waiting period determined by the branch instruction,
The branch condition and branch destination are output, and when the predetermined repeat instruction is decoded, the number of repeats and the number of instructions are output. The execution unit executes the instruction decoded by the decoder.

The instruction fetch unit indicates the instruction to be read next by the decoder. The instruction fetch unit indicates the instruction to be read next by the decoder based on the branch condition when the branch instruction is executed and based on the count of the instruction number counter when the repeat instruction is executed. In other cases, the instructions in the instruction memory are sequentially pointed.

The instruction number counter counts the number of executed instructions up to the number of instructions designated by the repeat instruction. The count counter counts the count end count of the instruction count counter up to the repeat count designated by the repeat command. When the branch instruction is being executed, the instruction fetch unit sequentially points to instructions from the branch destination instruction in the instruction memory when the branch condition is satisfied during the standby period, and the branch condition is satisfied during the standby period. If not, after the waiting period ends, instructions are sequentially pointed to from the instruction next to the branch instruction. When the repeat instruction is being executed, the instruction next to the repeat instruction is indicated each time the count of the instruction counter ends, and when the count of the number of times counter ends, a predetermined number of instruction sequences following the repeat instruction Points to the next instruction.

As a result, the direct memory access device can individually perform the branch operation of the direct memory access device according to claim 1 and the repetitive operation of the direct memory access device according to claim 2, and perform each operation. It can be performed in combination. Further, according to the invention, in the execution unit according to claim 1, claim 2 or claim 3 of the direct memory access device according to claim 4, the calculation unit performs address calculation using a register. The timing counter counts the number of addresses calculated by the calculation unit and outputs a timing signal for each predetermined count number. As a result, according to the present invention, the processor for processing the user program conventionally counts the number of data transfers of the direct memory access device to synchronize the direct memory access device in the parallel computer system. Since the timing counter counts the number of addresses calculated by the calculation unit, the load on the processor can be reduced and the effective efficiency of the processor can be improved.

Furthermore, according to the present invention, claim 5
In the described data transfer device, the first buffer temporarily stores the data input via the third port. The second buffer temporarily stores the data input via the second port. The third direct memory access device generates an address in the memory where the data to be transferred is stored. At the same time, the control signal is output to read the data from the address via the third port and store the data in the first buffer. The third direct memory access device is the second direct memory access device.
Generates an address in memory to write the data stored in the buffer. At the same time, a control signal is output via the third port to write data to the address in the memory. The second direct memory access device generates the address of the device in which the data to be transferred is stored. At the same time, a control signal is output to read data from the device via the second port and store the data in the second buffer. The first direct memory access device generates an address of a buffer in which the data stored in the first buffer should be written. At the same time, a control signal is output via the first port to write data in the buffer.

The above-mentioned first, second and third direct memory access devices are claimed in claim 1, claim 2 and claim 3.
Alternatively, since it is the direct memory access device according to claim 4, the data transfer device performs the data transfer operation based on the control of the direct memory access device according to claim 1, claim 2, claim 3, or claim 4. be able to.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a direct memory access device (hereinafter referred to as a DMAC) 250 of a first embodiment of the present invention will be described with reference to FIGS. Figure 1
1 is a block diagram showing a configuration of a data transfer device 150 including a DMAC 250 which is a first embodiment of the present invention. Figure 2
FIG. 3 is a block diagram showing a configuration of a DMAC 250 according to the first embodiment of this invention. The DMAC 110 shown in FIG.
120, 130 and 140 are DMACs 250.

The data transfer device 150 is provided in the parallel computer system in place of the data transfer device 913 shown in FIG. The data transfer device 150 uses the DMAC 11
0, 120, 130, 140, ports 101, 102,
103, external address bus 104, external data bus 10
5, the internal bus 106, the data buffers 151 and 152, the selector 161, and the like.

The data buffers 151 and 152 are the PE 9
Data to be transferred between 01, specifically, coordinates, pressure,
Sequence data, which is physical data such as stress, velocity, and temperature,
Control information, image information, audio information, etc. are temporarily stored. External data bus 105 and external address bus 10
Reference numeral 4 denotes a local bus 912 in FIG. 9, and a processor 910 and a memory 911 in the PE 901 including the data transfer device 150 are connected to the external data bus 105 and the external address bus 104. The data transfer device 150 starts data transfer in response to a data transfer request from each processor 910 and an external device.

The DMAC 110 controls the reception of the port 101, the DMAC 120 controls the transmission of the port 102, and the DMA.
The C 130 controls transmission of the port 103, and the DMAC 140 controls reception of the port 103. DMAC110, 1
20 generates addresses of the buffers F11 to Fnn which are external devices. The address here is the buffer F11.
~ Fnn device address, i.e. which buffer F11-F
Indicates whether to select nn. In addition, the DMACs 130, 14
0 generates the address of the memory 911.

In addition, each DMAC 110, 120, 13
Reference numerals 0 and 140 generate a bus control signal for reading and writing, and a timing notification signal for synchronously operating each DMAC. First, the initial setting will be described. Instruction memory 111, 121, 131, 141, data memory 11 via external data bus 105 and internal bus 106
Data is stored in 4, 124, 134, and 144. This is realized by the processor 910 directly writing to each instruction memory and each data memory.

Next, from the port 103 to the data buffer 15
The transfer to No. 2 will be described.

The DMAC 140 generates the address of the storage area in the memory 911 in which the data to be transferred is stored, sends it to the address line 174, and sends it to the external address bus 104 via the selector 161. At the same time, a bus control signal for instructing reading is transmitted. DMAC14
0 reads the data to be transferred from the memory 911 at the address and stores it in the data buffer 152 via the external data bus 105.

Next, the DMAC 120 is a transfer destination buffer F.
The device addresses 11 to F1n are generated and transmitted to the address line 172, and at the same time, the bus control signal for instructing writing is transmitted. The device address is the buffer F1.
1 to F1n, one of the buffers F11 to F1
n is selected. The DMAC 120 simultaneously transfers the data to be transferred from the data buffer 152 to the data line 182.
Send to. As a result, the transmitted data is stored in the selected buffers F11 to F1n.

Next, the transfer from the port 1010 to the port 103 will be described.

The DMAC 110 generates device addresses of the buffers F11 to Fn1 in which data to be transferred is stored and sends them to the address line 171, and also sends a bus control signal for instructing reading. The device address is sent to the buffers F11 to Fn1 and one of the buffers F11 to Fn1 is selected. At the same time, the data to be transferred from the selected buffers F11 to Fn1 is read to the data line 181, and stored in the data buffer 151.

Next, the DMAC 130 generates an address of a storage area in which the data in the memory 911 is to be written, sends it to the address line 173, sends it to the external address bus 104 via the selector 161, and a bus for instructing writing. Send a control signal. At the same time, the data to be transferred is sent to the external data bus 105, and the memory 91
Write to 1.

As shown in FIG. 2, the DMAC 250 is composed of an instruction memory 201, a decoder 202, an execution unit 203, a data memory 204, a program counter 205, a branch control unit 230 and the like. Furthermore, the branch control unit 23
0 is composed of a gate 207, a standby counter 208, a condition determination unit 209, a branch address unit 210, and the like.

The instruction memory 201 stores an arithmetic instruction sequence for address generation. The decoder 202 starts the instruction memory 201 from the address indicated by the program counter 205.
The instructions in the above are read and decoded, and then instructions are given to the execution unit 203. Further, the decoder 202 includes the instruction memory 20.
When the instruction read from 1 is the standby & branch instruction, the stop instruction signal is sent to the stop instruction line 216 to suspend the program counter 205.

The execution unit 203 is controlled by the decoder 202. The execution unit 203 executes an operation while exchanging data with the data memory 204, and generates an address, a bus control signal, and a timing notification signal. Execution unit 20
Each time 3 sends out a set of address and bus control signals, one piece of data is transferred to the data transfer device 150 and the memory 91.
1 or data transfer device 150 and buffer F11
To Fnn. The address calculated by the execution unit 203 is sent to the address line 232, the bus control signal is sent to the bus control line 233, and the timing notification signal is sent to the timing notification line 234.

The data memory 204 has a base address,
Stores the count number and offset of the counter. The program counter 205 counts the address of the instruction to be read next. The gate 207 sends the logical product of the counting signal and the condition satisfaction signal to the branch instruction line 223 as a branch instruction signal.

The standby counter 208 counts down the standby time every predetermined time, for example, every one instruction cycle. The standby counter 208 activates the counting signal until the waiting time times out, and sends it to the counting line 215. The standby counter 208 is reset by the condition satisfaction signal from the condition satisfaction line 222.

The condition determination unit 209 determines whether or not the branch condition signal input via the plurality of branch condition lines 231 satisfies the condition. When the branch condition signal satisfies the condition, the condition determination signal is output. It is activated and sent to the condition establishment line 222. The branch condition line 231 is connected to, for example, the buffers F11 to Fnn, the data buffers 151 and 152, the external address bus 104, the external data bus 105, etc., and the presence or absence of data in the buffers F11 to Fnn or the data buffers 151 and 152 and The overflow state is shown, and the use states of the external address bus 104 and the external data bus 105 are shown. Condition determination unit 20
9 indicates, for example, buffers F11 to Fnn of the data acquisition destination.
If there is no data in, the condition is not satisfied, and the condition is satisfied when the data arrives.

The branch address unit 210 stores the address of the branch destination in the instruction memory 201 that branches according to the branch instruction. In the above configuration, the DMAC250
Is an instruction fetch, decode,
And a three-stage pipeline operation of instruction execution in the execution unit 203. The pipeline operation is an operation method in which processing is executed in parallel at each stage, and when a result is sent to the next stage, each stage simultaneously moves to the next process.

FIG. 3 is a timing chart showing the operation of the DMAC 250 of the first embodiment. Cycle C in Figure 3
0, C1, C2, ... Show cycles for executing one instruction.
Here, the DMAC 250 follows the wait & branch instruction
It waits for a predetermined time, and if the condition is satisfied within the waiting time, it executes from the instruction at the branch destination, and if not, it executes from the instruction next to the wait & branch instruction. The wait & branch instruction is "wait & bra N L".
Is described and indicates that the process branches to L if the condition is satisfied in N cycles.

The decoder 202 decodes the wait & branch instruction in the cycle C4 and sends the wait count number N, the condition and the branch destination address L to the decoder output line 220. The standby counter 208, the condition determination unit 209, and the branch address unit 210 respectively fetch these in cycle C5. The wait & branch instruction “wait & bra 5 L shown in FIG. 3
1 "indicates that if the condition is satisfied during 5 cycles, the instruction" i "of the branch destination address L1 is executed, otherwise the next instruction" e "is executed, and the wait counter 208 indicates" 5 ". Is set. The condition is satisfied when the branch condition signal is "1".

When the decoder 202 decodes the wait & branch instruction, it issues a stop instruction signal to the program counter 205 to instruct temporary stop. The timing for restarting the count of the program counter 205 follows the count end signal when the condition is not satisfied, and follows the branch instruction signal when the condition is satisfied. The case where the conditions are not satisfied will be described below.

The standby counter 208 is "5", "4", "3", from cycle C5 to cycle C9.
Count down as "2" and "1". During this period, the counting signal is activated and is "1", but since the condition satisfaction signal is still "0", the branch instruction signal which is a logical product is "0". Therefore, no branching operation is performed. In cycle C9, the count end signal becomes "1", and the program counter 205 executes the instruction "e" at the address next to the wait & branch instruction. The instruction sequence executed by the above is "
a ”,“ b ”,“ c ”,“ wait & bra ”,“
e "and" f ".

The case where the conditions are satisfied will be described below.
The standby counter 208 starts counting down from the cycle C5, and the condition satisfaction signal is activated to become "1" in the cycle C6. As a result, the branch instruction signal "1" is transmitted in cycle C6, and the standby counter 208
To reset. In response to the branch instruction signal, the program counter 205 fetches the branch address “L1”,
It is sent to the instruction memory 201. Here, cycle C7
From "L1" branch instruction from "i", "j", "k"
Move to the execution of. The instruction sequence executed by the above is "
a ”,“ b ”,“ c ”,“ wait & bra ”,“
i ”,“ j ”,“ k ”, ...

Whether the condition is satisfied or not satisfied
Immediately after the execution of "t &bra", the subsequent instruction execution is not decoded, and therefore "NOP" (No Operation: No Operation: from the decoder 202 to the execution unit 203 for about two cycles.
Do nothing) is instructed. During this time, the decoder 202 fetches and decodes the next instruction. As described above, according to the present embodiment, “wait for a certain time and branch if a condition is satisfied during that time”, specifically, “when the presence or absence of data in one buffer is checked, If there is no data in, wait for the arrival of data for a predetermined time,
When the data arrives during the waiting time, the data is read and transferred to the transfer destination, and if not, go to see if there is data in another buffer ”.

Next, the execution unit 203 will be described. Figure 4
FIG. 3 is a block diagram showing a configuration of an execution unit 203 of the first embodiment. The execution unit 203 includes a general-purpose register 425, a calculation unit 426, and a timing counter 427. The general-purpose register 425 temporarily stores data used in the calculation by the calculation unit 426. The calculation unit 426 is an arithmetic unit and exchanges data with the general-purpose register 425 and the data memory 204 according to an instruction from the decoder to execute an arithmetic operation and generate an address and a bus control signal. Calculator 4
26 sends an address generation notification signal to the timing counter 427 every time an address is generated. The timing counter 427 counts the number of address generation notification signals and sends the timing notification signal to the timing notification line 234 when it reaches a predetermined value. In this,
Each of the DMACs 110, 120, 130, 140 stops its operation when the timing counter 427 sends out a timing notification signal.

FIG. 5 shows DM in the parallel computer system.
FIG. 6 is a diagram for explaining a synchronous operation of AC 250. FIG. 5A shows the configuration of the parallel computer system. Figure 5
(B) is a timing chart showing the operation of the DMAC 250. Here, in order to simplify the explanation, each PE 9
Each 01 is provided with one DMAC 250.

In the DMAC 250 in each PE 901, the timing counter 427 is used for each calculation unit 4
When 26 generates, for example, 10 addresses, it sends a timing notification signal to the timing notification line 234. Timing notification line 234 from each PE 901
Are connected to the input stage of the gate 501. Gate 501
Takes the logical product of the timing notification signals and sends the stop notification signal to the stop notification line 520. Therefore, the stop notification signal is sent to all DMACs 25 in the parallel computer system.
When 0 stops, it becomes "1". The stop notification line 52
0 is connected to the processor 910 of each PE 901.
When each processor 910 detects the stop notification signal “1”, each processor 910 sets a parameter for instructing the DMAC 250 in the PE 901 to perform the next transfer operation, and the instruction memory 201 and the data memory 204 are required for the next transfer operation. Write the address generation instruction and address data. As a result, the processor 910 can switch the data transfer operation of the data transfer device 150 according to the user program processed by the entire parallel computer system.
Next, each PE 901 sends a stop release signal to the stop release line 530 to restart the transfer operation of each DMAC 250.

As described above, each processor 910 is DM
By programming the AC 250, the data transfer device 150 can evenly buffer the buffer F11 when the communication pattern is random and uniform, such as general numerical simulation.
~ Fnn is searched, and when data is transferred biasedly between PEs 901 having high correlation as in the particle simulation described later, the predetermined buffers F11 to Fnn are searched preferentially to determine whether there is data to be transferred. You can perform the action of examining.

Specifically, in the particle simulation,
The closer the target particle is, the stronger the effect of the particle is, so that the communication pattern between the PEs 901 is biased. In this case, PEs in charge of areas that are considered to have a strong influence on each other.
By prioritizing the reception from 901, the efficiency of data transfer can be improved. More specifically, in the particle simulation, the calculation processing target area is subdivided into blocks, and each PE 901 takes charge of the calculation processing of each block. Here, it is assumed that the PE 901 (n) is in charge of the area n. (Here, n is a natural number.) Further, it is assumed that the regions adjacent to the region 20 are the regions 19, 21, 10, and 30. In such a case, processor 910 (20)
DMAC250 (20) with PE901 (19), PE9
01 (21), PE901 (10), PE901 (3
Address generation instructions are programmed to preferentially receive data from 0). As a result, data can be transferred more efficiently as compared with the case where the buffers F11 to Fnn are sequentially searched.

Further, predetermined buffers F11 to Fnn
In the case of prioritizing reception from the terminal, various priority operations can be programmed. For example, all the buffers F11 to Fnn are sequentially searched, and the waiting time in the buffers F11 to Fnn having a high priority is set to be long. Alternatively, considering the case where the DMAC 250 (1) preferentially searches the buffer F13, F11 → F13 → F12 →
F13 → F13 → F13 → F14 → F13 → F15 → ...
As described above, while the buffers F11 to F1n are sequentially searched, the buffers F11 to Fnn having a higher priority are searched. Thus, the optimum data reception priority operation can be selected according to the user program being executed by the parallel computer system.

Further, as described above, the execution unit 2 of this embodiment
03 counts the address generation signal in the timing counter 427 and sends the timing notification signal, so that it is not necessary for the processor 910 to count the number of data transfers of the DMAC 250 and synchronize the DMAC 250 as in the conventional case. The load can be reduced.

The DMAC 650 according to the second embodiment of the present invention will be described below.
Will be described with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the DMAC 650 according to the second embodiment of the present invention. The data transfer device of this embodiment is the same as the data transfer device 150 shown in FIG.
Reference numerals 130 and 140 are DMACs 650. DMAC6
50 is replaced with the branch control unit 230 of the DMAC 250,
An adder 612 and a repetition control unit 631 are provided. The same reference numerals are given to the same components as those in the first embodiment, and only the adder 612 and the repetition control unit 631 will be described below.

As shown in FIG. 6, the repeat control unit 631
Includes a number counter 613, an instruction number counter 614, and the like. The adder 612 is an arithmetic unit, and after the program counter 205 is stopped by the instruction of the decoder 202, the instruction offset of an instruction number counter 614 described later is multiplied by a predetermined value and the relative address of the instruction to be executed next. Calculate (based on the address of the repeat instruction), add it to the output of the program counter 205, and send it to the instruction memory 201.

The number counter 613 counts the number of repetitions in the repetitive processing. Number counter 613
Counts down by one for each count end signal of the instruction number counter 614. The count counter 613 sends a count end signal “1” to the count end line 622 at the end of counting, and restarts the operation of the program counter 205.

The instruction number counter 614 counts the number of instructions executed in the repetitive processing, and sends a count end signal to the count end line 621 each time the count ends. For example, here, the instruction number counter 614 is
Each time one instruction that is repeatedly processed is executed, it counts down by one from the initial value. Further, the instruction number counter 614 calculates an instruction offset from the count value and sends it to the instruction offset line 625. The instruction offset is the number of instructions from the repeat instruction to the next instruction to be executed. The instruction number counter 614 detects the count end signal of the number counter 613 at the end of counting, resets the count value to the initial value when the count end signal of the number counter 613 is “0”, and continues the countdown. When the count end signal of the number counter 613 is "1", the instruction number counter 614 sends the instruction offset to the instruction offset line 625 and ends the countdown. At this time, the program counter takes in and outputs the output of the adder 612 at this time, and starts counting from the next instruction cycle.

The basic operation of the DMAC 650 constructed as above is the same as that of the first embodiment. Therefore, the iterative controller 631 and the adder 612 are used as the main components of the DMAC 650.
The operation of will be described with reference to FIG. FIG. 7 shows the DM of this embodiment.
6 is a timing chart showing a repeated operation of AC650. In FIG. 7, cycles C0, C1, C2 ... Show the cycles required to execute one process.

Here, the repeat instruction is "loop N
It is described as "M", and indicates that N consecutive instructions are executed M times in succession after the repeat instruction, that is, N * M times in total.
The decoder 202 decodes the repeated instruction in the cycle C3, and determines the number of repetitions and the number of instructions in the decoder output line 220.
Send to. The number counter 613 and the instruction number counter 614 respectively fetch these in cycle C3.

The repeat instruction "loop 2 here"
3 "indicates that the following two instructions are repeated three times. When the decoder 202 decodes the repeated instruction, it sends a stop instruction signal to the stop instruction line 216 and the program counter 2
05 is instructed to pause. The number counter 613 and the instruction number counter 614 each start counting down from cycle C3. Here, the number counter 613 counts down to “3”, “2”, “1”, and the instruction number counter 614 counts down to “2”, “1”.

During this time, the program counter 205 has stopped operating, so the adder 612 sends the output of the program counter 205 plus the instruction offset sent from the instruction number counter 614. Here, "1" and "2" are alternately transmitted as the command offset, whereby the commands "c" and "d" are transferred to the command memory 201.
Are continuously read from.

The number counter 613 is the instruction number counter 61.
It counts down by the count end signal of 4. Figure 7
Then, the cycles are C5, C7, and C9. Finally, in cycle C9, the count end signal of the number counter 613 is transmitted, and the instruction number counter 614 ends the countdown. At this time, the instruction offset is “3”. Also,
The program counter 205 uses the adder 612 at this time.
The output of the instruction is fetched, and the addresses after the instruction "e" are counted from the cycle C10.

When the instruction sequence executed according to the timing chart of FIG. 7 is rewritten, "a", "b", "loo"
p "," c "," d "," c "," d "," c ","
In the conventional example shown in FIG. 11, "DBc" is placed between "c", "d" and "c", "d".
c "is entered. If the instruction sequence of this embodiment is executed by the conventional one," a "," b "," c "," d "," D ".
Bcc "," c "," d "," DBcc "," c ","
d ”,“ DBcc ”,“ e ”, and D for each repetition
The Bcc instruction causes overhead. That is,
In the conventional address calculation by the processor, the address is 1
This causes an overhead for each calculation, which is inconvenient in a direct memory access device that requires high-speed address calculation. In this embodiment, the repetitive instruction is executed only once in the first loop instruction.

Therefore, according to the present embodiment as described above,
The repetitive instruction can be executed with almost no overhead, and the repetitive processing can be preferably performed in the direct memory access device that requires the repetitive processing with high frequency in the address calculation.

Although the conditional branching process is described in the first embodiment and the iterative process is described in the second embodiment, an apparatus having both of them is also possible. I will describe it here. A direct memory access device according to a third embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 shows the DMAC 8 of the third embodiment of the present invention.
It is a block diagram which shows the structure of 50. The data transfer apparatus of this embodiment is the same as the data transfer apparatus 150 shown in FIG. 1, except that the DMACs 110, 120, 130, 140 are DMs.
AC850. The DMAC 850 includes the branch control unit 230 of the first embodiment, the adder 612 of the second embodiment, and the repetition control unit 631 at the same time.

The conditional branching process shown in the first embodiment and the iterative process shown in the second embodiment can be realized by the DMAC 850 and the data transfer device configured as described above. The branch control unit 230 controls branching, and the repetition control unit 631 controls repetition. These are the same as those described in the first and second embodiments.

With the above configuration, the combined operation of the waiting & branching process of the first embodiment and the iterative process of the second embodiment can be performed. It is possible to select a more appropriate transfer operation in response to the generation status of transfer data that differs depending on the processing content of the user program.

[0079]

As described above, according to the present invention as set forth in claim 1, when the branch condition is satisfied during the waiting period, the execution unit sequentially executes the instructions from the branch destination instruction in the instruction memory. When the branch condition is not satisfied during the waiting period, the instructions are sequentially executed from the instruction next to the branch instruction after the waiting period ends.

Therefore, for example, until just before the branch instruction in the instruction memory, an instruction sequence for calculating the address of one device is stored, and the execution unit is thereby provided with the address of the acquisition destination of the data to be transferred. To calculate. Also,
The branch condition is that "there is data to be transferred in the device specified by the address calculated immediately before". Further, immediately after the branch instruction, an instruction sequence for calculating the address of another device is stored, and an instruction sequence for calculating the address of the data transfer destination is stored at the branch destination. This allows the direct memory access device to
"When I checked the presence / absence of data in one device, if there was no data in that device, I waited for the arrival of data for a predetermined time, and if data arrived during the waiting time, read that data and transfer it to the destination. Data transfer operation, otherwise, go to see if there is data in another device. "

Further, the direct memory access device of the present invention controls data transfer based on the transfer program stored in the instruction memory, not limited to the branch instruction described above, so that the environment can be freely set according to the contents of the transfer program. It can be performed and is highly expandable and versatile. For example,
Priority can be given to the transfer order, and the number of transfer destination devices can be freely set.

As described above, according to the present invention, the direct memory access device counts the number of instructions executed by the instruction counter up to the number of instructions to be repeatedly executed, and the number counter counts the number of instructions. Since the count end count of the counter is counted up to the repeat count, the direct memory access device only executes the predetermined repeat instruction once, and the executing unit does not count the number of instructions and the repeat count, but a predetermined number of instructions. Can be repeatedly executed a predetermined number of times. Therefore, the direct memory access device of the present invention can reduce the overhead in the repetitive processing, and consequently can perform the address calculation and the data transfer operation with the effective efficiency.

As described above, according to the present invention as set forth in claim 3, the direct memory access device has the branch operation of the direct memory access device according to claim 1 and the repetitive operation of the direct memory access device according to claim 2. Can be performed individually, and each operation can be performed in combination. As described above, according to the present invention as set forth in claim 4, the processor for processing the user program conventionally counts the number of data transfers of the direct memory access device and synchronizes the direct memory access device in the parallel computer system. The direct memory access device of the present invention,
Since the timing counter counts the number of addresses calculated by the calculation unit, the load on the processor can be reduced and the effective efficiency of the processor can be improved.

As described above, according to the present invention of claim 5, the first, second and third direct memory access devices are any one of claim 1, claim 2, claim 3 or claim 4. Since it is the direct memory access device described in the above, the data transfer device is defined by claim 1, claim 2, or claim 3.
Alternatively, the data transfer operation can be performed under the control of the direct memory access device according to the fourth aspect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer device 150 including a DMAC 250 according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a DMAC 250 according to the first embodiment of this invention.

FIG. 3 is a timing chart showing the operation of the DMAC 250 of the first embodiment.

FIG. 4 is a block diagram showing a configuration of an execution unit 203 of the first embodiment.

FIG. 5 is a diagram for explaining a synchronous operation of the DMAC 250 in the parallel computer system.

FIG. 6 is a block diagram showing a configuration of a DMAC 650 according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining a repeating operation of the DMAC 650 of the second embodiment.

FIG. 8 is a block diagram showing a configuration of a DMAC 850 according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a schematic configuration of a conventional parallel computer system.

FIG. 10 is a block diagram showing a configuration of a network 930 that transmits data between PEs 901 (1) to 901 (n).

FIG. 11 is a diagram showing an instruction sequence of a conventional microprocessor.

[Explanation of symbols]

 201 instruction memory 202 decoder 203 execution unit 204 data memory 205 program counter 207 gate 208 standby counter 209 condition determination unit 210 branch address unit 230 branch control unit

Claims (5)

[Claims] 1. In a parallel computer system in which a plurality of processor elements each including a processor, a memory, and a data transfer device are connected via a network, a memory in a processor element to which the processor element belongs and a plurality of devices on the network. A direct memory access device for use in a data transfer device for transferring data between a plurality of memory devices, comprising an instruction memory for storing a transfer program and one instruction from the instruction memory for decoding and decoding a predetermined branch instruction. Includes a decoder that outputs a waiting period determined by the branch instruction, a branch condition, and a branch destination, and an execution unit that executes the instruction decoded by the decoder. The execution unit satisfies the branch condition during the waiting period. When this is done, the instructions are executed sequentially from the branch destination instruction in the instruction memory, After completion of the waiting period when the branch condition during aircraft period is not satisfied, sequentially from the next instruction of the branch instruction, the direct memory access device and executes the instructions. 2. In a parallel computer system in which a plurality of processor elements each including a processor, a memory, and a data transfer device are connected via a network, a memory in a processor element to which the processor element belongs and a plurality of devices on the network. A direct memory access device for use in a data transfer device for transferring data between a plurality of memory devices, comprising: an instruction memory for storing a transfer program; Is a decoder that outputs the number of repetitions and the number of instructions determined by the repeat instruction, an execution unit that executes the instruction decoded by the decoder, and the number of executed instructions, and the number of instructions determined by the repeat instruction. The instruction counter that counts up to The instruction fetch unit that sequentially points to the instructions in the memory and, when the repeat instruction is executed, points to the decoder the instruction to be read next based on the count of the instruction number counter, and the count end count of the instruction number counter. A count counter that counts up to the number of repetitions indicated by a repeat instruction, wherein the instruction fetch unit indicates the next instruction of the repeat instruction each time the count of the instruction counter ends, and when the count of the count counter ends, A direct memory access device characterized by pointing to the next instruction of a predetermined number of instruction sequences following a repetitive instruction. 3. A parallel computer system in which a plurality of processor elements each including a processor, a memory, and a data transfer device are connected via a network, and a memory in a processor element to which the processor element belongs and a plurality of devices on the network. A direct memory access device for use in a data transfer device for transferring data between a plurality of memory devices, comprising an instruction memory for storing a transfer program and one instruction from the instruction memory for decoding and decoding a predetermined branch instruction. Is a decoder that outputs a waiting period determined by the branch instruction, a branch condition, and a branch destination, and outputs a repeat count and the number of instructions when decoding a predetermined repeat instruction, and an instruction decoded by the decoder. The execution part to be executed and the number of executed instructions An instruction counter that counts up to the instructed number of instructions, and sequentially points to instructions in the instruction memory. Based on a branch condition when the branch instruction is executed, an instruction when the repeat instruction is executed The instruction fetch unit includes an instruction fetch unit that indicates to a decoder the instruction to be read next based on the count of the number counter, and a number counter that counts the count end count of the instruction number counter up to the repeat count designated by the repeat instruction. When the branch instruction is being executed, when the branch condition is satisfied during the waiting period, the section sequentially indicates the instructions from the branch destination instruction in the instruction memory, and the branch condition is not satisfied during the waiting period. After the end of the waiting period, the instructions are sequentially pointed to from the instruction following the branch instruction, and the repeat instruction is executed. When the count of the instruction counter is completed, the instruction next to the repeat instruction is indicated, and at the end of the count of the number of times counter, the instruction next to the predetermined number of instruction sequences following the repeat instruction is indicated. Characteristic direct memory access device. 4. The execution unit according to claim 1, claim 2, or claim 3, which counts a register, a calculation unit that performs address calculation, the number of addresses calculated by the calculation unit, and a predetermined count number. A direct memory access device including a timing counter for outputting a timing signal for each. 5. In a parallel computer system in which a plurality of processor elements each including a processor, a memory, and a data transfer device are connected via a network, a memory in a processor element to which the processor element belongs and a plurality of devices on the network. A data transfer device for transferring data between a first port, a second port, a third port, and a first port for temporarily storing data input via the third port. Buffer, a second buffer for temporarily storing the data input through the second port, and an address in the memory in which the data to be transferred is stored, and the second port through the third port. The data to be read from the address, stored in the first buffer, and the data stored in the second buffer should be written. A third direct memory access device for generating an address in the memory and outputting a control signal to write data to the address in the memory via the third port; and a device storing data to be transferred. A second direct memory access device that generates an address of the device and outputs a control signal to read data from the device via the second port and store the data in the second buffer; A first direct memory access device for generating an address of a buffer to write the stored data and outputting a control signal to write the data to the buffer via the first port; The second and third direct memory access devices are claim 1, claim 2, claim 3 or claim 4.
A data transfer device, which is the direct memory access device described in the above.