JPH0894723A - Memory semiconductor testing device - Google Patents

Abstract

PURPOSE: To obtain a circuit configuration where the capacity in the depth direction of a memory for generating a patten to be used when performing I/O control of pattern data to be applied to a device to be measured in a memory semiconductor testing device. CONSTITUTION: SCRAM 10 which is the scramble memory of address is partially used as the buffer memory of a random pattern for I/O control for generating a pattern EDRE 18. A selector 19 is provided in a programmable data selector 3 to select a patten NDRE 12 which is a conventional I/O control patten and a newly generated pattern EDRE 18. When testing a logic part 15, the selector 19 selects the pattern EDRE 18, the pattern EDRE 18 is interrupted into the I/O control line, and the pattern is applied to a driver 4, thus testing the logic part 15 of a device to be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention shows the structure of a random pattern generation circuit for controlling I / O of pattern data applied to a memory device to be measured in a memory semiconductor test apparatus.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a random pattern generating circuit for I / O controlling the pattern data applied to a memory device to be measured according to the prior art. In the write mode of the memory device to be measured, the pattern PAT17 applied to the memory device to be measured 5 is the pattern PAT D8 generated from the data buffer memory 1.
Data is selected for each channel by the programmable data selector 3 via the algorithmic pattern generator 2, input to the driver 4, and applied to the memory device 5 to be measured. The I / O control of the driver 4 is performed by the I / O control signal generator 1 of the algorithmic pattern generator 2.
1 I / O control pattern NDRE12 generated from 1 through pattern data DRE1
3 is output and then input to the driver 4.

When the output of the device under test 5 is read, the pattern P generated from the data buffer memory 1
ATD8 goes through the algorithmic pattern generator 2,
The programmable data selector 3 selects an expected value EXP 14 for each channel, inputs it to the logical comparison section 6, inputs the output of the device under test 5 to a comparator, and performs logical comparison to determine Pass / Fail 20. The control of the logical comparison is performed by the pattern PC for enabling / disabling the logical comparison for each channel generated from the data buffer memory 1 and applied to the logical comparison unit 6.
Performed by PE7.

When the logic section 15 of the device under test 5 is tested, as shown in the timing chart of FIG. 4, at the time of Write Cycle, the driver output is set to Enable by the pattern DRE 13 and the pattern PAT 17 is output from the driver 4, and the pattern PCPE7 is set. Thus, the logical comparison in the logical comparison unit 6 is set to Disable.
At the time of Read Cycle, the driver output is set to the high impedance state by the pattern DRE13, and the pattern PC
The PE7 sets the logical comparison between the output signal of the device under test 5 and the expected value EXP14 to Enable, and Pass /
Fail 20 is judged. The memory SCRAM in the algorithmic pattern generator 2 shown in FIG.
10 scrambles the address generated by the address generator 9. Here, the data pattern PATD8 and the pattern PCPE7 generated from the data buffer memory 1 are the algorithmic pattern generator 2
It is synchronized with the pattern generation cycle of.

When performing an I / O pin test of the logic section 15 of the device under test 5, a random pattern for I / O control must be generated at an arbitrary channel / time. The algorithmic pattern generator 2 mounted on the semiconductor test apparatus of the conventional technique has a length of less than 1 kWds in the depth direction of the WCS, which is an instruction memory, and is long even when it is necessary to repeatedly generate a pattern by a loop. A random pattern cannot be generated. Therefore, the I / O control pattern DRE
When the algorithm 13 is generated from the algorithmic pattern generator 2 as in the prior art, the I / O control of the driver 4 for a long pattern cannot be performed and the logic part 15 of the memory device 5 to be measured cannot be tested. Also, CA
It has a drawback that it is also difficult to test by linking the D pattern program.

[0006]

The I / I of the logic section of the device under test, which incorporates the circuit of the conventional logic section, has been described.
The O-pin test did not require a random test pattern in the depth direction, nor did the CAD test pattern be linked and used. Therefore, even if the capacitance in the depth direction of the pattern used for I / O control is small, there is no problem. However, in recent years, the circuit configuration of the logic part of the device under test 5 is complicated and a longer test pattern is required.
There is also a need for tests that link these test patterns.

However, in the conventional memory semiconductor test apparatus, the circuit function for generating a random pattern for controlling the I / O of the pattern data applied to the memory device to be measured is insufficient and the device to be measured as described above is insufficient. Memory device cannot measure. The problem to be solved by the present invention is to provide a pattern generation circuit that enables a large capacity in the depth direction of a memory for generating a pattern used for I / O control, and that enables a test linked with a CAD test pattern. It is to be realized.

[0008]

In order to solve the above problems, in the present invention, address scrambling (Sc) is performed.
A part of the SCRAM in the algorithmic pattern generator used for a random) is used as a buffer memory of a random pattern for I / O control, and an I / O control pattern EDRE is generated. In the selector in the programmable data selector, the conventional I / O control pattern NDRE generated from the I / O control signal generation unit in the algorithmic pattern generator,
The newly provided I / O control pattern EDRE can be selected.

When testing the logic part of the device to be measured by the memory semiconductor test apparatus, the I / O control pattern EDRE of the present invention is selected, the pattern EDRE is interrupted in the I / O control line, and the pattern is applied to the driver. Then, I / O control is performed. With such a circuit configuration, it is possible to generate a long random pattern required for the test of the logic part of the memory device to be measured, and it is also possible to perform a test in which a CAD pattern program is linked. . It should be noted that instead of using a part of SCRAM, a part of data buffer memory is used for I / O.
The same thing can be done by generating EDRE which is a control pattern or separately providing it as an external memory and outputting it.

[0010]

[Action]

(1) Normally, in a memory semiconductor test device having a general prior art circuit configuration, an instruction memory W
Since the capacity of CS in the depth direction is only about 1 kWds, the capacity of SCRAM which is a scramble memory in the algorithmic pattern generator is usually about 64 kWords, so the memory device to be measured is It was sufficient to generate the long random pattern required for the test pattern of the logic part of.
Further, the data buffer memory is generally composed of about 72 bits, and a sufficient capacity can be obtained even when a part of the data buffer memory is used. (2) In the present invention, the hardware of the memory semiconductor test apparatus having the circuit configuration of the prior art has only a few steps to be taken for the hardware, and it can be dealt with by the software program.

[0011]

1 is a block diagram showing the concept of an embodiment of the present invention. 2 is a block diagram showing the concept of another embodiment of the present invention. (1) As shown in FIG. 1, in the present invention, a part of the SCRAM 10 in the algorithmic pattern generator 2 which is used only for address scrambling in the memory semiconductor test device having the conventional circuit configuration is , Used as a random pattern buffer memory for I / O control. Then, the pattern EDRE 18, which is an I / O control pattern, is generated from there. Further, the selector 19 of the present invention is provided in the programmable data selector, and the pattern NDRE 12 and the pattern EDRE 18 which are the conventional I / O control patterns generated from the I / O control signal generator 11 of the algorithmic pattern generator 2 are provided. Made it possible to select.

(2) When the logic section 15 of the device under test 5 is tested, the pattern EDRE 18 is selected, the pattern EDRE 18 is interrupted in the I / O control line, and the I / O control is performed by applying it to the driver 4. I do. As a result, a long random pattern, which is necessary as a test pattern for the logic unit 15 of the device under test 5, can be generated, so that the logic unit 15 can be tested, and a test in which a CAD pattern program is linked is also possible. It has become possible. According to the configuration in which the selector 19 is newly provided in the programmable data selector 3 according to the present invention, the SCRAM 1 in the algorithmic pattern generator 2 is provided.
Instead of using 0, a part of the data buffer memory 1 is used and a pattern EDRE1 which is an I / O control pattern is used.
It is now possible to generate and output 8. Furthermore,
If the SCRAM 10 and the data buffer memory 1 cannot be used due to the user's convenience in using the test apparatus, a configuration is possible in which an external memory is separately prepared and output.

[0013]

Since the present invention is configured as described above, it has the following effects. According to the present invention, the I / O of the logic part of the device under measurement is
When performing an O-pin test, a long random pattern that repeats the pattern by the loop necessary for controlling the I / O of the driver at an arbitrary channel / time was generated with sufficient margin, so it becomes the measured object. Even if the logic part of the memory device is large and complicated, which is increasing in recent years, I / O can be
The O-pin test has become possible sufficiently, and the test as a CAD pattern program link linked with CAD has become possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of an embodiment of the present invention.

FIG. 2 is a block diagram showing the concept of another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a random pattern generation circuit for I / O controlling applied pattern data according to a conventional technique.

FIG. 4 shows I / O of a logic part of a memory device to be measured.
The timing chart at the time of an O pin test is shown.

[Explanation of symbols]

 1 Data Buffer Memory 2 Algorithmic Pattern Generator 3 Programmable Data Selector 4 Driver 5 Device Under Test 6 Logical Comparison Unit 7 Pattern PCPE 8 Pattern PATD 9 Address Generator 10 SCRAM 11 I / O Control Signal Generator 12 Pattern NDRE 13 Pattern DRE 14 Expected value EXP 15 Logic part 16 Comparator 17 Pattern PAT 18 Pattern EDRE 19 Selector 20 Pass / Fail

Claims (3)

[Claims] 1. A SCRAM (10) which is a scramble memory of an address, which uses a part of a memory function as a buffer memory of a random pattern for I / O control and generates a pattern EDRE (18) for I / O control. When testing the logic part (15) of the device under test (5), the EDRE that is the I / O control pattern is tested.
Select (18) and add the EDRE to the I / O control line.
A memory semiconductor test apparatus comprising: a selector (19) which interrupts (18) and uses it as an I / O control pattern of the driver (4). 2. The memory semiconductor test apparatus according to claim 1, wherein a part of the data buffer memory (1) is used instead of the SCRAM (10) to generate the I / O control pattern EDRE (18). 3. An I / O control pattern EDR is synchronized with a pattern generation cycle of an algorithmic pattern generator (2) from a memory provided separately as an external memory.
The memory semiconductor test apparatus according to claim 1, wherein E (18) is generated.