JPH0888615A - Signal multiplexer and multiplex signal demultiplexer - Google Patents

Abstract

PURPOSE: To eliminate the need for an identification signal and to reduce the scale of the demultiplexer by automatically identifying a transport stream(TS)/a program stream(PS) which are disabled discrimination without other identification signal in the method employing the TS or the method employing the PS as the system to multiples audio and video data or the like. CONSTITUTION: The multiplexer (demultiplexer) is constituted of a circuit 101 detecting TS synchronization from a received multiplex signal, a circuit 104 detecting PS synchronization, and a changeover control circuit 103 identifying the PS/TS based on the result of two synchronization detecting circuit and switching any of them. Therefor, according to the constitution, an identification signal is not required the automatically identifying the TS/PS to reduce the scale of the multiplexer (demultiplexer) and the multiplex signal demultiplexer is realized with high flexibility by processing a code string in which the TS and PS are in existence in mixture.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing signal demultiplexing device and a demultiplexing device for demultiplexing desired information from a code string in which a plurality of information such as video signals and audio-acoustic signals are multiplexed.
In particular, it is applied to an audio / audio video signal separation part of a video decoding device / encoding device such as digital broadcasting or cable television or a reproducing device such as a digital video disc.

[0002]

2. Description of the Related Art Studies have been actively conducted to digitize video signals and audio signals, compress them, and store or transmit them.
On the other hand, studies are being made to multiplex these compressed digital signals. By multiplexing multiple pieces of audiovisual information, it is possible to clarify the mutual relationship between these individual pieces of information, facilitate management during transmission or storage, and facilitate standardization of receiving terminals. Occurs. ISO / IEC DIS standardized by International Organization Standardization (ISO) is a typical method of multiplexing audiovisual information.
There is 13818-1 (94.6, also known as MPEG2 systems). MPEG2 s
Details of the ystems are described in detail in the above ISO / IEC DIS 13818-1. Therefore, only this outline will be described in this description.

MPEG2 systems specify two multiplexing methods. One is the transport stream and the other is the program stream.

FIG. 1 shows a transport stream (T
It is a figure showing composition of S). The TS consists of a fixed-length packet of 188 bytes, and at the beginning of it is 4 in hexadecimal notation.
Sync byte 30 of 7 (hereinafter, hexadecimal notation is represented by adding 0X to the beginning of the number like 0X47. Here, when transmitting and accumulating in bit units, processing is performed in order from the most significant bit of 8-bit byte data) 1-3 (byte for synchronization)
Is attached. In the remaining 187 bytes (31-1 to 3) of each packet, a part of data such as audio or video is stored together with an identification number indicating the type of the data and information necessary for decoding. Data multiplexing is 1
This is performed for each 88-byte packet, and the receiving side can separate the required data based on the identification number of the data type. Since the TS is composed of a relatively short fixed length packet, the influence of an error or the like can be reduced, and it is advantageous when a large amount of high-speed data is multiplexed. Generally, it is assumed to be used for applications such as communication and broadcasting.

FIG. 2 is a diagram showing the structure of a program stream (PS). The PS consists of packets called variable-length packs, and the pack starts with 0X000001.
32-bit pack header 40-1 represented by BA
2 is added. In the code string stipulated by ISO / IEC 13818, it is prohibited to have 23 or more consecutive 0 bits except for special codes such as pack headers, so data (from the bit unit to the byte unit) (Including the case of data whose delimiter is unknown) is read, the head of the pack can be uniquely identified. One or more PEs after the pack header (41-1 and 2)
S packets are stored, and one PES packet stores a part of data such as one audio or video.
The PES packet is a variable-length packet, and its length, an identification number indicating the type of data, and information necessary for decoding are stored together with the data. End of all data is 0X0
It is notified by an MPEG program end code composed of 000019. Since the PS is composed of packets that are considerably longer than the TS, the amount of processing such as packet header analysis processing is small, and the amount of multiplexed data is often relatively small. Therefore, it is possible to construct an inexpensive multiple signal demultiplexing device by software. Generally, it is assumed to be used for storage and file transfer between computers. Therefore, a code indicating the end of all data is strictly defined (TS does not specifically define).

FIG. 3 shows the configuration of a conventional multiple signal demultiplexer. The multiplex signal separation device of FIG. 3 has a function of separating multiplex data of both TS and PS.

The multiplexed signal 1 is input to either a circuit for processing TS or a circuit for processing PS by the switch 2. Switching of the switch is instructed from outside the device. The instruction is given by the data bus 24, the address 25, the RW selection signal 26, and the status notification signal 27 of the external IF 20, and the external IF circuit 20 outputs the signal written at a predetermined address to the signal line 21 to select TS and PS. I do. For example, when the signal line 21 is 1, TS is selected, and when the signal line 21 is 0, P is selected.
S is selected. The signal line 21 is also input to the selection circuit 7 and is also used to select the separated data.

In the multiplexed signal input to the TS synchronization detection circuit 3, sync bytes (30-1 to 3 etc.) are detected in the same circuit. After the sync byte is detected and the synchronization is correctly established, the multiplex signal 4 is output, and at the same time, the synchronization signal 22 that outputs the pulse indicating the synchronization at the timing of the data of the sync byte is output. In the TS separation circuit 5, the synchronization signal 22
The data inside the packet is analyzed on the basis of the timing indicated by and the desired data is output to the designated portion of the separated data 6-1 to n. Here, the value of n is a value predetermined according to the function / configuration of the device. For example, in the minimum device, n = 2 because only the audio signal and the video signal are required. In a device that requires a large number of audio, video or other data at the same time, n takes a value of 3 or more. The control information and the information necessary for decoding, which are multiplexed in the multiplexed signal, are output as the separated data 6-0.

The multiplex signal input to the PS sync detection circuit 13 is the same as the sync signal (40-1 to 40-1) of the pack header.
2) is detected. After the pack head is detected and synchronization is correctly established, the multiplex signal 14 is output, and the sync signal 23 that outputs a pulse indicating synchronization at the timing of the data at the pack head is also output. The PS separation circuit 15 analyzes the data in the packet based on the timing indicated by the synchronization signal 23 and separates the desired data into the separated data 7-1 to n.
Output to the specified location. Separated data 7 is used for control information and information necessary for decoding that were multiplexed in the multiplexed signal.
Output to -0.

In the selection circuit 7, the data indicated by the signal line 21 out of the separation data 6-1 to n separated by the TS separation circuit 5 and the separation data 7-1 to n separated by the PS separation circuit 15. To the separated data 8-1 to n. At the same time, the control information of the separated data 6-0 or the separated data 7-0 is output to the external IF circuit 20 as the separated data 8-0 so that the control data can be read from an external control device.

FIG. 4 shows a detailed view of the TS synchronization detection circuit 3. The input multiplexed signal is once stored in the register 40 and then compared with the fixed data 41 (0X47: sync byte code) in the comparison circuit 42. On the other hand, the memory 45 has 18
It is a memory having a capacity of 8 bits, and all bits are set to 1 in the initial state. The address signal 57 of the memory 45 is connected to a counter 56 that operates periodically in synchronization with input data in 188 cycles.
The 188 bits inside are sequentially accessed. The entire circuit operates in a unit of time that is twice the operating frequency of the counter 56, that is, half the data input period. In the first half of the data input cycle, the write signal 51 of the memory 45 is prohibited,
By allowing the output signal 54, the memory is brought into a read state. The data read from the memory 45 is stored in the register 47. In the latter half of the data input cycle, the write signal 51 of the memory 45 is temporarily permitted and the output signal 54 is prohibited to put the memory in the write state. The data stored in the register 47 is compared with the comparison result 43 with the previous sync byte in the AND circuit 44, and the result is output to the signal line 48. The signal line 48 is 1 when the input data coincides with the sync byte and the corresponding bit in the memory is 1, and 0 otherwise. The signal line 48 is a 3-state buffer 50.
Is written to the memory via. The written address is the same as the previously read address. Control circuit 55
Controls the memory write signal 51 output signal 54 and the like so as to perform the above operation. By repeating such an operation, only 1 bit of the 188 bits of the memory 45 remains 1 and the remaining 187 bits become 0. The counter 49 counts the number of 1 bits out of the 188 bits. That is, the reset signal 53 is received from the control circuit 55 at a fixed timing in 188 cycles. Upon receiving the reset signal, the counter 49 causes the signal line 4
8 is loaded into the least significant bit of the counter value and the remaining bits are all zeros. After that, the counter is incremented only when the signal line 48 is 1. By doing so, the value immediately before the next reset signal is input is 1 in 188 cycles.
Represents the number of When this becomes 1, the sync byte of the TS is detected and the synchronization is achieved. In synchronization with this, the control circuit 55 outputs the signal 22 indicating the synchronization position.

FIG. 5 is a detailed diagram of the PS sync detection circuit 13. The input multiplexed signal is temporarily stored in the register 60 and the register 61 in order, and then fixed data 69 and 72 (0XBA and 0X0, respectively) in the comparison circuits 70 and 73, respectively.
1). On the other hand, the output signal 41 of the register 61 is compared with the fixed data 63 (0X00) in the comparison circuit 62. If the comparison results 76 match, the counter 64 is incremented at the timing of (1) next data input, and if they do not match, the counter 64 is reset to the counter 0 at the timing of (0) next data input. The initial value of the counter 64 is 0. The output 65 of the counter 64 is compared with the fixed data 68 (3) by the comparison circuit 66. The pack header is (0
X00, 0X00, 0X01, 0XBA) are sequentially input, when the data 0XBA is stored in the register 60, the output of the register 61 becomes 0X01 and the counter 6
The output 65 of 4 becomes 2, and the three comparison results 71, 74,
All 67 are in the coincident (1) state. The AND circuit 75 outputs 1 to the synchronization signal 23 when all the comparison results 71, 74 and 67 are 1 to notify that the synchronization code is detected.

[0013]

The conventional multiplex signal separation device described above has the following two problems.

The first problem is that it is necessary to externally set which code, TS or PS, is input. Therefore, in communication and broadcasting, in addition to the means of receiving TS / PS, T
A means for receiving / decoding / setting the S / PS identification signal is required. When reading from the storage medium, it is necessary to read the auxiliary data and the like at the same time to perform TS / PS identification.

The second problem is that it is not possible to receive a code string in which TS / PS are mixed. T in ISO / IEC 13818-1
S / PS is positioned as an independent multiplex system, and it is not mentioned that they are mixed. However, merging code strings multiplexed for each TS / PS, intentionally switching TS / PS in order to cope with a change in line conditions during communication, a terminal supporting only TS and a terminal supporting only PS It is not possible to handle cases such as when performing multipoint communication including.

An object of the present invention is to automatically identify TS / PS, thereby eliminating the need for identification signals other than multiplexed signals, reducing the size of the apparatus, and at the same time handling multiple code strings in which TS and PS are mixed. It is to increase the flexibility of the signal separation device.

[0017]

In order to achieve the above object, the present invention is provided with means for detecting TS synchronization and PS synchronization at the same time, and for detecting the synchronization establishment first. . Further, when the sync code is lost in the TS or when the MPEG program end code is detected in the PS, a means for controlling to perform the sync detection operation of the previous TS and PS is provided promptly.

[0018]

By detecting TS / PS synchronization at the same time, it is possible to determine whether the code string is TS or PS.
Further, by detecting the end of TS and PS and detecting the next synchronization, it becomes possible to process a code string in which TS / PS are mixed.

[0019]

EXAMPLE FIG. 6 shows an example using the present invention. FIG. 6 is an example in which the present invention is applied to the multiplex signal separation device of FIG.
In the figure, the part indicated by 100 is the part according to the present invention, and the other parts have the same functions as those in FIG. 3, so the description thereof will be omitted and the part 100 will be mainly described.

Sync signal output 2 of the TS sync detection circuit 101
2, the TS end signal 110, the sync signal output 23 of the PS sync detection circuit 104, and the PS end signal 111 are input to the switching control circuit 103. In the switching control circuit 103, the switching signal 1 is set so that the system in which the synchronization is established is selected first.
06 is output. The switching signal 106 is input to the selection circuit 7 to select the output of TS or PS, and at the same time is input to the external IF circuit 107 to notify the outside whether TS / PS is being processed. When the selection circuit 7 is selected, the delay circuit 108 delays the selection signal by the processing time of the TS separation circuit 5 or the PS separation circuit 15.

The switching control circuit 103 operates as follows, for example.

State TS Sync PS Sync TS End PS End Next State Output Initial 0 0 X X Initial Undefined Initial 1 0 0 X TS Sync TS Sync Initial X 1 X X PS PS PS Sync TS Sync X 0 0 X TS Sync TS Sync TS Sync X 0 1 X Initial Undefined TS Sync X 1 X X PS PS PS Sync PS Sync X X X 0 PS Sync PS Sync PS Sync XX X 1 Initial Undefined Here, “X” is 1/0 input signal Show that you don't care.

Since PS synchronization uses a synchronization code that is uniquely determined, it is processed with priority over TS synchronization. Therefore, the transition from TS to PS can be performed at any time. On the other hand, a PS end signal is always required to shift from PS synchronization to another state.

By controlling as follows, T
It is also possible to prioritize S-sync over PS-sync.

State TS Sync PS Sync TS End PS End Next State Output Initial 0 0 X X Initial Undefined Initial 1 X 0 X TS Sync TS Sync Initial 0 1 X X PS Sync PS Sync TS Sync XX 0 X TS Sync TS Sync TS sync X 0 1 X Initial undefined TS sync X 1 1 X PS sync PS sync PS sync X X X X 0 PS sync PS sync PS sync X X X 1 Initial undefined The following points are different from the PS priority control. It is a point.
When the TS synchronization signal is always switched to the PS synchronization, the TS end signal becomes 1 (indicating that the TS synchronization is lost), and when the PS synchronization and the TS synchronization are simultaneously established in the initial state. This is a point that gives priority to TS synchronization. PS priority,
The present invention can be applied to any case of TS priority. The present invention can also be applied to the case where a function of switching PS priority / TS priority is provided from the outside.

FIG. 7 shows a detailed view of the TS synchronizing circuit 101 of the present invention. The operation is the same as that of the TS synchronization circuit 3 of FIG. 4 except that the ring buffer 90 is added.

When the sync byte is not input at a predetermined timing after the synchronization is established (sync byte disappears), the TS sync detection circuit sends the TS end signal 110. As the TS end signal, the TS end signal may be sent immediately after the loss of the sync byte is detected, or the TS end signal may be sent after waiting for the next sync byte input scheduled time and detecting the non-input of the sync byte.

The input multiplex data 1 is stored in the ring buffer 90 at the same time that the sync byte detection process is performed. The ring buffer 90 has a capacity of M times 188 bytes, and when a sync byte is input after the synchronization is established, the ring buffer 90 starts to output the data 188 * m bytes before the input data to the signal line 4. Where m is m <= M
And 188 * m <= (the number of input data) is the maximum integer. At this time, the first data output is the sync byte. It is necessary to read at least 189 bytes of data to establish TS synchronization. For example, as shown in FIG. 8, in a code string in which PS and TS are continuous, data until the synchronization is established, that is, a packet of TP6 is held in the ring buffer 90 to ensure data continuity. The time until TS synchronization is established depends on the input data, and is determined by the presence or absence of the same data as the sync byte (0X47 continues at a 188-byte cycle). Therefore, the ring buffer 90 has a capacity larger than 188 bytes, that is, M> = 2.
Is preferable. When the number of input data exceeds the capacity of the ring buffer 90, the oldest data in the buffer are deleted.

FIG. 9 shows a detailed diagram of the PS synchronization detection circuit 104 to which the present invention is applied. The PS sync detection circuit 104 has 12
The PS detection circuit 13 is the same as the PS detection circuit 13 except that 0 is added. The place indicated by 120 indicates the end of PS MPEG pro
gram end code (0X000001B9) is detected.
The detection method is the same as the method of detecting the beginning of the pack header. The output of the register 60 is compared with the fixed value 122 (0XB9) in the comparison circuit 121, and the comparison program 123 is used to detect the MPEG program end code in the AND circuit 124. Then, the detection result is output to the PS end signal 111.

The multiplex signal separating apparatus shown in FIG. 6 does not need to process the first byte of the input data. That is, even if the data is read from any part of the code string, T
It is possible to synchronize S or PS. Conversely, when reading from the beginning of the data (including immediately after detection of the MPEG program end code), the sync pull-in time is shortened depending on whether the first data is the TS sync byte (0X47) or PS header encoding (0X00). can do. This synchronization pull-in becomes remarkable at the time of TS synchronization pull-in. That is, when the first data is 0X47 and the 189th data is also 0X47, the synchronization is preferentially established with the timing of the first data as the sync byte even if there are sync byte candidates in other locations.

FIG. 10 shows a second embodiment of the present invention. The multiplex signal separating apparatus of FIG. 10 realizes almost the same function as the multiplex signal separating apparatus of FIG. However, PS separation is assumed to be executed by external software. As a function therefor, it has a means for outputting the multiplexed signal 14 and the synchronizing signal 23 to the outside via the external IF 107. Since the external IF 107 has the function of direct memory access, PS transfer processing can be performed more efficiently.

As described above, in the first and second embodiments, it is premised that the input multiplexed signal is an 8-bit parallel signal. This may be a 16-bit or 32-bit parallel signal. In these cases, the above-described embodiment can be applied as it is by dividing the input data into 8 bits and performing the processing. However, the internal operation timing is based on the data input timing after being divided into 8-bit units.

The present invention is also applicable to serial input. In this case, the TS synchronization circuit 101 of FIG.
Then, a memory of 188 * 8 bits is required as the memory 45, and a counter of 188 * 8 cycles is required as the counter 56. By making the register 40 part an 8-bit shift register and always inputting the latest 8 bits to the comparison circuit 42, the same processing as in the case of 8-bit parallel input can be performed. At this time, writing to the ring buffer 90 after the synchronization is detected is performed in parallel with 8 bits at a timing obtained by dividing the input cycle by 8 from the time when the synchronization is achieved. The output 4 may output the parallel data of the ring buffer 90 as it is or may convert it again into serial data.

In the case of serial input, the PS synchronizing circuit 14 of FIG. 9 is provided with an 8-bit shift register instead of the register 60, and after making 8-bit parallel data, the comparator 71 performs comparison. On the other hand, the register 61 holds the previous (old) bit of the preceding 8-bit parallel data, and the comparators 62 and 73 perform 1-bit comparison.
At this time, the fixed data 68 becomes 23 (decimal).

When the auxiliary information for synchronization detection is input from the outside, the synchronization detection may be performed based on the auxiliary information. This particularly facilitates TS sync detection. When dividing a 188-byte TS packet into packets shorter than 188 bytes and transmitting the packets, if the beginning of the TS packet always matches the beginning of the transmission packet, the synchronization is detected using the information indicating the beginning of the transmission packet. be able to. Specifically, when transmitting in an asynchronous transfer mode (ATM) cell having a length of 47 bytes or 48 bytes, 1 TS packet can be transmitted in 4 cells, or 2 TS packets can be transmitted in 8 cells. In such a case, if the head information of each cell is known, synchronization can be detected by performing four or eight sync byte comparisons. As a result, in FIG. 7, the capacity of the memory 45 is 4 bits or 8 bits, and the counter 56
Also, 4 or 8 cycles are sufficient. As described above, by using the auxiliary information, it is possible to reduce the circuit size and reduce the delay in establishing synchronization due to the influence of data similar to the synchronization pattern.

FIG. 11 shows an audiovisual receiving terminal to which the multiplex signal separating apparatus of the present invention is applied. The portion indicated by 400 corresponds to the multiplex signal separating apparatus of the present invention. The input signal 502 to the terminal is, for example, an ATM (asynchronous transfer mode) or analog modulated signal, and the reception IF circuit 503 performs signal processing according to the input signal and outputs the transmitted signal train 1. To do. This signal train 1 is a multiple signal. The multiple signal separation circuit 400 decodes and separates the multiple signal 1 and inputs the encoded audio signal 8-1 and the encoded video signal 8-2 to the audio decoder 401 and the video decoder 402, respectively, and outputs the audio signal. 411 and the video signal 412 are output. The audio decoder 401 and the video decoder 402 are ISO / IEC 13818-3 and ISO / IEC 1 respectively.
It has a function to decode the code of 3818-2. Control CPU 403
Controls these via the bus 410. Since the part indicated by 500 is a processing part corresponding to the multiplex signal 1, if it is stored in a single LSI, the circuit scale can be reduced. The audiovisual receiving terminal or 5 shown in FIG.
The multiple audiovisual processing circuit indicated by 00 is also included in the present invention.

FIG. 12 shows an embodiment of a transmitting apparatus 600 that outputs a code in which TS / PS are mixed. The figure shows an example in which one audio signal 610 and one video signal 611 are multiplexed. The audio signal 610 and the video signal 611 are encoded by the audio encoder 601 and the video encoder 602, respectively.
-1, 8-2 are encoded. The two encoded signals are multiplexed by the multiple signal generation circuit 603.
Is multiplexed with the multiplexed signal 1 by the transmission IF 604, converted into a signal form suitable for the transmission path by the transmission IF 604, and output. These controls are performed by the control CPU 605 via the bus 612. Data 62 is transmitted to and from the multiple signal generation circuit 603.
4, the address 625, the read / write switching signal 625, and the status display signal 627 are used to read / write data. It should be noted that the already encoded signal is converted into the multiple signal generation circuit 6
It is also possible to enter in 03, and this case is also included in the present invention. When the encoded signal is directly input, the corresponding audio encoder or video encoder becomes unnecessary.

FIG. 13 shows the multiple signal generation circuit 603 of FIG.
It is an example of. FIG. 13 shows that the number of input signals 8 is n
S is multiplexed and the control CPU 6 is connected via the external IF 704.
The signal 711 input from 05 is multiplexed as PS. The signal 711 includes protocol information, control information, user information, and the like. The multiple signal generation circuit 603 of FIG.
In the case of n = 2.

The input signals 8-1 to 8-n are input to the buffers 701-1 to 70-n, respectively. The signal input to each buffer is read by the TS multiplexing circuit 702 at an appropriate timing, and is TS packetized. On the other hand, signal 70
5 is input to the buffer 705, and P is set at an appropriate timing.
It is read from the S packet generation circuit and converted into PS packets. The switch 703 selects the TS packet and the PS packet in packet units according to the ratio of the amount of information,
A / PS mixed signal 1 is obtained. At this time, if the size of the PS packet is set to an integral multiple of 188 bytes, the TS signal can be easily generated from the TS / PS mixed signal by replacing the PS packet with a dummy TS packet.

The generated TS / PS signal can be received by the receiving terminal 500 shown above.

FIG. 14 shows the multiple signal generation circuit 603 of FIG.
Is another embodiment of the. FIG. 14 shows that n input signals 8 are
Multiplex as S and PS. That is, finally 1
The same information is transmitted twice in two transmission paths, TS and PS. The multiple signal generation circuit 603 of FIG.
This is the case of 2.

The input signals 8-1 to n are input to buffers 701-1 to n and buffers 800-1 to n, respectively. The signals input to the buffers 701-1 to 70-n are read out by the TS multiplexing circuit 702 at appropriate timings and are converted into TS packets. On the other hand, buffer 800-1
The signals input to n are read from the PS multiplexing circuit 801 at appropriate timings and converted into PS packets. The switch 703 selects a TS packet and a PS packet in packet units according to the ratio of the amount of information, and TS / PS
PS mixed signal 1 is obtained. At this time, if the size of the PS packet is set to an integral multiple of 188 bytes as in the embodiment of FIG. 13, the TS signal can be easily generated from the TS / PS mixed signal.

The generated TS / PS signal can be received by the receiving terminal 500 shown earlier. Also, TS
Extracting only TS packets from / PS mixed signal,
Alternatively, by extracting only the PS packet, the conventional TS receiving terminal and PS receiving terminal can also read the information.

FIG. 15 shows a transmitter 600 using the present invention.
3 shows an example of the configuration of a TS / PS mixed video communication system using the receiving terminal 500. The portion indicated by 900 corresponds to transmission equipment, and the video signal read from the camera 902, the VCR 903, the disk 904, or the like or the coded video signal is multiplexed by the transmission device 600 and transmitted to the communication network 910. On the other hand, the receiving terminal side has, for example, a configuration in which the receiving terminal 500-1 includes a monitor 905, a VCR 906, an external storage disk 908, and an input device 909 for inputting data or selecting signals.
The received video is obtained by taking out the necessary multiple signals from 10 and decoding / separating / decoding.

The form of the multiplexed signal is, for example, the TS / PS mixed signal output from the transmitter shown in FIG.
The mixed TS / PS signal output from the transmitter shown in FIG. 4 may be used. The communication network may be ATM, ISDN, analog telephone line, dedicated analog line, dedicated digital line, LAN or wireless. All the receiving terminals 500-2, 3 and the like must have a function of identifying the TS / PS mixed signal of the present invention. Although FIG. 15 describes only the transmission of video, the same processing can be performed when audio, voice, data, etc. are added.

FIG. 16 shows a transmitter 600 using the present invention.
Another example of the configuration of a video communication system of mixed TS / PS using the receiving terminal 500 is shown. Most of the parts are the same as those in FIG. 15, but the form of the multiplexed signal is, for example, TS / PS output from the transmitter shown in FIG.
Mixed signals are preferred. The receiving terminal 901 of the present invention having the function of identifying mixed TS / PS signals receives signals directly from the communication network 910 and reproduces video. On the other hand, a TS extraction circuit 920 that extracts TS packets from a mixed TS / PS signal
Alternatively, or alternatively, by providing a PS extraction circuit 921 for extracting PS packets, and installing a communication network 911 for transmitting the extracted TS-only signal and a communication network 912 for transmitting the PS-only signal, respectively, the conventional TS-dedicated reception The video can also be reproduced at the terminal 950 or the PS dedicated receiving terminal 951. In this case, the receiving terminal 901 having the function of identifying the TS / PS mixed signal of the present invention is the communication networks 910, 9
It has a feature that it can be connected to any of the networks 11 and 912. Although FIG. 16 describes only video transmission, the same processing can be performed when audio, voice, data, etc. are added. The communication networks 910, 911,
912 may be an ATM, an ISDN, an analog telephone line, a dedicated analog line, a dedicated digital line, a LAN or a wireless line, and when the same physical communication network is used in frequency or time division. Also included in the present invention.

FIG. 17 shows an embodiment of the TS extraction circuit 921. The overall configuration is the same as the multiplex signal separation circuit of FIG. The input multiplexed signal 1 is synchronized with TS / PS at the same time as in FIG. Then, the data is written in the buffer 1001 only when the TS is synchronized. The written data is read according to the transmission rate of a new TS packet. The new transmission rate is T
It is a value obtained by multiplying the ratio of S packet data. For example, T
When the data amount of the S packet and the data amount of the PS packet are the same, the transmission speed is half of the input. In this case, it is necessary to update the time stamp of the TS according to the timing of reading the data from the buffer 1001.

FIG. 18 shows another embodiment of the TS extraction circuit 921. FIG. 18 is used when the PS packet length in the input multiple signal is all an integral multiple of 188 bytes.
The input multiplexed signal 1 synchronizes TS / PS at the same time. When the TS is synchronized, the selection circuit 10
03 outputs the TS signal 4, and the null packet (dummy packet) of the TS is generated from the null packet sending circuit 1002 and transmitted during the period in which the PS is synchronized. If the PS packet length is an integral multiple of 188 bytes, all PS packets are replaced with TS null packets, and the transmission rate at the time of output does not change. It is not necessary to change the time stamp of the TS packet.

The PS extraction circuit can be realized with the same configuration as the TS extraction circuit of FIGS. Since the PS packet has a variable length, when replacing the TS packet with dummy data, there is no limitation on the TS packet length.

[0050]

According to the present invention, by simultaneously detecting TS / PS synchronization, it is possible to determine whether the code string is TS or PS without any prior information from the outside.
Alternatively, by detecting the end of TS and PS and detecting the next synchronization, TS / PS mixed communication becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a transport stream.

FIG. 2 is a diagram illustrating a program stream.

FIG. 3 is a diagram illustrating a conventional multiple signal separation device.

FIG. 4 is a detailed diagram of conventional TS synchronization detection.

FIG. 5 is a detailed diagram of conventional PS synchronization detection.

FIG. 6 is a diagram illustrating a first embodiment of a multiplex signal separation device to which the present invention has been applied.

FIG. 7 is a detailed diagram of TS synchronization detection to which the present invention is applied.

FIG. 8 is a diagram illustrating a mixture of TS and PS.

FIG. 9 is a detailed diagram of PS synchronization detection to which the present invention is applied.

FIG. 10 is a second multiplex signal demultiplexing apparatus to which the present invention is applied.
It is a figure explaining the Example of this.

FIG. 11 is a diagram illustrating an audiovisual receiving terminal to which the multiplex signal separating apparatus of the present invention is applied.

FIG. 12 is a diagram illustrating an audiovisual transmission terminal to which the multiplex signal multiplexing device of the present invention is applied.

FIG. 13 is a detailed diagram of a multiple signal generation circuit.

FIG. 14 is another configuration example of the multiple signal generation circuit.

FIG. 15 is a diagram illustrating a video transmission system to which the multiplex signal multiplexing / demultiplexing device of the present invention is applied.

FIG. 16 is a diagram illustrating another configuration example of a video transmission system to which the multiplex signal multiplexing / demultiplexing device of the present invention is applied.

FIG. 17 is a detailed diagram of a TS extraction circuit.

FIG. 18 is another configuration example of the TS extraction circuit.

[Explanation of symbols]

 1 input multiplexed signal, 3 TS sync detection circuit, 5 TS separation circuit, 7 selection circuit, 13 PS sync detection circuit, 15 PS separation circuit, 20 external IF circuit, 22 TS sync signal, 23 PS sync signal, 90 ring buffer, 103 switching control circuit, 400 multiplex signal separation circuit, 500 audiovisual receiving terminal, 600 audiovisual transmitting terminal

Claims (5)

[Claims] 1. A first multiplexed signal decoding unit for separating a desired code sequence from a first code sequence in which data is multiplexed by using a synchronization code which is periodically inserted, and is distinguished from other codes. In the multiplex signal demultiplexing device including the second multiplex signal decoding unit 2 for separating a desired code string from the data of the second code string in which data is multiplexed using a possible unique code, the first code The first synchronization detecting section 1 of the sequence, the second synchronization detecting section of the second code sequence, and the signals of whether the synchronization establishment is correct output from the first and second synchronization detecting sections A multiplex signal demultiplexing apparatus comprising: an identification unit that identifies either the first or second code string and a selection unit that selects data to be separated according to the identification result. 2. A multiplexed signal demultiplexing device comprising a multiplexed signal decoding unit for demultiplexing a desired code sequence from a first code sequence in which data is multiplexed using a synchronization code inserted periodically. No. 1 of the two code strings by inputting the synchronization establishment corrector 1 of the first code string 1, the second synchronization detector 2 of the second code string 2 A multiplex signal demultiplexing apparatus comprising: an identification unit for identifying whether or not the data is separated by the multiplex signal decoding unit according to the identification result and a selection unit for selecting the input data. 3. The multiplex signal demultiplexing apparatus according to claim 1, wherein the first code string is a transport stream and the second code string is a program stream. 4. A means for generating a packet from a plurality of pieces of input data using a synchronization code which is periodically inserted, a means for generating a packet using a unique code which can be distinguished from other codes, and 2. 1. A signal multiplexing apparatus comprising: a unit for selecting a generated packet of a type; and a unit for transmitting the selected packet. 5. A first method using a synchronization code which is periodically inserted.
In a multiplexing signal demultiplexing device that demultiplexes a desired packet sequence from a packet sequence in which the packet of 1) and a second packet using a unique code that can be distinguished from other codes are mixed,
The first synchronization detecting unit of the first packet, the second synchronization detecting unit of the second packet, and the two synchronization signal inputting the signals of correctness of synchronization establishment output from the two synchronization detecting units. 2. A multiplex signal demultiplexing device, comprising: an identification unit that identifies any of the above, and a selection unit that selects a packet to be separated according to the identification result.