JPH088668A - Output waveform duty control circuit - Google Patents

Abstract

PURPOSE:To control a comparison reference voltage by sampling the output waveform from a signal output circuit having a differential pair constitution by plural clocks different by phases and using the average value of sampled data. CONSTITUTION:This control circuit consists of a delay circuit which generates plural clock signals having the same speed and prescribed phase relations to an input signal, temporary storage circuits 2 and 3 which are triggered by plural clock signals from the delay circuit to temporarily store the output signal from the signal output circuit and correspond to plural clock signals respectively, average value circuits 4 and 5 which obtain the average values of outputs from plural temporary storage circuits 2 and 3 respectively, and a discriminating circuit 6 detects the difference between average value outputs from average value circuits 4 and 5 and controls the reference voltage given to the signal output circuit so as to minimize this difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output waveform duty control circuit, and more particularly, in a signal output circuit having a differential pair configuration such as an optical transmission circuit in optical communication, an input signal waveform applied to one input and the other input. The present invention relates to an output waveform duty control circuit for controlling the duty of an output signal obtained by comparing with a reference voltage given to.

[0002]

2. Description of the Related Art FIG. 7 shows a circuit example of a differential input buffer section of an optical transmission circuit formed into an IC. In FIG. 7, one input terminal of the differential amplifier composed of the differential pair transistors 47 and 48 and the like has an input data signal (Di
n) is applied, and the reference voltage (Dref) as the comparison reference signal is applied to the other input terminal. The comparison signal is given as an output signal (Q, Q *) from each of the output transistors 49 and 50 to a laser diode driver (not shown) in the subsequent stage. The laser diode converts the electric output signal from the laser diode driving unit into an optical signal and outputs the optical signal to the optical fiber transmission line.

[0003]

However, as shown in FIG. 7, the input data signal and the reference voltage are transmitted to the differential pair transistor 47 through the respective input buffer transistors 41 and 44 and the level shift diodes 42 to 45. , 48 gates. Therefore, there is a limit to fixedly and accurately setting the reference voltage from the outside due to a level shift due to variations in the gate-source voltage of each transistor, a temperature change of its frequency characteristic, and the like.

In this case, particularly in high-speed optical communication in which the data transmission rate reaches several Gbit / s, the rising time (tr) and the falling time (tf) account for a large proportion of the input data signal waveform (Din), There is a problem in that the duty of the output data signal waveform varies greatly depending on the set value of the reference voltage. Further, in order to realize the above-mentioned high-speed communication, when the above-mentioned circuit is configured using a gallium arsenide transistor suitable for high-speed operation, the fluctuation characteristics such as the level and temperature are easily affected by the manufacturing process and the like. Therefore, it is more difficult to externally set the reference voltage fixedly in order to adjust the duty of the output signal waveform.

FIG. 8 is an explanatory diagram showing that the duty of the output data signal waveform varies depending on the input data signal waveform and the reference voltage value. In FIG. 8A, a high-speed NRZ input data signal waveform (Din) in which the ratio of the rising time and the falling time to the input waveform is large
And the case where the reference voltage (Dref) for determining the data value "1" or "0" fluctuates up and down. 8B to 8C show respective output data signal waveforms corresponding to the fluctuation of the reference voltage. FIG. 8B shows a case where the reference voltage (Dref) is set higher than the standard value (shown by a dotted line in FIG. 8A), and FIG.
Indicates that the reference voltage is set to the standard value ((a) in FIG. 8).
FIG. 8D shows the case where the reference voltage is set lower than the standard value (shown by the alternate long and short dash line in FIG. 8A).

As shown in FIG. 8, the duty of the output waveform changes greatly depending on the set value of the reference voltage, and if the laser diode is driven in this circuit configuration, it leads to deterioration of the optical output waveform, and therefore the line quality is reduced. There was a possibility that it could not be secured, and there was a system configuration problem. Further, the optical transmission circuit is generally a constant optical output power control circuit (APC).
Circuit) is provided. The APC circuit detects the deterioration of the laser diode by monitoring the output power of the laser diode, and controls the pulse drive current and bias current of the laser diode in order to control the optical output power to be constant. However, the AP
The C circuit also follows changes in output power due to duty fluctuation of the output waveform, and depending on the duty, an output signal having an excessive or excessive peak value is sent out to the transmission line, so that the line quality cannot be secured. was there.

In view of the above problems, an object of the present invention is to provide an input signal waveform applied to one input and a reference voltage applied to the other input in a signal output circuit having a differential pair configuration such as an optical transmission circuit. And an output signal that sequentially detects the duty of the output signal waveform from an output signal obtained by comparing the output signal waveform and the feedback control of the reference voltage value so that the duty of the output signal waveform becomes optimal (duty 100% for the NRZ signal). By newly providing a waveform duty control circuit, an output signal from the signal output circuit having an optimum duty that does not depend on the internal circuit configuration of the signal output circuit having the differential pair configuration, element variation and its temperature characteristics, etc. The waveform is not guaranteed.

[0008]

According to the present invention, there is provided a differential pair configuration in which an input signal is provided to one input and a reference voltage is provided to the other input, and the input signal and the reference voltage are provided. The circuit for performing duty control of the output signal waveform with respect to the output signal from the signal output circuit which outputs the comparison judgment signal with: is a plurality of clock signals having the same speed and a predetermined phase relationship with the input signal. A plurality of temporary storage circuits respectively corresponding to the plurality of clock signals which are triggered by the plurality of clock signals from the delay circuit and temporarily store the output signal from the signal output circuit; An average value circuit for obtaining the average value of each output from the temporary storage circuit; and a difference between the average value outputs from the average value circuit is detected, and the difference is minimized. Output waveform duty control circuit constituting the judgment circuit for controlling the reference voltage applied to the signal output circuit is provided.

The determination circuit detects the difference between the average value outputs from the A / D converter for converting each average value output from the average value circuit from an analog signal to a digital signal, and the difference between the average value outputs. , A digital operation circuit for generating the reference voltage applied to the signal output circuit, and a D / A conversion for converting the reference voltage from a digital signal into an analog signal and applying it to the signal output circuit as the reference voltage. It consists of vessels.

Further, according to the present invention, there is provided a differential pair configuration in which an input signal is applied to one input and a reference voltage is applied to the other input, and a comparison / determination signal between the input signal and the reference voltage is provided. The circuit that performs duty control of the output signal waveform for the output signal from the signal output circuit that outputs
A delay circuit for generating a plurality of clock signals having the same speed and a predetermined phase relationship with the input signal; triggered by a plurality of clock signals from the delay circuit,
A plurality of temporary storage circuits respectively corresponding to the plurality of clock signals for temporarily storing the output signal from the signal output circuit; a first average value for obtaining an average value of each output from the plurality of temporary storage circuits Circuit; adder circuit for adding and outputting each output average value from the first average value circuit; determining an average value of the input signals of the signal output circuit, and adding it to the number of average values from the first average value circuit A second average value circuit for giving a corresponding gain; and comparing the output levels from the adder circuit with the output level from the second average value circuit as a reference, and giving them to the signal output circuit so that they become equal. An output waveform duty control circuit is provided which comprises a comparator circuit for controlling the reference voltage.

Each of the output waveform duty control circuits described above uses two D type flip-flop circuits as the temporary storage circuit, and one clock signal from the delay circuit and two clock signals delayed by a half cycle from the clock signal. It can be configured with two clock signals. The signal output circuit is an optical transmission circuit or the like that converts an electric signal into an optical signal and outputs the optical signal.

[0012]

By using a plurality of clock signals having a predetermined phase relationship with the input signal, the output signal from the output circuit is fetched into each temporary storage circuit including a D-type flip-flop corresponding to them. If the duty of the output signal waveform fluctuates due to the internal circuit configuration of the output circuit, the element used, its temperature characteristics, etc., it causes the phase fluctuation of the output signal waveform, and thus the different phase clocks are used. Phase information corresponding to the duty fluctuation appears at the output of each flip-flop.

The average value circuit is composed of a low-pass filter that smoothes the output from each flip-flop and obtains the average value. The duty variation information converted into the DC level by the average value circuit is given to the determination circuit at the next stage. In the determination circuit, when the flip-flops are operated with a plurality of clock signals each having a predetermined phase relationship with the input signal, the average values are output when the output signal waveform has a duty of 100% (NRZ signal). Focusing on the fact that the outputs are equal to each other (the difference between the average values is zero), the reference voltage of the output circuit is controlled so as to minimize the difference between the average values. As a result, the duty of the output waveform is kept at 100% regardless of the internal configuration of the output circuit, the element characteristics, and the like.

[0014]

1 is a circuit block diagram showing the basic configuration of an output waveform duty control circuit according to the present invention. FIG.
In the above, the comparator 1 corresponds to the signal output circuit having the above-mentioned conventional differential pair configuration, in which the input data signal (Din) is given to one input, and the reference voltage (Dref) is given to the other input. ) Is given. The comparator 1 compares the input data signal with a reference voltage to determine the value of the input data signal.
The output data signal of the comparator 1 is input to the flip-flop circuits 2 and 3 and the output data signal is latched by a clock signal from the outside. A clock signal delayed by a delay element 7 for a predetermined time is applied to the flip-flop circuit 3.

The low-pass filters 4 and 5 in the next stage smooth the latch output signals from the flip-flop circuits 2 and 3 in the previous stage and output the average value DC signal. The determination circuit 6 at the final stage, based on the averaged signal,
Judge the current duty state of the output signal of the comparator 1,
The reference voltage is feedback-controlled so that its duty becomes optimum. For example, when the data signal is in the NRZ code format, the control is performed so that the duty is 100%.

FIG. 2 is an operation timing chart showing an example of the operation of the output waveform duty control circuit according to the present invention in FIG. 2A, the input data signal waveform of the flip-flop circuits 2 and 3 of FIG. 1 (output data signal waveform of the comparator 1) is 100% (shown by a solid line), the duty is 50% (shown by a dotted line), and Each case of 150% (indicated by a one-dot chain line) is shown. In this example,
A data signal in the NRZ code format is used, and FIG. 2A shows a case of a data bit string of "1011010". 2B shows the clock signal of FIG. 1, and FIG. 2C shows the clock signal delayed by 1/2 clock time by the delay element 7 of FIG. Therefore, in the case of this example, the delay element 7 can be configured by one inverter circuit.

2D to 2F are D-type flip-flop circuits (FF1, FF1) used in this example for the respective cases of the input data signal waveforms having the duty of 100%, 50% and 150%. Output data signal waveforms from FF2) 2 and 3 are shown respectively. The D-type flip-flop circuits 2 and 3 are drawn as holding and outputting input data at the rising edge of the clock signal. Duty 100% in FIG. 2 (d)
In the case of, the output waveforms of the flip-flop circuits (FF1, FF2) 2 and 3 are determined by the relationship between the solid line waveform of FIG. 2A and the rising edges of the clocks of FIGS. 2B and 2C. Will be the same. Therefore, in this case, the average value output from each of the low pass filters 4 and 5 described in FIG. 1 shows the same value.

Next, in the case of the duty of 50% in FIG. 2 (e), from the relationship between the dotted line waveform in FIG. 2 (a) and the rising edges of the clocks in FIG. 2 (b) and (c). , The output waveforms from the flip-flop circuits (FF1, FF2) 2 and 3 are not identical, and in the case of this example, the output of the output data value "1" from the flip-flop circuit (FF2) 3 decreases. There is. On the contrary, in the case of the duty of 150% in FIG. 2 (f), from the relationship between the dashed-dotted line waveform in FIG. 2 (a) and each clock rising edge in FIG. 2 (b) and (c) Similarly, the identity of the output waveforms from the flip-flop circuits (FF1, FF2) 2 and 3 is broken, and in the case of this example, the flip-flop circuit (FF1)
The output of the output data value "1" from 2 is increasing.

Therefore, the duty 5 of FIG.
In the case of 0% and the duty of 150% in FIG. 2 (f), the average value output from each of the low-pass filters 4 and 5 described in FIG. 1 shows different values. Therefore, from the above three cases, the determination circuit 6 of FIG.
Monitors the average value output from the low-pass filters 4 and 5, generates a reference voltage value (Dref) so that the difference between the average values becomes small, and feeds it back to the reference voltage input of the comparator 1. By doing so, it is possible to approach the case of the duty of 100% shown in FIG.

FIG. 3 shows an embodiment of the output waveform duty control circuit according to the present invention shown in FIG. In FIG. 3, the decision circuit 6 of FIG. 1 is composed of a microprocessor 16, and therefore, the analog-digital converter (A / A / D) for converting the analog output signal from each low-pass filter 15, 14 into a digital output signal.
D) 17 and 18 are provided respectively. Further, a digital-analog converter (D / A) 19 for converting the digital reference voltage signal from the microprocessor 16 into an analog signal is provided. Otherwise, Figure 1
And is not described further here.

FIG. 4 shows an example of a control flowchart of the microprocessor 16 shown in FIG. In FIG. 4, as an initial setting procedure, in step 101, a reference voltage (Dref) at the time of operation disclosure, in step 102, the output voltage value V1 from the A / D converter 17 and the output voltage value from the A / D converter 18 are set. The absolute value of the voltage difference with V2 (|
V1-V2 |) allowable width Dw, and step S103
Then, the increasing / decreasing step width x of the reference voltage (Dref) having the increasing / decreasing sign (+, −) as Δd is set in the corresponding memory area or internal register.

Next, during the operation, in steps 104 and 105, the output voltage value V from the A / D converter 17 is output.
1, and the output voltage value V2 from the A / D converter 18 is input to the registers A and B, respectively. Step S106
At, the absolute value of the difference (| V1-V2 |) is taken and input to the register C. Then, in step S107, it is determined whether or not the absolute value is within the allowable width Dw. When it is determined that the allowable width is within Dw, that is, when the duty of the output signal waveform is almost 100% as described above, the reference voltage (Dref) at that time is directly output without being changed in step S108. To be done. Then, in step S109, a timer for counting a predetermined control cycle is set, and upon completion of the counting, step S104 and subsequent steps are repeated again.

When it is determined in step S107 that the absolute value is other than the allowable width Dw, the absolute value is converged within the allowable width Dw to make the duty almost 100%. Therefore, first in step 110, the difference is calculated. Absolute value C,
Absolute difference value Cp obtained in the immediately preceding control cycle
Compare with. If it is determined that Cp> C, that is, if the current difference absolute value C is smaller than the previous difference absolute value Cp, then Cp is updated to C in step S111, and then step S112. Then, Δd consisting of the increment / decrement step width x with the increment / decrement sign (+ or −) at that time is added to the reference voltage (Dref) at that time, and the reference voltage after the addition is updated to the updated reference voltage (Dref).
). After that, the above-described step S108 and subsequent steps are repeated.

If it is determined in step S110 that the current difference absolute value C is equal to or larger than the previous difference absolute value Cp, it means that the update direction of the previous reference voltage is wrong. Therefore, steps S113 to 11
At 5, the current increase / decrease sign (+ or-) is inverted. After this, the above-described step S111 and subsequent steps are executed,
The reference voltage (Dref) is updated in the opposite direction to the previous cycle according to the increase / decrease step width x having the opposite increase / decrease sign (-or +). As described above, the reference voltage (Dref) is set so that the duty of the output waveform becomes 100% by the control flow described above.
Are sequentially feedback controlled.

FIG. 5 is a circuit block diagram showing another configuration example of the output waveform duty control circuit according to the present invention.
The difference between FIG. 5 and FIG. 1 described above is only that the determination circuit 6 of FIG. 1 is configured by an addition circuit 28, a low-pass filter 29, and a comparator 26 in FIG. Therefore,
Here, only the difference will be described. In FIG. 5, the input data signal is smoothed through the low pass filter 29, and its average value V1 is given to one input of the comparator 26. Further, the average value output from each of the low pass filters 24 and 25 is added by the adding circuit 28, and the added output is given to the other input of the comparator 26.

Here, as shown in FIG. 2, the duty of the output data signal waveform from the differential pair circuit 21 of FIG.
In the case of 0%, the output data signal waveforms of the flip-flop circuits 22 and 23 are the same. Further, at this time, the respective output data signal waveforms substantially match the respective input data signal waveforms (duty is 100%).
Therefore, when the gain of the low-pass filter 29 is 1, the average value output from the adder circuit 28 is about twice the average value output. If the gain of the low-pass filter 29 is set to double, the average value output is output. When the duty of the data signal waveform is 100%, the output signals V1 and V2 are substantially equal to each other. The reason why they are almost equal in the above is that the input data signal waveforms are trapezoidal and not so-called square waves, as shown in FIG.

Therefore, in this embodiment, the duty of the output data signal waveform from the differential pair circuit 21 is 100% by, for example, initial adjustment of the gain of the low-pass filter 29.
At that time, the output V1 is set to be equal to the output value V2 of the adder circuit 28, and it is used as the comparison threshold signal of the comparator 26. As described in FIG. 2, the adder circuit 2
In the mean value output V2 from 8, the output from one flip-flop (FF2) is a low level value when the duty of the output data signal waveform becomes small and the state of FIG.
The 0 "side becomes dominant. On the contrary, when the duty of the output data signal waveform becomes large and the state of FIG. 2 (f) is reached, the output from one flip-flop (FF1) is at the high level value" 1 ". The side becomes dominant.

From this, in the former case, the voltage of the output V2 of the adder circuit 28 decreases, so that the reference voltage (Dref) is decreased by the comparator 26 as described in FIG. 8 and V1 = V2.
Return to the state of. Further, in the latter case, the voltage of the output V2 of the adder circuit 28 rises, and therefore the reference voltage (Dref) is raised by the comparator 26 to restore the state of V1 = V2. That is, in any case, the feedback control is executed so that the duty of the output data signal waveform becomes 100%. In this embodiment, by using the input average value as a reference, it is possible to deal with variations in the mark ratio of the input data signal. As described above, when the circuit configuration according to the present invention is used, the duty of the output data signal waveform can be easily maintained and controlled at 100% by a simple analog circuit such as a comparator.

FIG. 6 is a circuit diagram showing an embodiment of an optical transmission circuit using the output waveform duty control circuit according to the present invention shown in FIG. In FIG. 6, the lower part shows the output waveform duty control circuit according to the present invention.
The same reference numerals are given. The upper part of FIG. 6 is a so-called APC circuit of the optical transmission circuit.

The operation of the APC circuit part will be briefly described. The Ip driver circuit 21 and the bias thereof, which are composed of a differential pair configuration to which an input data signal and a reference voltage are applied, and drive the pulse output current (Ip) of the laser diode. A laser diode (LD) 30 is driven by an Ib driver circuit 34 that provides a current (Ib). The photodiode (PD) 31 is the laser diode 30.
The optical output is monitored in order to confirm the normal operation of, and the monitor current is given to one input of the comparator 33 as its average value through the low-pass filter 32. Further, the average value of the input data signal passed through the low pass filter 35 is given to the other input of the comparator 33 as a comparison reference signal. The comparator 33 controls the current values Ip and Ib from the Ip driver circuit 21 and the Ib driver circuit 34 so that the average value of the monitor current matches the reference signal, whereby the output power of the laser diode 30 is controlled. Keep constant.

However, as described in the conventional problem, the output power from the laser diode 30 also varies depending on the duty of its output waveform. The output waveform duty control circuit unit according to the present invention in the lower part of FIG. 6 eliminates a variation factor of the output power related to the duty of the output waveform, whereby the control operation of the APC circuit unit described above is the original purpose. It can be limited to those caused by the failure of the diode 30 or deterioration over time.
The operation of the output waveform duty control circuit section has already been described with reference to FIG. 5, and will not be described further here.

In the above description, in each embodiment,
Since all the two flip-flop circuits are used and only the original clock signal and the clock signal with a half cycle delay are used for the clock signal, the control duty range of the output waveform duty control circuit according to the present invention is Therefore, only the range of 50-150% was covered.

However, the present invention is not limited to such a configuration, and by using a plurality of flip-flop circuits and clock signals having a plurality of identification phase relationships corresponding thereto, for example, FF number identification phase Relation Control duty range 2 1/2 cycle shifts 50-150% 5 1/5 cycle shifts 80-120% 10 1/10 cycle shifts 90-110% 20 1/20 cycle shifts 95-105%, etc. Further, it is possible to easily realize a more detailed configuration that satisfies various duty control specifications.

[0034]

As described above, by providing the output waveform duty control circuit according to the present invention having a simple circuit configuration, the internal circuit configuration of the signal output circuit having the differential pair configuration, the element variation and the temperature characteristic thereof. An output signal waveform having an optimum duty can be obtained from the signal output circuit regardless of the above. In particular, in high-speed optical communication in which the influence of the duty fluctuation of the signal waveform is large, deterioration of the optical output signal waveform is prevented thereby, and thus it becomes possible to easily secure the line quality. Further, according to the present invention, in the APC circuit of the optical transmission circuit, the output power variation factor related to the duty variation of the output waveform is surely removed, so that the original function of the APC circuit is realized.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a basic configuration of an output waveform duty control circuit according to the present invention.

FIG. 2 is an operation timing chart showing an example of the operation of the output waveform duty control circuit according to the present invention in FIG.

FIG. 3 is a circuit block diagram showing an embodiment of the output waveform duty control circuit according to the present invention in FIG.

FIG. 4 is a flowchart showing an example of a control flow of the microprocessor shown in FIG.

FIG. 5 is a circuit block diagram showing another configuration example of the output waveform duty control circuit according to the present invention.

6 is a circuit diagram showing an embodiment of an optical transmission circuit using the output waveform duty control circuit according to the present invention shown in FIG.

FIG. 7 is a circuit diagram showing an example of a circuit of a differential input buffer section in an integrated optical transmission circuit.

FIG. 8 is an explanatory diagram of duty variation of an output data signal waveform according to an input data signal waveform and a reference voltage value.

[Explanation of symbols]

 1 ... Comparator 2, 3 ... Flip-flop circuit 4, 5 ... Low pass filter 6 ... Judgment circuit 7 ... Delay element

Claims (9)

[Claims] 1. A differential pair configuration in which an input signal is applied to one input and a reference voltage is applied to the other input,
The circuit that performs duty control of the output signal waveform with respect to the output signal from the signal output circuit that outputs the comparison determination signal of the input signal and the reference voltage has the same speed and a predetermined phase relationship with respect to the input signal. A delay circuit for generating a plurality of clock signals having: a plurality of clock signals triggered by the plurality of clock signals from the delay circuit and temporarily storing the output signal from the signal output circuit. A temporary storage circuit, an average value circuit for obtaining an average value of each output from the plurality of temporary storage circuits, and a difference between each average value output from the average value circuit is detected, and the difference is minimized. An output waveform duty control circuit comprising a determination circuit for controlling the reference voltage applied to a signal output circuit. 2. The determination circuit, an A / D converter that converts each average value output from the average value circuit from an analog signal to a digital signal, detects a difference between each average value output by the digital signal, A digital operation circuit that generates the reference voltage that is applied to the signal output circuit so that the difference is minimized, and D / that applies the reference voltage to the signal output circuit by converting the reference voltage from a digital signal to an analog signal. The output waveform duty control circuit according to claim 1, comprising an A converter. 3. The output waveform duty control circuit according to claim 1, wherein the temporary storage circuit is a D-type flip-flop circuit. 4. The delay circuit creates two clock signals, one clock signal and a clock signal delayed by a half cycle from the clock signal, and two temporary storages corresponding to the two clock signals. The output waveform duty control circuit according to claim 1, wherein a circuit is used. 5. The output waveform duty control circuit according to claim 1, wherein the signal output circuit is an optical transmission circuit that converts an electric signal into an optical signal and outputs the optical signal. 6. A differential pair configuration in which an input signal is applied to one input and a reference voltage is applied to the other input,
The circuit that performs duty control of the output signal waveform with respect to the output signal from the signal output circuit that outputs the comparison determination signal of the input signal and the reference voltage has the same speed and a predetermined phase relationship with respect to the input signal. A delay circuit for generating a plurality of clock signals having: a plurality of clock signals triggered by the plurality of clock signals from the delay circuit and temporarily storing the output signal from the signal output circuit. A temporary storage circuit, a first average value circuit for obtaining an average value of each output from the plurality of temporary storage circuits, an adder circuit for adding and outputting each output average value from the first average value circuit, the signal output A second mean value circuit for determining the mean value of the input signal of the circuit and providing it with a gain corresponding to the number of mean values from said first mean value circuit; A comparison circuit that compares the output levels from the adder circuit with reference to the output level from the average value circuit and controls the reference voltage applied to the signal output circuit so that they are equal to each other. Output waveform duty control circuit for. 7. The output waveform duty control circuit according to claim 6, wherein the temporary storage circuit comprises a D-type flip-flop circuit. 8. The delay circuit creates two clock signals, one clock signal and a clock signal delayed by a half cycle from the clock signal, and two temporary storages corresponding to the two clock signals. The output waveform duty control circuit according to claim 6, which uses a circuit. 9. The output waveform duty control circuit according to claim 6, wherein the signal output circuit is an optical transmission circuit that converts an electric signal into an optical signal and outputs the optical signal.