JPH088476B2 - Semiconductor integrated circuit timer circuit - Google Patents

Description

The present invention relates to a timer circuit provided inside a semiconductor integrated circuit, and is used for an auto power down timer circuit in a semiconductor memory, for example. is there.

(Prior Art) In a semiconductor memory, for example, a static random access memory (SRAM), in order to reduce power consumption, a power down state is automatically controlled after a required operation of each access. An auto power down timer (hereinafter abbreviated as APDT) circuit for setting the timing of the power down signal for control is used.

That is, for example, as shown in FIG. 8A, the pulse output from the pulse generation circuit 82 in synchronization with the change in the output of the address buffer 81 at the start of access causes the power down output signal of the APDT circuit 83 to output the pulse of the memory internal circuit. A part (address decoder 84, sense amplifier 85) is controlled to an inactive state. The operation timing in the memory of FIG. 8 (a) is shown in FIG. 8 (b).

An example of the configuration of the APDT circuit 83 is shown in FIG. 9 (a). The input signal is directly input to one input of the two-input NAND circuit 91 and a delay circuit including a plurality (even) stages of inverters 92 ... It becomes the other input of the two-input NAND circuit 91 via 93. The operation timing of the APDT circuit 83 is shown in FIG. 9 (b).

In the above memory, the power supply voltage dependency of the APDT circuit 83 and the power supply voltage dependency of the circuit system that accesses the memory cell are independent of each other. Here, the storage time in the output data latch circuit 86 is T ₁ , and the address decoder by the APDT circuit 83
The time during which the 84 and the sense amplifier 85 are controlled to the inactive state is represented by T ₂ .

Now, for example, as shown in FIG. 10, when T ₁ > T ₂ in a region where the power supply voltage is high, the accessed memory cell data is not output and a function error occurs. To avoid this, the address decoder by APDT circuit 83
84, time to control sense amplifier 85 to inactive state
If T ₂ is increased and T ₁ << T ₂ is set in a region where the power supply voltage is low, the current consumption increases.

In particular, in the case of a circuit that is accessed at high speed, a circuit system that senses a minute potential is easily affected by power supply noise, and the power supply voltage dependence of this circuit system and the power supply voltage dependence of the APDT circuit 83 are different. In many cases, the above-mentioned function error and current consumption increase.

In order to solve this problem, it is conceivable to make the power supply voltage dependencies of the two independent circuit systems as described above the same. However, the power supply voltage dependence of a circuit system is
It is determined by the transconductance gm of the transistors that make up this circuit system and the CR time constant of the load circuit, and shows a single dependency on the power supply voltage. It was very difficult to get the same gender.

(Problems to be Solved by the Invention) In the present invention, as described above, it is very difficult to match the power supply voltage dependency of the timer circuit with the power supply voltage dependency of another circuit system, and this matching is performed. If this is not the case, the problem was that, for example, the occurrence of a function error or an increase in current consumption would be solved, so that the timer circuit can be easily set to a desired delay time for each power supply voltage. It becomes possible to adjust, the power supply voltage dependency of the timer circuit and the power supply voltage dependency of other circuit systems can be easily matched, and a margin for the power supply voltage of the semiconductor integrated circuit can be ensured over a wide range. An object is to provide a timer circuit of an integrated circuit.

[Structure of the Invention] (Means for Solving the Problem) The present invention is a semiconductor integrated circuit having a timer circuit built therein, and a plurality of inverter circuits delaying an input signal for a predetermined time, and a plurality of inverter circuits delayed by these inverter circuits. A first logic circuit that takes a logical product of a signal and the input signal,
A first timer circuit having a large power supply voltage dependency in which a delay time largely changes with respect to a change in power supply voltage, a plurality of inverter circuits delaying an input signal for a predetermined time, and between each output terminal of these inverter circuits and ground. It has a connected capacitor, a second logic circuit that takes a logical product of the inverter circuit and the signal delayed by the capacitor, and the input signal, and the delay time changes from the first timer circuit to the change of the power supply voltage. A second timer circuit having a small power supply voltage dependency that slightly changes with respect to the third timer circuit;
And a logic circuit of.

The present invention is also a semiconductor integrated circuit having a timer circuit built therein, wherein a first inverter circuit delays an input signal for a predetermined time, and a logical product of the signal delayed by the first inverter circuit and the input signal. And a second inverter circuit for delaying an output signal of the first logic circuit for a predetermined time, and a logical product of the signal delayed by the second inverter circuit and the input signal. A plurality of second logic circuits are cascade-connected, a first timer circuit having a large power supply voltage dependency in which a delay time greatly changes with a change in a power supply voltage, and a third timer circuit delaying the input signal for a predetermined time. An inverter circuit, a third logic circuit that obtains the logical product of the signal delayed by the third inverter circuit and the input signal, and a third delay circuit that delays the output signal of the third logic circuit for a predetermined time. Connected to at least the output terminals of the third and fourth logic circuits, and a fourth logic circuit that performs a logical product of the signal delayed by the fourth inverter circuit and the input signal. At least one second timer circuit that is connected in cascade and that has a smaller delay time than the first timer circuit with respect to a change in the power supply voltage and that has a small power supply voltage dependency and a second timer circuit. A fifth logic circuit for taking the logical sum of the output of the first timer circuit and the output of the second timer circuit;
And a sixth logic circuit which takes the logical product of the output of the logic circuit and the input signal.

(Operation) By combining a plurality of timer circuits having different power supply voltage dependences, it becomes possible to easily adjust the timer circuit to have a desired delay time for each power supply voltage.
Therefore, it becomes easy to match the power supply voltage dependence of the timer circuit with the power supply voltage dependence of other circuit systems, and it is possible to ensure a wide margin for the power supply voltage of the semiconductor integrated circuit.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a timer circuit provided as an APDT circuit in an SRAM, for example, and this timer circuit is composed of a combination of a plurality of timer circuits (two in this example) having different power supply voltage dependencies. That is, 1 is a first timer circuit having a large power supply voltage dependency, 2 is an input signal common to the first timer circuit 1, and a second timer circuit having a smaller power supply voltage dependency than the first timer circuit 1. 2 timer circuits, 3 first
Is a logical sum circuit for calculating the logical sum of the output of the timer circuit 1 and the output of the second timer circuit 2.

In the first timer circuit 1, the input signal is directly input to one input of the two-input NAND circuit 4, and the other of the two-input NAND circuit 4 is passed through the delay circuit 6 including a plurality of (even) stages of inverters 5 ... Is configured to be an input of.

In the second timer circuit 2, the input signal is directly input to one input of the two-input NAND circuit 7, and the plurality of (even) stages of the inverters 8 ... And between the stages and the V _SS potential (ground potential) end. It is configured to be the other input of the two-input NAND circuit 7 via a delay circuit 10 composed of capacitors 9 ...

Here, each of the inverters 5 of the delay circuit 6 in the first timer circuit 1 has a circuit threshold Vth1 which is an intermediate potential (V _CC / 2) between the V _CC power supply potential and the V _SS potential, The voltage waveform of the node is as shown in FIG. Further, in this case, since the delay circuit 6 is composed of only transistors, the power supply voltage dependency of its delay time is large as shown in FIG.

On the other hand, the delay circuit in the second timer circuit 2
Each of the ten inverters 8 has a circuit threshold value Vth2 lower than V _CC / 2 for the falling edge of the input and a circuit threshold value Vth3 higher than V _CC / 2 for the rising edge of the input. Therefore, the voltage waveform of each node becomes as shown in FIG. 4, and the delay time of the delay circuit 10 in the second timer circuit 2 becomes larger than the delay time of the delay circuit 6 in the first timer circuit 1. . In this case, the delay circuit 10
Since it is composed of a transistor and a capacitor, the power supply voltage dependency of the delay time thereof is small as shown in FIG.

In addition, the inverters 8 of the delay circuit 10 in the second timer circuit 2 include an inverter having a circuit threshold value Vth2 lower than V _CC / 2 for a falling edge of the input and V _CC / for a rising edge of the input. Inverters having a circuit range value Vth3 higher than 2 may be alternately provided. Alternatively, the circuit threshold V below V _CC / 2 for input rising.
An inverter having th2 and an inverter having a circuit threshold Vth1 of V _CC / 2 may be alternately repeated.
Alternatively, V _CC / inverter having a second circuit threshold value Vth1, V _CC / 2 higher than the circuit threshold value V for the rising input
An inverter having th3 may be provided so as to be alternately repeated.

According to the timer circuit of the above embodiment, the output of the first timer circuit 1 in which the delay time has a large power supply voltage dependency as shown in FIG. 3 and the delay time in the power supply voltage dependency as shown in FIG. Since the logical sum is obtained with the output of the second timer circuit 2 having a small value, the dependency of the timer output on the power supply voltage is as shown by the solid line in FIG.
Is controlled by the output of the timer circuit 1, and is controlled by the output of the second timer circuit 2 in a region where the power supply voltage is high, and the power supply voltage dependency is adjusted as a whole.

In this way, by combining two timer circuits having different power supply voltage dependencies, it becomes possible to easily adjust the timer circuit to have a desired delay time for each power supply voltage. Therefore, it becomes easy to match the power supply voltage dependence of the timer circuit with the power supply voltage dependence of other circuit systems,
It is possible to ensure a wide margin for the power supply voltage of the semiconductor integrated circuit.

In the above-described embodiment, the timer circuit including the combination of the two timer circuits having different power supply voltage dependences is shown, but the third timer circuit having a smaller power supply voltage dependence than the second timer circuit 2 is used. Further, even if a common input is given to this and the output is logically ORed together with the output of another timer circuit, the power supply voltage dependency of the timer time can be more easily obtained as desired than in the above embodiment. Can be set.

FIG. 7 shows a timer circuit according to another embodiment capable of setting a longer timer time as compared with the above embodiment.
That is, the input is input to the two timer circuits 53 and 54 via the two-stage inverters 51 and 52. The first timer circuit 53, which is composed of only transistors, has inverters 55 and 56, a two-input NAND circuit 57, an inverter 58, a two-input NAND circuit 59, an inverter 60, and a two-input NAND circuit as shown in the figure. The circuit 61 is connected. The other second timer circuit 54 is connected to the inverters 62 and 63, the two-input NAND circuit 64, the inverter 65, the two-input NAND circuit 66, and the two-input NAND circuit 68 of the inverter 67 as shown in the figure. Has been done.

In addition, the input terminals of the inverters 65 and 67 between the stages and V
Capacitors 68 and 69 are connected between the _SS potential end and
Capacitors 70 and 71 are connected between the output terminals of the inverters 65 and 67 and the V _CC potential terminal, respectively. These two
The output of each timer circuit 53 and 54 is a two-input NOR circuit 72.
The output of the two-input NOR circuit 72 is input to the two-input NAND circuit 75 together with the input through the two-stage inverters 73 and 74.
The output of this two-input NAND circuit 75 is input to the inverter.
It is configured to be output via 76.

In the timer circuit of FIG. 7 as well, similar to the timer circuit of the above-described embodiment, by setting the power supply voltage dependence of the delay time of the two timer circuits 53 and 54 to a desired value, the desired power supply as a whole can be obtained. The voltage dependence can be obtained.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to easily adjust the timer circuit so as to have a desired delay time with respect to each power supply voltage. It becomes easy to match with the power supply voltage dependency of the circuit system, and it is possible to realize the timer circuit of the semiconductor integrated circuit which can ensure a wide margin for the power supply voltage of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a timer circuit in a semiconductor integrated circuit of the present invention, FIG. 2 is a waveform diagram showing the timing showing the operation of the delay circuit in the first timer circuit in FIG. 1, 3 is a characteristic diagram showing the power supply voltage dependency of the output of the first timer circuit in FIG. 1 of the inverter of FIG. 2, and FIG. 4 is the operation of the delay circuit in the second timer circuit of FIG. 5 is a waveform diagram showing the timing of FIG. 5, FIG. 5 is a characteristic diagram showing the power supply voltage dependence of the output of the second timer circuit in FIG. 1, and FIG. 6 is a power supply voltage dependence of the output of the timer circuit of FIG. FIG. 7 is a circuit diagram showing a timer circuit according to another embodiment of the present invention, FIG. 8 (a) is a configuration explanatory view showing a part of a conventional semiconductor memory, and FIG. b) is a waveform diagram showing the operation timing in the memory of FIG.
9 (a) is a circuit diagram showing an example of the APDT circuit in FIG. 8 (a), FIG. 9 (b) is a waveform diagram showing the operation timing of FIG. 9 (a), and FIG. FIG. 6 is a characteristic diagram showing power supply voltage dependence of a storage time T ₁ in an output data latch circuit and a time T ₂ for controlling an address decoder and a sense amplifier in an inactive state by an APDT circuit in the memory of FIG. 1, 53 ... first timer circuit, 2, 54 ... second timer circuit, 3, 72 ... logical sum circuit, 4, 7 ... two-input NAND circuit, 5, 8 ... inverter, 6, 10 ... Delay circuit, 9
……capacity.

Claims (2)

[Claims] 1. A semiconductor integrated circuit containing a timer circuit, comprising: a plurality of inverter circuits for delaying an input signal for a predetermined time;
A first timer that has a first logic circuit that takes a logical product of a signal delayed by these inverter circuits and the input signal, and that has a large power supply voltage dependency in which the delay time changes significantly with respect to changes in the power supply voltage. A circuit and a plurality of inverter circuits for delaying the input signal for a predetermined time,
And a second logic circuit that performs a logical product of the input signal and the signal delayed by the inverter circuit and the capacitance, the capacitance being connected between each output terminal of the inverter circuit and the ground, and the first logic circuit. At least one second timer circuit whose power supply voltage dependency is smaller than that of the timer circuit, the delay time of which is smaller than that of the power supply voltage, and the output of the first timer circuit and the output of the second timer circuit. And a third logic circuit for obtaining a logical sum of 2. A semiconductor integrated circuit containing a timer circuit, the first inverter circuit delaying an input signal for a predetermined time,
A first logic circuit that obtains a logical product of the signal delayed by the first inverter circuit and the input signal;
A plurality of second inverter circuits for delaying the output signal of the logic circuit for a predetermined time, and a plurality of second logic circuits for performing a logical product of the signal delayed by the second inverter circuit and the input signal are cascaded. A first timer circuit having a large power supply voltage dependency in which a delay time greatly changes with respect to a change in a power supply voltage, a third inverter circuit delaying the input signal for a predetermined time, and a delay caused by the third inverter circuit. A third logical circuit that takes the logical product of the generated signal and the input signal, a fourth inverter circuit that delays the output signal of the third logical circuit for a predetermined time, and a fourth inverter circuit that delays the output signal. A plurality of fourth logic circuits that take a logical product of a signal and the input signal, and at least a plurality of capacitors that are connected between the output terminals of the third and fourth logic circuits and the ground are cascade-connected, and At least one second timer circuit whose delay time is smaller than that of the first timer circuit with respect to the change of the power supply voltage and whose power supply voltage dependency is small; and the output of said first timer circuit and said second timer circuit And a sixth logic circuit that obtains the logical product of the output of the fifth logic circuit and the input signal. Timer circuit.