JPH0883808A - Semiconductor device - Google Patents

Abstract

PURPOSE: To improve the controllability of a threshold voltage and to reduce a gate parasitic capacity and source/gate parasitic resistance by laying out a semiconductor layer of an opposite conductive type constituting a PN junction gate on a one-conductive type active layer. CONSTITUTION: A PN junction gate consisting of n-type GaAs layer 14, undoped Al GaAs layer 15, and p-type GaAs layer 16 is formed. Then, SiN layer 20 at source and drain formation parts is selectively eliminated for SiO2 side wall 21 and is formed at a gate. Then, undoped AlGaAs layer 15 at source/drain formation parts is eliminated. Then, two n<++> GaAs layers 18 acting as source and drain which are electronically connected to the n-type GaAs active layer 14 is selectively grown and formed. Then, AuGe, W, Ni, and Au are laminated on two n<++> GaAs layers 18 in this order and source and drain electrodes are formed, thus completing an FET.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a PN junction gate FET.
The present invention relates to a semiconductor device having (field effect transistor), and particularly to a semiconductor device capable of providing a high-performance MMIC (microwave monolithic integrated circuit).

[0002]

2. Description of the Related Art In recent years, portable telephones that can be carried outdoors by individuals have become widespread, and it is conceivable to use enhancement type PN junction gate FETs in the radio wave transmission portion. The FET of this type is, for example, ICI / I Transaction / Electron, Volume E75-C,
No. 10, pp. 1110 to 1114 (IEICE
Trans. ELECTRON. , Vol. E75-
C, No. 10, p1110-p1114), and the manufacturing method thereof is as follows.

An n-type active layer and a source / drain n + type GaAs layer are formed by an ion implantation method. Then SiN
An insulating film such as is deposited, an opening is formed in the gate portion, and Zn is diffused through the opening to form a PN junction in the n-type active layer. The gate electrode metal is deposited after diffusion, and the gate electrode is formed by photolithography using dry etching.

[0004]

SUMMARY OF THE INVENTION The above prior art is based on the PN
Since the diffusion process is used to form the junction, the threshold voltage Vth
Controllability of is extremely poor.

Since a PN junction is formed in the n-type active layer, the gate parasitic capacitance (source / gate capacitance and gate / gate capacitance
Drain capacity) becomes large. In particular, the gate parasitic capacitance has a trade-off relationship with the source / gate parasitic resistance.
That is, n + type GaAs source / drain layers and p type G
In order to reduce the resistance (source / gate parasitic resistance) of the n-type GaAs active layer in the open area separating the aAs gate layer, p
When the diffusion depth of the type GaAs gate layer is reduced, the gate parasitic capacitance increases. Further, the increase in the gate / drain capacitance lowers the gains of the power amplifier and the low noise amplifier in the case of the MMIC in which the power amplifier and the low noise amplifier are formed monolithically.

As described above, the above conventional technique has the above problems. Further, this problem is not limited to the enhancement type PN junction gate FET, but has the depletion type PN junction gate FET.

It is an object of the present invention to provide a semiconductor device having a PN junction gate FET which has good controllability of threshold voltage and can reduce gate parasitic capacitance and source-gate parasitic resistance.

[0008]

The above object is to arrange a source and a drain made of a semiconductor layer of a field effect transistor on an active layer of one conductivity type, and to dispose on the active layer between opposed end faces of the source and the drain. An undoped semiconductor layer having a band gap larger than that of the active layer is arranged, a semiconductor layer of opposite conductivity type to one conductivity type is arranged on the undoped semiconductor layer away from the source and drain, and a semiconductor layer of opposite conductivity type, undoped semiconductor layer This can be achieved by forming the PN junction gate of the field effect transistor with the layer and the active layer.

[0009]

Since the semiconductor layers of opposite conductivity type forming the PN junction gate are arranged on the active layer of one conductivity type, that is, the conventional diffusion method is not adopted, the controllability of the threshold voltage is improved. good. Since the semiconductor layer of the opposite conductivity type forming the PN junction gate is separated from the source and the drain, the gate parasitic capacitance formed by these is small. A source and a drain made of a semiconductor layer are arranged on an active layer of one conductivity type, and a built-in potential φp due to a PN junction is provided.
The depletion layer at the open area is positively utilized by positively utilizing the difference in the extension of the depletion layer into the active layer due to the difference between the surface potential Φs of the active layer (open area) between n and the source and the gate. , The source / gate parasitic resistance is small. The extension of the depletion layer under the gate extends over the entire thickness of the active layer in the case of the enhancement type, and does not extend over the entire thickness of the active layer in the case of the depletion type, and a part of the active layer remains.

The reduction of the source / gate parasitic resistance will be described in detail below by taking the structure of FIG. 1 (c) as an example. n
If the concentration of the active layer 14 is ND, the film thickness is a, the permittivity is ε, and the unit charge is q, the enhancement type PN
The threshold voltage Vth of the junction gate FET is represented by Vth = Φpn-qNDa ² / 2ε ... (Equation 1).

Further, a perforated portion 70 (region 7 of the n-type active layer 14 immediately below the SiN side wall 20 and the SiO ₂ side wall 21) is formed.
0) If the thickness of the depletion layer extending inward is h, the surface potential Φs
The relationship between h and h is represented by Φs = qNDh ² / 2ε ... (Equation 2).

On the other hand, if the built-in potential of the Schottky barrier is defined as Φ _B n and the film thickness of the n-type active layer is defined as b, Vth of the enhancement type FET such as MESFET having a Schottky gate or heterojunction FET is Vth = Φ _B n-εNDb ² / 2ε ... (Expression 3)

The built-in potential Φ _B n of the Schottky junction and the surface potential Φ s are almost the same.

[0014] Therefore, in the case of the same Vth, compared to PN junction gate FET and Schottky gate FET, if the same active layer impurity concentration _{ND Φpn-Φ B n ≒ qND} (a 2 -b 2) / 2ε = 0. 7 to 1.0 V (Equation 4), and a can be considerably larger than b. That is,
PN junction gate FET is more Schottky gate FET
As a result, since the channel layer can be made thicker and the depletion layer at the open area 70 in FIG. 1 (c) can be suppressed from extending so that the sheet resistance can be made relatively small, a large amount of source / drain current flows and source / gate parasitic Resistance can be reduced. As a specific example, Vth = 0.2V, ND = 7 × 10 ¹⁷ / c
m ³ , Φpn = 1.4V, Φs = 0.7V, mobility μ =
When 3500 cm ² / Vs, SiO ₂ sidewall 2 from the above formula
It is expected that the sheet resistance ρs of the n-type active layer immediately below 1 will be around 2 KΩ / □, and it has been confirmed experimentally.

When the SiO ₂ side wall 21 is designed to have a film thickness of about 200 nm, a source / gate parasitic resistance of 40 Ω is generated for a transistor width of 10 μm, and when the n ++ type GaAs high concentration layer 18 and the source electrode are added, the transistor width 1
The source / gate parasitic resistance per 0 μm is about 70Ω, which is a sufficiently small value that can be practically used as a power FET.

On the other hand, a Schottky gate MESFET
In the case of forming an enhancement type FET with a heterojunction FET, the built-in potential Φ _B n of the Schottky junction and the surface potential Φs are almost the same, so that the sheet resistance ρs of the n-type active layer in the open area is extremely high. A depletion type GaAs MESFET having a deep threshold value and a simple process has been the mainstream of the power GaAs FET in the past, because it cannot be a practical device unless the sheet resistance ρs is lowered. In other words, conventional ME
Enhancement type FE with SFET and heterojunction FET
When making T, the sheet resistance of the open area 70 becomes several tens of kΩ / □ or more, and the impurity concentration of the n-type active layer must be raised more than the impurity concentration of the active layer of the channel layer immediately below the gate due to an ion implantation source or the like. I have no choice but to use the sauce,
The breakdown voltage of the gate and drain was deteriorated. On the contrary, when trying to secure the breakdown voltage, the device performance deteriorated.

According to the present invention, as described above, the power F
An enhancement type FET having a sufficiently low source / gate parasitic resistance that can be practically used as an ET can be realized. Also,
In the present invention, the undoped semiconductor layer (undoped AlGaAs layer 15 in FIG. 1C) having a bandgap larger than that of the active layer arranged on the active layer also contributes to the improvement of the breakdown voltage between the gate and the drain. That is, the thickness of the depletion layer extending from the drain side end of the gate is effectively increased, the electric field is relaxed, and the breakdown voltage is improved. Here, undoped means that impurity atoms are not intentionally doped. In addition, the fact that the ion implantation method is not used for forming the source and drain also contributes to the improvement of the breakdown voltage between the gate and the drain. That is, since the crystallinity is not disturbed, breakdown due to current leakage does not occur and the breakdown voltage is improved.

In FIG. 1 (c), both the P-type and N-type semiconductor layers constituting the PN junction gate are made of GaAs and made of the same material with the same band gap, but as can be easily understood from the above description. The present invention can be practiced even if one of the layers, which also functions as an active layer, is made of a material having a smaller bandgap than the other layers.

Although the N-channel FET has been described as an example, the present invention is also effective for the P-channel FET, as can be easily understood from the above description.

Although the present invention is effective for both the enhancement type and the depletion type, from the viewpoint of the power source, the enhancement type which requires only a single power source is more advantageous than the depletion type which requires two power sources. is there.

For manufacturing the semiconductor device of the present invention, MOCVD (organic metal pyrolysis method) or MBE (molecular beam epitaxy method), which has recently been established as a mass production technology, can be used.

By using the same device structure and manufacturing process as the semiconductor device of the present invention, a high-performance low noise amplifier or switch in a high frequency region having a plane configuration different from that of the semiconductor device of the present invention is monolithically integrated with the semiconductor device of the present invention. Can be configured to.

[0023]

【Example】

Example 1 An enhancement type power FET (Vth = 0.2V) using an n-type conductive layer in a channel of Example 1 of the present invention will be described with reference to FIGS. 1 (a) to 1 (c) and FIG. To do. An undoped GaAs layer 11 (thickness 500 nm) is formed on the semi-insulating GaAs substrate 10 by using the MOCVD epi growth technique.
Undoped AlGaAs layer 12 (thickness 5 nm), undoped GaAs layer 13 (thickness 50 nm), n-type GaAs layer 14 (thickness 50 nm), undoped AlGaAs layer 15
(Thickness 5 nm), p-type GaAs layer 16 (thickness 50 n
m) and a p ++ type GaAs layer 17 (thickness: 50 nm) are deposited in this order (FIG. 1 (a)). Next, although not shown, p ++
WSi, which is a high heat resistant gate metal, on the GaAs layer 17
(Thickness 50 nm), W (thickness 800 nm) and / WS
i (50 nm thick) is deposited in this order. Then WS
A protective film (thickness: 250 nm) such as SiN is formed on the i layer. The Al composition of the undoped AlGaAs layer 12 is 0.3. Usually, this composition is selected from the range of 0.1 to 0.45. A of undoped AlGaAs layer 15
Each l composition is 0.45. Usually, this composition is selected from the range of 0.42 to 0.5. n-type GaAs
The impurity concentration of the layer 14 is ND = 7 × 10 ¹⁷ / cm ³ . Usually, this impurity concentration is ND = 1-10 × 10 ¹⁷ /
It is selected from the range of cm ³ . The impurity concentration of the p-type GaAs layer 16 is NA = 2 × 10 ¹⁹ / cm ³ . p ++ Ga
The impurity concentration of the As layer 17 is NA = 5 × 10 ²⁰ / cm ³ , and its dopant is carbon (C).

Next, using the photoresist as a mask, the gate forming portion is left and the other portions are removed by the μ wave dry etching method to remove the SiN layer 22, the WSi layer 32, and the W layer 3.
1. Form the WSi layer 30. As a result, the WSi layer 30
A gate electrode composed of the / W layer 31 / WSi layer 32 is formed. Next, after removing the photoresist and cleaning, the SiN layer 2
2 and the gate electrode are used as a mask to leave the gate formation portion, and the other portions are selectively removed by RIE (reactive ion etching method) to form a p ++ type GaAs layer 17 and a p type GaA.
The s layer 16 is formed. As a result, the n-type GaAs layer 14 /
A PN junction gate composed of the undoped AlGaAs layer 15 / p-type GaAs layer 16 is formed. Regarding the impurity concentration and the film thickness of the n-type GaAs active layer 14, even if Vth is the same (Vth = 0.2V in this embodiment), according to the equation 1,
Can be changed. Next, the SiN layer 20 (thickness 50n
m) is formed by plasma CVD. Next, SiO ₂
After depositing (thickness 300 nm) by plasma CVD, S
R for which iO ₂ was used for the SiN layer 20 using CHF ₃ based gas
Selective etching is performed by IE to form a side wall 21 of SiO ₂ on the gate. The thickness of the SiO ₂ side wall 21 is 250 nm
Met. The thickness of the SiO ₂ side wall 21 is determined by the design of the withstand voltage of the source and drain, and is 100 nm to 400 nm.
It is set in the range of nm (FIG. 1 (b)).

Next, S of the source and drain forming portions
The iN layer 20 is selectively removed with respect to the SiO ₂ sidewall 21 using hot phosphoric acid having a boiling point (150 ° C.) under atmospheric pressure to form the SiN sidewall 20 on the gate. Next, undoped AlGaAs at the source and drain forming portions
Layer 15 is removed. A of undoped AlGaAs layer 15
If the l composition is selected in the range of 0.42 to 0.5, AlGaAs can be selectively removed using the buffer hydrofluoric acid (HF) at a selection ratio of 1000 or more with respect to the n-type GaAs layer 14. Next, using the MOCVD method, two n ++ GaAs layers 18 (thickness: 300 nm, N, which serve as a source and a drain, which are electrically connected to the n-type GaAs active layer 14, are used.
D = 2 × 10 ¹⁸ / cm ³ ) is selectively grown (FIG. 1C).

Next, although not shown, AuGe, W, N
The FET is completed by stacking i and Au in this order on the two n ++ GaAs layers 18 to form a source electrode and a drain electrode. Pseudomorphic InGaAs can be used as the active layer 14 to improve the device performance. That is,
20 nm to 10 nm instead of the n-type GaAs layer 14
N-type In _z Ga _1-z A with a critical film thickness or less without strain
An s layer (z = 0.1-0.2) is used. If you need more,
An n-type GaAs layer may be laminated on this layer. InGaA
Since the electron drift velocity of s is high, it becomes possible to improve the device characteristics in the vicinity of the pinch-off voltage. In order to improve the gate breakdown voltage and the drain breakdown voltage, it is possible to design the impurity concentration of InGaAs lower than that of n-type GaAs.

The gate electrode may be a single layer of W (thickness: about 600 nm) without using WSi. The sheet resistance of the gate electrode usually has a value of 0.3Ω / □ or less.

When extracting only static device characteristics,
Direct NA = 2 × 10 ¹⁹ without using the p ++ type GaAs layer 17.
The gate electrode may be brought into contact with the p-type GaAs layer 16 having a relatively low concentration of about / cm ³ . However, about 0.
When operating at a high frequency of 8 GHz or more, p ++ type Ga
The As layer 17 is necessary. When operating at a high frequency of approximately 0.8 GHz or more, the gate resistance plays an important role, so the ohmic contact resistance between the gate electrode and the P-type semiconductor layer of the PN junction is approximately 5 × 10 ⁻⁶ Ωcm ² or more. When,
The gate resistance becomes non-negligible compared to the source resistance, and as a result, the device characteristics deteriorate. To prevent this, p ++
Type GaAs layer 17 has an impurity concentration of NA = 8 × 10 ¹⁹ / c
It must be at least m ³ . In addition, the p-type GaAs layer 16
Since the impurity has a relatively low concentration of NA = 2 × 10 ¹⁹ / cm ^3, it is possible to use Be or Mg, but p
Since the impurity concentration of the ++ type GaAs layer 17 is high, carbon, which is less diffused in various thermal steps in the process steps, is essential as the dopant.

Next, a plan view of this embodiment will be described with reference to FIG. In the figure, reference numeral 60 'is a source pad, 61' is a drain pad, and 62 'and 62''are gate pads. In this embodiment, the gate electrode has a resistivity of Al or C.
Since a high heat-resistant metal that is higher than u, Au, etc. by one digit or more is used, the unit gate width of the comb-shaped gate structure is made small (unit gate width: 50 μm), and the total gate resistance is normally set (unit gate width: It is reduced to 1/4 of 100 μm). Further, the structure is such that the three source pad regions 60 'are folded back symmetrically with respect to the center line, and the size of the transistor in the unit gate arrangement direction is reduced.

The relationship between the gate resistance Rg and the size of the transistor in the unit gate arrangement direction will be described below. If the sheet resistance of the high heat-resistant gate metal is defined as ρsg, the unit gate width of the comb-shaped gate is defined as Wg, and the gate length is defined as Lg, then 2 GHz-5.
At a high frequency of GHz level, the gate resistance Rg per unit gate width (high frequency approximation) is represented by Rg = ρsgWg / (3Lg) ... (Equation 5).

When ρseff is defined as the effective sheet resistance between the source and gate electrodes and Lsg is defined as the distance between the source and gate electrodes, the source resistance Rs is expressed by Rs = ρseffLsg / Wg ... (Equation 6) It

It is desirable that the gate resistance Rg be less than or equal to the source resistance Rs or a negligible value. Gate resistance Rg
Can be reduced in principle by reducing the unit gate width Wg in the same gate width. However, if the length is too short, the number of unit gates increases and the size of the transistor in the unit gate arrangement direction becomes too large. As a result, the phases of the input signals of the unit gates at both ends are out of phase, which causes a problem that the power addition efficiency is reduced. As a solution to this problem,
A structure in which the three source pads 60 'of FIG. 2 are symmetrically folded back about the center line (the source pad is a line symmetry axis) is adopted.

The structure of the gate 62 in this embodiment has a unit gate width Wg = 50 μm and a gate length Lg = 0.5 μm.
m, four gate pads 62 ″, each gate pad 62
18 unit gates (72 in total) in a row,
The total gate width W consists of 3.6 mm. Maximum source drain current is source drain voltage Vds = 2.0V
At that time, it was 1 A (ampere). The sheet resistance of the gate electrode was ρsg = 0.18Ω / □, the gate resistance Rg per unit gate width was 6Ω, the source resistance Rs was 14Ω, and the intrinsic channel region resistance was 10Ω. On the other hand, in the case of a normal planar structure, the gate resistance R per unit gate width
g is 12Ω, source resistance Rs is 7Ω, and the resistance of the intrinsic gate region is 5Ω. As can be seen from this, the gate resistance Rg per unit gate width is smaller than the source resistance Rs and has almost no influence on the device performance.

When the size of the transistor in the unit gate arrangement direction is small, it is not necessary to adopt the folded structure as shown in FIG.

Example 2 An enhancement type power FET using a two-dimensional electron gas formed in the heterojunction interface of n-AlGaAs and u-GaAs in the channel of Example 2 of the present invention is shown in FIGS. 2 and 3 (a). ) -FIG.3 (d) demonstrates.

An undoped GaAs buffer layer 11 (thickness: 500 nm) and an undoped AlGaAs buffer layer 112 (thickness: 5 n) are formed on a semi-insulating GaAs substrate 10.
m), undoped GaAs layer 113 (thickness 50 nm),
n-type AlGaAs layer (Al composition 0.3, thickness 50 nm)
114, undoped AlGaAs layer 15 '(thickness 10n
m), p-type AlGaAs layer 19 (Al composition 0.3, thickness 50 nm), p ■■ -type GaAs layer 17 (thickness 50 nm)
Are formed in this order using MBE (FIG. 3 (a)).
The Al composition of the p-type AlGaAs layer 19 is usually selected from the range of 0.3 to 0.45.

The subsequent process is the same as in Example 1 except for the following points. In the present embodiment, in order to reduce the parasitic resistance of the source and drain electrodes 51, the wiring electrodes Mo52 and Au53 are provided in this order on the source and drain electrodes 51 facing the unit gate electrode 50 shown in FIG. 2 (FIG. )). In FIG. 3B, only one of the source electrode and the drain electrode is shown. The sheet resistance of the wiring electrode depends on the source and drain electrodes 51 (Au
Sheet resistance after alloying Ge / W / Ni / Au) is 1Ω
Since it is / □, it is about 0.1Ω / □ -0.01Ω / □. The wiring electrode material may be Al or Cu.

In this embodiment, the undoped GaAs layer 11 is used.
The two-dimensional electron gas layer (2DEG) formed at the interface with the n-type AlGaAs layer 114 of No. 3 is a channel. The n-type AlGaAs layer 114 and the two-dimensional electron gas layer are active layers. In the state in which the gate voltage is not applied, the interface portion just below the gate electrode 50 is depleted. However, the interface portion just below the SiO ₂ side wall 21 is not depleted, and the two-dimensional electron gas (2DEG) 70 ′ exists (FIG. 3 (c)). Therefore, the source / gate parasitic resistance is small.

Ga of the undoped GaAs layer 113
As Pseudomorphic
ic), the sheet resistance of 2DEG can be reduced to 1 KΩ / □, so that the source / gate parasitic resistance can be further reduced. Further, when the gate resistance adversely affects the device characteristics even when the folded structure is designed in a plane (for example, when operating at 10 GHz or higher).
For this, as shown in FIG. 3D, a low resistance metal 54, 55 is formed on the gate metal 50 to reduce the gate resistance.

Although the two-dimensional electron gas layer which is the two-dimensional carrier gas layer is used as the channel in the embodiment, the two-dimensional hole gas layer may be used as the channel.

AlInA is used as a heterojunction forming material.
Other heterojunction systems such as s / InGaAs may be used.

Third Embodiment A third embodiment of the present invention will be described below with reference to FIG. In the present embodiment, a planar structure in which the chip area is made smaller than the planar structure shown in FIG. 2 used in the first and second embodiments is adopted.

The feature is that the opposing gate pads 62 ″ in FIG. 2 are commonly used to form two gate pads 62 ″ as a whole. As a result, according to this embodiment, the lateral width of the transistor can be set to 400 μm, which is the same as in the case of the normal planar structure without being folded back by the source electrode, and the chip area can be hardly increased from the case of the normal planar structure. It is possible.

That is, in FIG. 2, the drain pad 61
Since the lengths L1 and L5 of ′ are each 100 μm, the unit gate widths L2 and L4 are each 50 μm, and the length L3 of the source and gate pads 60 ′ and 62 ″ is 200 μm, the lateral width of the transistor is 500 μm. However, in FIG. 4 of the present embodiment, since the gate pad is commonly used, the length L3 of the gate / source pad can be halved to 100 μm, and the lateral width of the transistor is 400 μm.

According to the enhancement type PN junction gate FET of the above embodiment, it is possible to realize a power FET capable of operating a low power source of about 2.0 V by a single power source, and a high performance low noise amplifier in a high frequency region and It is possible to realize an MMIC in which switches are monolithically integrated.

[0046]

According to the present invention, in particular, an enhancement type PN junction power FET using a compound semiconductor such as GaAs and capable of a single power source, and a semiconductor device in which this and a high frequency low noise amplifier are formed monolithically are provided. realizable.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a power FET according to a first embodiment of the present invention.

FIG. 2 is a plan structure diagram of a power FET according to first and second embodiments of the present invention.

FIG. 3 is a manufacturing process diagram of a power FET according to a second embodiment of the present invention.

FIG. 4 is a plan structure diagram of a power FET of Example 3 of the present invention.

[Explanation of symbols]

10 ... Semi-insulating GaAs substrate, 14, 114, 55 ... Active layer, 16, 19 ... P-type semiconductor layer, 17 ... Ohmic contact p ++-type semiconductor layer, 12, 112 ... Selective etching stopper, 15 ... Selective etching stopper the high-voltage barrier layer, 15 '... the high-voltage barrier layer, 21 ... SiO ₂
Side wall, 70, 70 '... Channel layer of source (drain) gate opening, 30, 31, 32, 50, 62 ...
Gate electrode, 51 ... Source, drain electrode, 52, 53
... Wiring electrodes, 54, 55 ... Low resistance electrodes, 60 ... Source electrodes, 60 '... Source pads, 61 ... Drain electrodes, 61
′ ... Drain pad, 62 ′, 62 ″ ... Gate pad.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/338 29/812 29/778 9171-4M H01L 29/80 L 9171-4MH

Claims (13)

[Claims] 1. A source and a drain of a field effect transistor comprising an active layer of one conductivity type and a semiconductor layer formed on the active layer, and on the active layer between opposing end faces of the source and the drain. An undoped semiconductor layer having a band gap larger than that of the formed active layer and a semiconductor layer of a conductivity type opposite to the one conductivity type formed on the undoped semiconductor layer are spaced apart from the source and the drain. The opposite conductivity type semiconductor layer, the undoped semiconductor layer and the active layer constitute a PN junction gate of the field effect transistor, and the source, the drain and the source electrically connected to the gate, respectively. A semiconductor device having an electrode, a drain electrode, and a gate electrode. 2. The semiconductor device according to claim 1, wherein the field effect transistor is an enhancement type. 3. The semiconductor device according to claim 2, wherein the undoped semiconductor layer between the source and the gate and between the drain and the gate is protected by an insulating film. . 4. The semiconductor device according to claim 3, wherein the insulating film is SiO ₂ and SiN. 5. The semiconductor device according to claim 1, wherein the field effect transistor is an N channel type, and the P
A portion of the P-type semiconductor layer forming the N-junction gate in contact with the gate electrode contains carbon (C) as an impurity atom, and the concentration of the impurity atom is approximately 6 × 10 ¹⁸ / cm ³ or more. . 6. The semiconductor device according to claim 1, wherein the active layer is a GaAs layer disposed on the side of the gate electrode and a pseudomorphic layer disposed on a side remote from the gate electrode.
A semiconductor device characterized by being a laminated body with another InGaAa layer. 7. The semiconductor device according to claim 6, wherein the impurity concentration of the InGaAs layer is lower than the impurity concentration of the GaAs layer. 8. The semiconductor device according to claim 1, wherein the active layer has a two-dimensional carrier gas layer, and the two-dimensional carrier gas layer acts as a channel of the field effect transistor. Semiconductor device. 9. The semiconductor device according to claim 1, wherein the band gaps of the semiconductor layer of the opposite conductivity type and the active layer forming the PN junction gate are larger in the semiconductor layer of the opposite conductivity type. Semiconductor device. 10. The semiconductor device according to claim 1,
A semiconductor device comprising at least one field-effect transistor having a planar structure in which the pad of the source electrode is an axis of line symmetry. 11. The semiconductor device according to claim 10, wherein the gate electrode pad has a common structure, and two drain electrode pads correspond to the common gate electrode pad. A semiconductor device comprising at least one field effect transistor. 12. The semiconductor device according to claim 1,
The active layer is an N-type GaAs layer, the source and drain are N-type GaAs layers, the undoped semiconductor layer is an undoped AlGaAs layer, and the semiconductor layer of the opposite conductivity type is a P-type GaAs layer. Characteristic semiconductor device. 13. The semiconductor device according to claim 12, wherein the Al composition of the AlGaAs is 0.42 to 0.
A semiconductor device characterized by being selected from the range of 5.