JPH0883403A - Data recording and reproducing device and its data reproducing method - Google Patents

Abstract

PURPOSE: To reduce incidence of read errors by correcting erorrs caused by vertical asymmetry in a data recording and reproducing device using heads such as MR head having vertical asymmetry and so forth. CONSTITUTION: This is a flash type A/D conversion circuit used it the data reproducing channel of a PRML system. An adjustment circuit 11 for adjusting the center voltage level of reference voltages is provided in the circuit. In the case where vertical asymmetry is present in analog read data being an input signal from an MR head, errors of sampling bits caused by vertical asymmetry are corrected by adjusting the adjustment circuit 11 and consequently correct digital data DRD are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording / reproducing apparatus for use in, for example, a magnetic disk device, and more particularly to an MR head and a PRML data reproducing system.

[0002]

2. Description of the Related Art In recent years, especially hard disk devices (HD
In the magnetic disk device such as D), the recording density of the data recorded on the disk is increased with the increase of the storage capacity. As a technique for realizing this high recording density, P
RML (Partial Response Maxi)
There is a signal processing technique of a data reproduction system called a um Likelihood method.

The PRML system is a PR (Partial)
Response) waveform equalization method and ML (maximum likelihood) decoding method in combination, and is superior in S / N characteristics to the conventionally known peak detection method.

The PRML data reproducing apparatus is an HDD
When applied to, the analog signal (read data) read from the head is amplified by a preamplifier consisting of an automatic gain control amplifier (AGC amplifier) and converted into digital data by an A / D conversion circuit via a low pass filter (LPF). Convert. This digital data is equalized by a PR waveform equalizer circuit (PR equalizer),
terbi) The decoder executes the decoding process.

As the A / D conversion circuit, a 6-bit flash type (parallel type) which is excellent in high speed is usually used. As shown in FIG. 5, in the flash type A / D conversion circuit, a full-scale reference voltage Vre is supplied to both ends of the reference resistors R0 to R63, and the reference voltage equally divided by 64 comparators C0 to C63. Vre is compared with the analog input signal (analog read data ARD). Further, the encoder 10 encodes the sampling bits output from each of the comparators C0 to C63 and converts them into 6-bit (BIT0 to 5) digital read data DRD.

On the other hand, as a head for reading data from a recording medium (disk), an MR (magnetore) is used.
Attention has been paid to a magnetoresistive head (hereinafter referred to as MR head) called a "sitive" type. Since the MR head has excellent S / N characteristics as compared with the conventional inductive (inductive) head, it is possible to realize high data recording density together with the signal processing technology of the PRML system. MR
Since the head is exclusively for reading data, the HDD uses a composite type head in which a thin film head for writing data and an MR head are combined.

3 and 4 are graphs showing the output characteristics of the MR head. Each diagram (A) is a continuous isolated waveform diagram, and each diagram (B) is a waveform diagram in which isolated waveforms are superimposed. As shown in FIG. 3B, it is well known that the MR head becomes vertically asymmetric in the positive / negative level range of the output level. As a specific example, a vertical asymmetry such that the positive side level at the sample point (9) is “1.0”, while the negative side level at the sample point (11) is “0.9”. Indicates.

In the PRML data reproducing apparatus, the MR
Since the amplitude value of the read signal output from the head is sampled and converted into digital data, the error between the upper and lower sampling values is more likely to cause an error in the read data. On the other hand, the conventional well-known peak detection method is a method based on the detection of the peak position of the read signal, and therefore the vertical asymmetry of the MR head does not become a serious problem.

[0009]

In a data recording / reproducing apparatus such as an HDD, it is possible to increase the data recording density by applying a PRML type data reproducing apparatus and an MR head. However, since the MR head has the vertical asymmetry as described above, it causes a read error in the PRML type data reproducing apparatus that samples the amplitude value of the read signal.

An object of the present invention is to provide an MR having vertical asymmetry.
In a data recording / reproducing apparatus using a head such as a head, it is intended to correct an error caused by vertical asymmetry and reduce a read error occurrence rate.

[0011]

According to the present invention, in a data recording / reproducing apparatus provided with a head such as an MR head having vertical asymmetry and a data reproducing channel of PRML system, a flash capable of adjusting a central voltage level of a reference voltage. Type A /
This is a device having a D conversion circuit. This flash type A /
The D conversion circuit converts analog read data read by the head into digital data having a predetermined number of bits.

[0012]

According to the present invention, the analog read data read by the head has vertical asymmetry in which an error occurs in the positive and negative levels. When converting the vertically asymmetrical read data into digital data by the flash type A / D conversion circuit, the center voltage level of the reference voltage is adjusted according to the error between the positive and negative levels to correct the error in the digital data. Therefore, even if the read data has vertical asymmetry, accurate digital data can be obtained.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit diagram showing a configuration of a flash type A / D conversion circuit used for a PRML system data reproduction channel according to the embodiment, and FIG. 2 is a main part of a PRML system data reproduction channel according to the embodiment. It is a block diagram shown. (Structure of PRML Data Reproduction Channel) In this embodiment, an H head using a read-only MR head having a disk as a recording medium and reading data from the disk is used.
In the DD, it is assumed that a data recording / reproducing circuit system uses a PRML system data reproducing channel.

As shown in FIG. 2, the PRML data reproduction channel includes an automatic gain control amplifier (AGC amplifier) 2, a low-pass filter (LPF) 3, an A / D conversion circuit 4, a PR waveform equalization circuit (PR equalizer). ) 5 and a decoder 6.

The AGC amplifier 2 is an analog read data AR which is an analog signal output from the MR head 1 according to the gain control amount given from the gain control circuit 8.
Amplify the amplitude of D. The gain control circuit 8 outputs a gain control amount based on the output data output from the PR equalizer 5 so that the output amplitude of the AGC amplifier 2 becomes constant. Specifically, the gain control circuit 8 detects the amplitude difference generated between the tracks on the disc based on the output data from the PR equalizer 5, and obtains a gain control amount that eliminates this amplitude difference. The LPF 3 is a filter for removing high frequency noise from the analog signal output from the MR head 1.

The A / D conversion circuit 4 is a constituent element of the present invention, and has a flash (parallel) A / D conversion circuit as a basic structure as will be described later, and adjusts the center voltage level of the reference voltage. The adjusting circuit 11 is provided (see FIG. 1). The A / D conversion circuit 4 converts the analog signal output from the LPF 3 into digital data.

The PR equalizer 5 is a PR (Partia).
l Response) characteristic (intersymbol interference)
It is a digital filter that executes R waveform equalization processing.
The decoder 6 is a Viterbi decoding circuit called an ML (Maximum Likelihood) decoding method. Viterbi (vi
The terbi) decoding circuit is a maximum likelihood estimation decoding circuit that detects a maximum likelihood data sequence from the PR equalized code data based on the Viterbi algorithm.

In the A / D conversion circuit 4, the reference voltage is controlled by the offset control circuit 7 so that the input offset amount is eliminated. The offset control circuit 7 is based on the output data from the PR equalizer 5 and the A / D conversion circuit 4
The input offset amount of is detected, and the reference voltage is controlled so as to remove this detected amount. The input offset amount is an error between the center voltage level of the reference voltage and the common voltage level of the analog input signal waveform.

Further, the data reproduction channel supplies a sampling clock of the A / D conversion circuit 4, and a PLL (ph) for supplying each timing clock of the PR equalizer 5, the decoder 6, the offset control circuit 7, and the gain control circuit 8.
an as-locked loop) circuit 9. P
The LL circuit 9 generates a clock synchronized with the output data of the PR equalizer 5 by a phase locked loop and supplies it as the sampling clock and the timing clock. (Structure of A / D conversion circuit 4) The A / D conversion circuit 4 of the embodiment is a flash type (parallel type) A for converting analog read data ARD into 6-bit digital data DRD.
As shown in FIG. 1, the A / D conversion circuit is basically configured and includes an adjustment circuit 11 for adjusting the center voltage level of the reference voltage. The basic configuration of the A / D conversion circuit 4 is that the serial reference resistors R0 to R63 whose both ends are supplied with the full-scale reference voltage Vre, and the comparators that compare the equally divided reference voltage Vre with the analog read data ARD. C0
Encoder 10 that converts the sampling bits output from C63 and each comparator C0 to C63 into 6-bit (BIT0 to 5) digital read data DRD
Have.

The adjusting circuit 11 has a charging current control circuit 11a and a discharging current control circuit 11b,
Either the charging current control circuit 11a or the discharging current control circuit 11b is turned on by a control signal AC supplied from the outside (for example, a HDD control circuit). This adjusting circuit 11 is A /
Adjust the center voltage level of the reference voltage of the D conversion circuit 4,
It is a correction means for correcting the error of the sampling bit due to the asymmetry of the R head 1. The sampling bit is an output bit (64 bits) of each comparator C0 to C63.
A bit).

Next, the operation of the embodiment will be described. (Basic operation of data reproduction channel) In the HDD, read data A read from the disk by the MR head 1
The amplitude of the RD is maintained constant by the AGC amplifier 2, high frequency noise is removed by the LPF 3, and the A / D
The conversion circuit 4 converts the digital data DRD.

The digital data DRD is decoded by the PR equalizer 5 and the decoder 6 of the digital processing system. That is, P which gives the PR characteristic by the PR equalizer 5
R waveform equalization processing is executed. Further, the Viterbi decoding circuit 6 detects the maximum likelihood data series and outputs it as decoded data. (Operation of A / D conversion circuit 4) Here, as described above,
As shown in FIG. 3, the MR head 1 has vertical asymmetry in which an error occurs in the positive and negative levels of the output signal waveform.
The A / D conversion circuit 4 samples the read signal waveform (analog read data ARD) from the MR head 1 and outputs sampling bits (64 bits) from the comparators C0 to C63.
A bit).

Assuming now that the MR is as shown in FIG.
When the read signal waveform from the head 1 is vertically symmetrical, if the 32nd bit of the sampling bit of the A / D conversion circuit 4 is set to the amplitude "0" of the read signal waveform, 33
The bit and subsequent bits have a positive amplitude of the read signal waveform, and the bits 31 and before have a negative amplitude of the read signal waveform.

Furthermore, if the amplitude corresponding to the absolute value "1" of the read signal waveform is set to 16 bits, the data "+"
1 "becomes" 32 + 16 = 48 bits ", and the data"-"
1 "is" 32-16 = 16 bits ".

In such a specification, when a read signal waveform that is asymmetrical in the vertical direction is input to the A / D conversion circuit 4, positive level data "+1" is erroneously detected as "49 bits" or negative level data is detected. There is a possibility of erroneously detecting "-1" as "17 bits".

Therefore, in the present invention, as shown in FIG.
Center voltage level of reference voltage (32 sampling bits
An adjustment circuit 11 is provided which adjusts the 1-bit amplitude of the upper or lower sampling bit corresponding to the positive or negative level of the read signal waveform by adjusting the (bit number) to correct the error detection of the sampling bit.

As a concrete example, as shown in FIG.
In the case of a vertically asymmetrical read signal waveform in which the amplitude on the positive level side (upper side) is large and the amplitude on the negative level side (lower side) is small, the discharge current control circuit 11b is turned on by the control signal AC. As a result, the center voltage level (potential of the reference resistor 32) is lowered, and 3
The potential difference between both ends of the reference resistor that determines the reference voltage level of the third bit and thereafter becomes large. Therefore, when read signal waveforms having the same amplitude are input, the sampling bit is reduced by, for example, one bit amplitude. For example, even if the positive level data "+1" is detected as "47 bits" and the negative level data "-1" is detected as "17 bits", the vertical asymmetry can be resolved. As a result, in the digital data DRD output from the A / D conversion circuit 4, so to speak, an error due to vertical asymmetry is corrected.

In this way, when the amplitude value of the read data ARD output from the MR head is sampled and converted into digital data DRD of predetermined bits (6 bits) by the flash type A / D conversion circuit 4. The adjustment circuit 11 for adjusting the center voltage level of the reference voltage can correct the error due to the vertical asymmetry of the read data ARD. That is, by adjusting the 1-bit amplitude of the upper or lower sampling bit corresponding to the positive / negative level of the read signal waveform which is the read data ARD, the A / D
The error detection of the sampling bit of the conversion circuit 4 can be corrected.

Therefore, even when the vertically asymmetrical read data ARD due to the characteristics of the MR head is output, it is possible to correct the error due to the vertically asymmetrical and obtain accurate digital data DRD. As a result, in an HDD or the like that uses an MR head as a read-only head and uses a PRML type data reproduction channel, it is possible to greatly reduce the occurrence of read errors during a read operation for reproducing data from a disk. Become.

[0030]

As described above in detail, according to the present invention, in a data reproducing / recording apparatus such as a magnetic disk apparatus, particularly when a PRML system data reproducing apparatus and an MR head are applied, the data is read by the MR head. When converting the analog read signal into digital data, it is possible to correct the error due to the vertical asymmetry of the MR head and obtain digital data of an accurate value. Therefore, as a result, it is possible to significantly reduce the occurrence of read errors due to the vertical asymmetry of the MR head. This allows PRML
It is possible to realize a highly accurate data reproducing / recording apparatus having a high recording density and a low read error occurrence rate by applying the data reproducing apparatus of the method and the MR head.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a flash type A / D conversion circuit used for a data reproduction channel of a PRML system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a PRML data reproduction channel according to the first embodiment.

FIG. 3 is a read signal waveform diagram for explaining the characteristics of the MR head according to the embodiment.

FIG. 4 is a read signal waveform diagram for explaining characteristics of the MR head according to the embodiment.

FIG. 5 is a circuit diagram showing a configuration of a conventional flash type A / D conversion circuit.

[Explanation of symbols]

1 ... MR head, 2 ... AGC amplifier, 3 ... Low-pass filter, 4 ... Flash type A / D conversion circuit, 5 ... PR waveform equalization circuit (PR equalizer), 6 ... Decoder (Viterbi decoding circuit), 7 ... Offset Control circuit, 8 ... Gain control circuit, 9 ... PLL circuit.

Claims (5)

[Claims] 1. A data recording / reproducing apparatus having a head having vertical asymmetry in which the positive and negative levels of analog read data read from a recording medium are asymmetric, and decoding the read data read from the head. A flash type A / D conversion circuit for comparing the signal level of the read data with a reference voltage and converting it into digital data having a predetermined number of bits, and a central voltage level of the reference voltage of the flash type A / D conversion circuit is adjusted. Then, the data recording / reproducing apparatus is provided with a correcting means for correcting an error of the digital data due to the vertical asymmetry. 2. A data recording / reproducing apparatus which has a head for outputting analog read data read from a recording medium and which decodes the read data read from the head, wherein the read data output from the head To a digital data having a predetermined number of bits, the flash A / D conversion circuit having a plurality of comparators for comparing the signal level of the read data having a predetermined positive and negative level range with a reference voltage. When the positive / negative level of the read data is asymmetric, the correction means for adjusting the sampling bit resolution of the flash type A / D conversion circuit according to the error of the positive / negative level to correct the error of the digital data. Characteristic data recording / reproducing apparatus. 3. A reference voltage level having a number of comparators according to a predetermined number of bits of digital data, each comparator dividing an analog input signal level consisting of a predetermined positive / negative level range and a reference voltage having a predetermined scale. A flash A / D conversion circuit for comparing the comparison result and encoding the comparison result and outputting the predetermined number of bits of the digital data, wherein a center voltage level of a reference voltage having the predetermined scale is varied, A flash type A / D conversion circuit comprising an adjusting means for adjusting a resolution of a sampling bit corresponding to an upper range or a lower range of the reference voltage level with respect to a center voltage level. 4. A magnetoresistive head having vertical asymmetry in which the positive and negative levels of analog read data read from a recording medium are asymmetric, and the read data read by this magnetoresistive head is recorded in a PRML system. In a data recording / reproducing apparatus for decoding by a data reproducing process, a flash type A / D conversion circuit for converting the analog read data read by the magnetoresistive head into digital data having a predetermined number of bits, and the flash type. The center voltage level of the reference voltage of the A / D conversion circuit is adjusted, the resolution of each sampling bit corresponding to the upper voltage level and the lower voltage level with respect to the center voltage level is adjusted, and the digital data associated with the vertical asymmetry is adjusted. And a correction means for correcting the error of Reproducing apparatus. 5. A head having vertical asymmetry in which positive and negative levels of analog read data read from a recording medium are asymmetric, and a flash type A / D conversion circuit for converting the read data into digital data having a predetermined number of bits. In a data recording / reproducing apparatus provided with, when the positive / negative level of the read data is asymmetric, the center voltage level of the reference voltage of the flash type A / D conversion circuit is adjusted so as to adjust the sampling bit resolution according to the error of the positive / negative level. The step of adjusting, the step of outputting the digital data of the predetermined number of bits corresponding to the positive / negative level of the read data from the flash type A / D conversion circuit according to the adjusted sampling bit resolution, and the output digital data The read data decrypted from And a data reproducing method comprising the steps of: