JPH0883216A - Information processor and its method - Google Patents

Abstract

PURPOSE: To make possible the efficient consitency holding operation of a cache by providing a means which temporarily stores caching information in the center where respective clusters are connected. CONSTITUTION: A coupled network controller 104 judges the kind of a packet sent from a cluster; when the packet is a multicast request including directory information, the access is multicast to clusters recorded in the directory and the contents of an ICC 106 are updated. Further, when the sent packet is multicast request packet containing no directory information or a line connection request packet, the ICC 106 is checked; when there are target contents in an ICC 10, the access is multicast to clusters recorded in the directory and the contents of the ICC 106 are updated. When the contents of the ICC 106 are not present, the directory request packet is sent out to a cluster having a memory and a directory packet from the cluster is expected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method for performing cache coherency holding operation in a cluster type information processing apparatus.

[0002]

2. Description of the Related Art Conventionally, in a cluster type multiprocessor system, when it is attempted to maintain cache coherency by a directory method, a method for arranging a directory for storing caching information is one such as the central part of the system.
There are a method of centrally arranging them in one place, and a method of arranging them dispersedly in each cluster. The centralized arrangement has an advantage that the cost required for searching the caching information is uniform in each cluster. In the case of the distributed allocation method, it is common to allocate directories corresponding to memory fragments (a part of the shared memory in the system) existing in the cluster to the cluster. Depending on the caching state of the data block, there is the advantage that the access can be closed entirely within the cluster.

[0003]

However, when the directories are centrally arranged, it is necessary to search the central directory for each access to the cacheable area, and the access is concentrated. There is a problem that it can become a neck. In addition, when trying to increase the shared memory capacity in the system by increasing the number of clusters, etc., it is necessary to increase the directory capacity, and this is accompanied by a hardware limitation (number of stackable ICs, etc.) There is a problem that it is inferior to.

When the directories are distributed, the scalability is excellent, but when the access destination is a data block existing in another cluster, the cost required to check the caching state by accessing the directory is high. There is.

[0005]

Means (and Action) for Solving the Problems
In order to solve the above-mentioned problems, a cluster type information processing device that maintains cache coherency by a directory method and disperses and arranges directories for storing caching information, and stores the caching information for the directories of each cluster. There is provided an information processing device comprising: a means and a coherency holding means for performing a coherency holding operation of a cache by using the stored caching information. In order to solve the above problems, the present invention is preferably characterized in that the storage means is associated with the consistency holding means. In order to solve the above-mentioned problems, the present invention is preferably characterized in that the storage means can store a plurality of caching information. In order to solve the above-mentioned problems, the present invention is preferably characterized in that each of the clusters further includes a transmission means for transmitting packet data via a line. In order to solve the above problems, the present invention is an information processing method for a cluster-type information processing apparatus that maintains cache coherency in a directory system and dispersively arranges directories for storing caching information. It is determined whether or not the received packet includes directory information. If it is determined that the packet includes the directory information, the access is multicast to the cluster stored in the directory, and it is determined that the packet does not include the directory information. In this case, there is provided an information processing method characterized by reading the directory information from the storage means for storing the caching information of the directory and multicasting the access to the clusters stored in the directory.

[0006]

1 is a block diagram of a cluster type multiprocessor system including the present invention.

Although the present embodiment has a four-cluster configuration, any number of clusters may be used. This is not a limitation of the present invention.

Reference numeral 100 is a cluster 0, 101 is a cluster 1, 102 is a cluster 2, and 103 is a cluster 3.
Reference numeral 104 is a connection network control device, 105 is a switch for switching connections between clusters, and 106 is an I for temporarily storing caching information in a directory existing in each cluster.
CC (: Intercluster Cachingi
information cache).

Reference numeral 107 is a signal line connecting the cluster 0 (100) and the connection network control unit (104), and includes a use arbitration signal of the connection network and information on access. Similarly, 108 is the cluster 1 (101) and the connection network control device (10
4), a signal line 109 connecting the cluster 2 (102) and the connection network control device (104), and a signal line 110 connecting the cluster 3 (103) and the connection network control device (104). is there. Reference numeral 111 is a signal line connecting the cluster 0 (100) and the switch (105), and a signal such as an address and data is transmitted during the inter-cluster access. Similarly, 112 is a signal line connecting the cluster 1 (101) and the switch (105), and 113 is the cluster 2 (10).
2 is a signal line connecting the switch (105) and 114 is a signal line connecting the cluster 3 (103) and the switch (105).

FIG. 2 is a block diagram of a cluster. Although this figure shows the cluster 0 (100), each cluster has the same configuration in this embodiment.

Reference numeral 200 denotes a processor that executes processing in accordance with programs stored in the memory 202 or the like. A cache memory 201 temporarily stores data processed by the processor 200. 202
Is memory, which is set as part of the shared memory in the system. A directory manager 203 manages the directory 204. The directory manager 203 has a packet transmission unit and a packet reception unit (not shown). Reference numeral 204 is a directory. A network interface 205 is an interface with the connection network. 206 is a directory manager (203) and a network
It is a signal line connecting to the interface (205). 20
A bus 7 connects the modules in the cluster to each other.

FIG. 3 shows each cluster (100/101/10).
2 shows the breakdown of the signal line (107/108/109/110) connecting the network controller (2/103) and the connection network control device (104).

REQ is for each cluster (100/10/1/1)
02/103) is a signal line for requesting the connection network control device (104) to use the connection network. USE is a signal line indicating that each cluster (100/101/102/103) is using the connection network for the connection network control device (104). TYPE0 and TYPE1 are signal lines indicating the type of access by each cluster (100/101/102/103) to the connection network control device (104). The type of access is shown in FIG. TYPE
When 0 is the 0th signal line and TYPE1 is the 0th signal line, it is a read instruction. If TYPE0 is the first signal line and TYPE1 is the 0th signal line, it is a write instruction. If TYPE0 is the 0th signal line and TYPE1 is the 1st signal line, re
This is an ad with intent to modify instruction, and is a transaction to be issued when a write error occurs. TYPE0 is the first signal line, TY
If PE1 is the first signal line, it is a purge instruction, and is a transaction that is explicitly invalidated by the software when hit by write. A0 to A3
Reference numeral 1 is a signal line indicating an address at which each cluster (100/101/102/103) attempts to access the coupled network control device (104). SIZ0 and SIZ1 are signal lines indicating the size at which each cluster (100/101/102/103) tries to access the connection network control unit (104). As shown in FIG. 3B, when the size is 0th signal of SIZ0 and the 0th signal of SIZ1, the access size is 1 byte.
In addition, SIZ0 is the 0th signal and SIZ1 is 1
In the second case, the access size is 2 bytes. S
When IZ0 is the first signal and SIZ1 is the 0th signal, the access size is 4 bytes. If SIZ0 is the first signal and SIZ1 is the first signal,
The access size is 32 bytes.

GRT is a signal line indicating that the connection network control unit (104) permits each cluster (100/101/102/103) to use the connection network. OPR
Is the connection network control device (104) for each cluster (100/1
01/10/103) is a signal line for instructing an operation. In OPTTYPE0 and OPTYPE1, the connection network control unit (104) controls each cluster (100/10
This is a signal line indicating an operation to be performed on 1/102/103).

In FIG. 3 (c), the connection network control device (104) is used for each cluster (100/101/102/1).
03), the signal line indicating the operation to be performed is shown. The OPTYPE0 signal is the 0th and OPTYPE1
, The connection network control circuit checks the cluster, and the OPTYPE0 signal is the 0th signal.
When the signal of PTYPE1 is the first signal, the connection network control circuit invalidates the cluster, and
When the signal of PTYPE0 is the first and the signal of OPTYPE1 is the 0th, the connection network control circuit writes back each cluster, the signal of OPTYPE0 is the first, and the OPTY is OPTY.
When the signal of PE1 is the first, it is a signal for the ICC to load the miss directory.

In OPA0 to OPA31, the connection network control unit (104) operates in each cluster (100/101/102/1).
03) is a signal line indicating a data block to be operated. CINFO0 to CINFO3 are connected network control device (104) and each cluster (100/101/102).
/ 103) is a signal line used for exchanging caching information.

FIG. 4 is a block diagram of the connection network control device (104). Reference numeral 400 denotes a microcontroller that performs an arbitration operation for the connection network and a cache coherency holding operation.
Reference numeral 401 is a signal line buffer with the cluster 0 (100), 402 is a signal line buffer with the cluster 1 (101), 403 is a signal line buffer with the cluster 2 (102), and 404 is It is a buffer for the signal line to and from the cluster 3 (103). 405 is cluster 0 (100)
, 406 is from cluster 1 (101), 407 is from cluster 2 (102), and 408 is from cluster 3 (10).
3) Signal lines that indicate to the microcontroller (400) that requests for use of the connection network have come from each. 40
9 is a bus connecting the buffers (401 to 404) and the microcontroller (400), and 410 is an ICC (10
A bus 411 connecting 6) and the microcontroller (400) is a control line for setting connection of the switch (105) after the arbitration operation.

FIG. 5 is a block diagram of the ICC (106).
The ICC in this embodiment adopts a direct map type associative system, but this configuration may be a set associative system or a full associative system, and does not limit the present invention. 500 is a valid bit, a tag memory for storing an address tag, 501 is a comparator for determining hit / miss, 502 is an ICC indicating in which cluster a data block is cached.
This is the data section. Reference numeral 503 is a data buffer, 504 is a data signal line, and 505 is an address signal line.

The cache coherency maintaining operation according to the present invention will be described below. As an example, cluster 0 (10
Consider the case where the processor (200) of 0) accesses the data block A in the memory (202) of the cluster 3 (103).

Cluster 0 (100) processor (20
0) accesses the associated cache memory (201) when accessing. If there is a read hit to the cache here, or EXCLUSIV
When there is a write hit to a data block in the E state,
Access is complete. If there is a cache miss or a write hit to a SHARED data block, the corresponding access is issued on the bus (207). Since the access is to a data block outside the cluster, the network interface (205) accordingly initiates an intercluster access operation. The network interface (205) of the cluster 0 (100) uses the signal line (107) to control the use of the connection network together with access information to the connection network controller (10).
4) request. The microcontroller (400) of the connection network control unit (104) knows that a request to use the connection network is received from the cluster 0 (100) by asserting the signal line (405), and then, via the bus (409). Read access information. Micro controller (400)
Accesses the ICC (106) using the read access information. If you hit ICC here, that is, IC
If the cache information of the data block that the cluster 0 (100) is trying to access is stored in C, the consistency maintaining operation according to the cache information is started. If you make a mistake in ICC, that is, ICC
If the caching information of the data block that the cluster 0 (100) is trying to access is not stored in the cluster 0 (100), the data block of the data block stored in the directory (204) for the cluster 3 (103) is stored. Request caching information via signal line (110). In the cluster 3 (103), the directory manager (20
3) receives the request, reads the caching information of the data block by accessing the directory (203) using the received address, and reads the network interface (205) and the signal line (110).
The caching information is passed to the connection network control unit (104) via the. When the signal line 408 is asserted, the microcontroller (400) of the connection network control unit (104) knows that the requested caching information has come from the cluster 3 (103), and sends it via the bus (409). Is written and written to the ICC (106) via the bus (410), and a consistency maintaining operation according to the caching information is started. That is, when the access issued by the cluster 0 (100) is a read access, the write-back of the data block in the DIRTY state to the main storage device for the cluster caching the data block and the EXCLUSIVE state are performed. Data block S
Request state change to HARED state. After this operation is completed, the changed caching information such as adding to the caching information of the block with the cluster 0 (100) as the caching destination is used as the ICC (106) and the cluster
An operation for writing in the directory (204) of (103) is performed, and the setting of the switch (105) is changed using the switch control line (411) to access the cluster 0 (100).

Hereinafter, the processing of the cache coherency maintaining operation according to the present invention will be described in detail with reference to the flowcharts of FIGS. 6, 7 and 8.

FIG. 6 is a flowchart of the packet transmission unit in the directory manager in the cluster. In step S601, the packet transmission unit detects a bus access to the bus 207 (including cache maintenance). In step S602, it is determined whether the detected bus access is a memory in the self cluster. If it is an access to the memory in the self cluster, step S603.
Suppresses the response of the memory in the local cluster. While suppressing the response of the memory, the processes of steps S604 to S608 are executed. In step S604, the directory is referenced, and in step S605 it is determined whether or not the data is cached in another cluster. If not, the process proceeds to step S608. If cached, a multicast request is sent to the connection network control device together with the contents of the directory in step S606. Then, in step S607, it waits for a multicast completion packet from the connection network control device. When the multicast is completed, the directory is updated in step S608, and the response suppression of the memory is released in step S609. Step S
When it is determined in 602 that the bus access is not for the memory of the self cluster, it is determined in step S610 whether the bus access is cache maintenance information. A multicast request packet is sent to the network control device. Then, in step S613, the access retry is canceled.
Through the above processing, the processing of the packet transmission unit of the directory manager 203 is executed.

FIG. 7 is a flow chart of the connection network control device. In step S701, the packet sent from the cluster is waited for. In step S702, the type of the packet sent is determined, and if it is determined that the packet is a multicast request packet including directory information, the processes of steps S703 to S706 are skipped and the process of step S707 is executed. . If the received packet is a multicast request packet or a line connection request packet that does not include directory information in step S702, the process proceeds to step S703. In step S703, the ICC is checked, and if the intended content is present in the ICC, step S703
Steps S705 and S705 are skipped.
The process moves to 07. If the ICC has no contents in step S704, the directory request packet is sent to the cluster having the memory in step S705, and the directory packet from the cluster is waited in step S706. Then, the process proceeds to step S707. Step S
At 707, the access is multicast to the cluster recorded in the directory. Then, in step S708, the ICC is updated. In step S709, it is determined whether the type of packet is a line request packet. If it is a line request packet, the line is connected in step S710, and if it is not a line request packet, the process waits for the next packet.
FIG. 8 is a flowchart of the packet receiving unit inside the directory manager in the cluster. Step S8
A packet is waited for at 01, and the type of packet received at step S802 is determined. If the packet is a cache maintenance packet, the process proceeds to step S804, and access information is output to the bus according to the packet in step S804. Then, in step S805, the access result is sent to the connection network control device. Step S
If the packet type is a directory request packet in 802, the directory is accessed and output to the connection network control device.

[0024]

As described above, according to the present invention, the IC
If the directory and its contents exist in C, the cost required to maintain the cache coherency can be mitigated as compared with the method of simply arranging the directories. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a cluster type multiprocessor system in which the present invention is implemented.

FIG. 2 is a configuration diagram of a cluster.

FIG. 3 is a diagram of a signal line connecting each cluster and a connection network control device.

FIG. 4 is a configuration diagram of a connection network control device.

FIG. 5 is a configuration diagram of an ICC.

FIG. 6 is a flowchart of a packet transmission unit in the directory manager.

FIG. 7 is a flowchart of a connection network control device.

FIG. 8 is a flowchart of a packet receiving unit in the directory manager.

[Explanation of symbols]

100, 101, 102, 103 cluster 104 coupling network control device 105 switch 106 ICC (: Intercluster Caching information
Cache) 107, 108, 109, 110 Signal line connecting the cluster and the connection network control device 111, 112, 113, 114 Signal line connecting the cluster and the switch 200 Processor 201 Cache memory 202 Memory 203 Directory manager 204 Directory 205 Network interface 206 Signal line connecting the directory manager and network interface 207 Bus in cluster 400 Micro controller 401, 402, 403, 404 Signal line buffer 405, 406, 407, 408 Micro controller for signal arrival from cluster Signal line 409 for notifying to the bus Bus connecting the signal line buffer with each cluster and the microcontroller 410 Signal connecting the ICC and the microcontroller 500 address signal lines from the data signal line 505 the microcontroller tied a tag memory 501 comparator 502 data memory 503 buffer 504 microcontroller

Claims (5)

[Claims] 1. A cluster-type information processing device for maintaining coherency of a cache by a directory method and distributively arranging directories for storing caching information, and storage means for storing the caching information of directories of each cluster, An information processing apparatus, comprising: a coherency maintaining unit that performs a cache coherency maintaining operation using the stored caching information. 2. The information processing apparatus according to claim 1, wherein the storage unit is associated with the consistency holding unit. 3. The information processing apparatus according to claim 1, wherein the storage unit can store a plurality of pieces of caching information. 4. The information processing apparatus according to claim 1, wherein each of the clusters further includes a transmission unit that transmits packet data via a line. 5. A method of processing information in a cluster-type information processing apparatus, wherein cache consistency is maintained by a directory method, and directories for storing caching information are distributed and arranged, wherein a packet sent from a cluster is directory information. If it is determined that the directory information is included, the access is multicast to the cluster stored in the directory, and if the directory information is not included, the directory caching is performed. An information processing method comprising: reading directory information from a storage unit that stores information, and multicasting access to clusters stored in the directory.