JPH0879272A - Data queuing device - Google Patents

Abstract

PURPOSE: To provide a cell exchange device for housing the interfaces of different speeds using a queuing device with a retrieval function. CONSTITUTION: This device is provided with destination display bits 5 for writing data inputted to an input line 1 in shift memories 4 regardless of a destination and indicating the destination of the data corresponding to the shift memories, output data are retrieved in the order of arrival corresponding to output lines by retrieval circuits and they are outputted by selectors 7. Since a retrieval instruction means 100 instructs the retrieval timing of the retrieval circuits 6, the output frequency of the data are changed corresponding to the output lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention temporarily stores information of a frame structure in which various kinds of multimedia information such as voice, data and images are blocked, and finite length data such as fixed length packets, The present invention relates to an address control part of a data exchange device or a common buffer type data exchange device used for giving a delay or exchanging data.

[0002]

[Prior art]

Conventional example 1. In the ATM communication system, for example, continuous signals such as line signals and voice, and burst signals such as data and moving images are all divided into fixed lengths, and a header indicating destination information is added to the divided lengths. Packets are added to form a packet, and information is transferred in the same format packet. Since it is not necessary to synchronize frames and the like between the terminal and the transmission path, and the speeds of the terminal and the transmission path may be independent, it is possible to support any terminal. However, since packets arrive randomly at a high-speed packet switch, one destination may be flooded with many packets at a certain moment, and it is necessary to wait for packets to prevent information loss. Occurs.

To address this problem, for example, the document Internati
onal Conference on Communications, 1987, Session 22, Paper No. 2, Jean-Pierre Coudreuse, Michel
Servel, ■ PRELUDE: An Asynchronous Time-Division Sw
A high-speed packet switch is proposed in itched Network, Fig.5 and Fig.6. This document relates to a high-speed packet switch in an asynchronous transfer mode (ATM) communication system that efficiently multiplexes and transmits circuit-switched data and packet-switched data, and a conventional data queuing device can be found in its control circuit 16. You can Figure 30
Shows a block diagram of an example thereof. Reference numerals 11 _{1 to} 11 _{n denote} n (n ≧ 2) incoming lines to which data is input, and packets arriving here have a fixed length. Reference numerals 12 _{1 to} 12 _m denote _m (m ≧ 2) outgoing lines from which packets are output. A packet multiplexing circuit 13 multiplexes the input packets.
Reference numeral 14 is a memory in which data can be written to a specified address and the data can be read out by specifying the address regardless of the writing order.
Reference numeral 15 is a packet separation circuit for separating the read packet. Reference numeral 16 is a control circuit for controlling packet exchange.

FIG. 31 shows the control circuit 16 in detail. The control circuit 16 is a modified version of the conventional data queuing device shown in FIG. 10 of the above document. In the figure, 17 determines the address to write the packet in the memory 14 from the header of the arriving packet, and determines the destination outgoing line 12 _{1 of the} packet.
It is a header conversion circuit having a function of determining ~ 12 _m and converting to a new header. A circular selector 20 has a function of sequentially selecting information.

[0005] 18 is a conventional data queuing apparatus, the input line 1 is input write address to the memory 14 of the packet, 3 ₁ to 3 _m destination instruction input indicating a destination of the packet, 2 ₁ ~ 2 _m is an output line that is output after the address has met. Reference numerals 19 _{1 to} 19 _m denote first-in first-out memories provided corresponding to the outgoing lines 12 _{1 to} 12 _m . The conventional data queuing device 18 has a function of arranging the write addresses of the arrived packets in correspondence with the outgoing lines 12 _{1 to} 12 _m , forming a queue, and outputting the addresses in the order of arrival for each outgoing line 12 _{1 to} 12 _m. .

A plurality of incoming lines 1 of this high-speed packet switch
The packets arriving at 1 _{1 to} 11 _n are multiplexed by the packet multiplexing circuit 13 and written in the memory 14. Also,
The header including the destination information of the arrival packet is the control circuit 16
To the destination output line 12 ₁ by the header conversion circuit 17.
~ 12 _m is determined and converted to a new header. The addresses written in the memory 14 are queued by the conventional data queuing device 18 so as to correspond to the destination outgoing lines 12 _{1 to} 12 _m . The conventional data queuing device 18 uses first-in first-out memories 19 _{1 to} 19 _m .

On the other hand, according to the address read from the conventional data queuing device 18, the packet is read from the memory 14, separated by the packet separation circuit 15, and the packet is output to the predetermined outgoing lines 12 _{1 to} 12 _m. It As described above, by the operation of the data queuing device 18, the incoming line 11 ₁
The packets on ˜11 _n are output to the desired outgoing lines 12 _{1 to} 12 _m , and packet exchange is realized.

FIG. 32 is a diagram showing the structure of a conventional common buffer type ATM switch. ATM switch has an incoming line 1
If 1 ₁ to 11 ₈ cells to enter, and transfers to the control circuit 16 separates the header from the cell. The control circuit 16 queues the destination of the data from the header, and outputs the destination of the input data based on the queued data. On the other hand, the input data passes through the cross point switch and is input and stored in the common buffer memory (SBM). The data stored in the SBM is output to any of the outgoing lines 12 _{1 to} 12 ₈ based on the output instruction from the control circuit 16. FIG. 33 is a diagram showing address queuing using a conventional first-in first-out memory used in the control circuit 16.

Conventional example 2. Further, as a conventional technique, there is a technique described in, for example, Torii et al., "Consideration of Cell Transfer Control Function Deployment in ATM Switch", and IEICE Research Report Exchange System SSE90-134.

According to the techniques described in these documents,
ATM (Asynchr) for high-speed transmission and exchange
A unit called a cell, in which multimedia information is divided into blocks and a header including destination information is added, is used in the "Outer Transfer Mode" communication. The cell has a fixed length according to the international standard. On the other hand, the interface speed in the ATM communication system is based on 155.52 Mb / s (hereinafter, also abbreviated as 150 Mb / s), and some of integer speeds thereof, for example, 622.08 Mb / s (hereinafter abbreviated). 600 Mb / s) is becoming an international standard.

In an ATM switch for exchanging cell header information by directly referring to the header information by hardware, a cell multiplexing / demultiplexing circuit is used in the input section and the output section of the ATM switch to accommodate an interface different from the interface of the switch. It is often done.

In many cases, the network has a hierarchical circuit network configuration having a plurality of exchange stages using a subscriber exchange and a transit exchange. Therefore, A
The header of the TM cell is used as an identifier for identifying a line (virtual channel) and a line bundle (virtual path), and the VCI (v
irtual channel identifier) and VPI (virtual pathide)
ntifier). Further, these values are defined for each transmission path, and the VPI / VCI value or the VPI value needs to be rewritten in the switch or the cell switching device in the cross-connect node.

FIG. 34 is a block diagram of an ATM switching system. Further, FIG. 35 is a block diagram of a cell exchange apparatus in the same example, and is a configuration diagram of an ATM switch module, a cell multiplexing circuit, and a cell separation circuit. In the figure, 11 is an input line, 12 is an output line, 30 is an ATM switch, 40 is a cell multiplexing circuit, 50 is a cell separation circuit, 60 is an input port, 7
0 is an output port, and 80 is a cell switching device. Also, 9
Is a transmission line, 9a is a transmission line of 150 Mb / s, 9b
Is a 600 Mb / s transmission line. Also, 110, 11
1 is a header conversion unit, and 110a is 150M on the input side.
b / s VPI converter, 110b is 150 Mb on the output side
/ S VPI converter, 111a is input side 600 Mb /
s VPI converter, 111b is 600 Mb / s on the output side
Is a VPI conversion unit.

Next, the operation will be described. The cell switching device 80 includes an ATM switch 30, a cell multiplexing circuit 40, and a cell separating circuit 50. The generated information is divided into blocks of a certain length to form cells, and the transmission lines 9a,
It arrives at the cell switching device 80 through 9b and is first input to the input port 60. Next, the VPI conversion units 110 and 11
1 is input and VPI conversion is performed. The VPI conversion is to convert the VPI / VCI value in the header of the input cell into a new VPI / VCI value and add the destination of the cell in the cell switching apparatus. VP
By assigning a cell destination by I conversion, A
The TM switch 30 will select the destination outgoing line.

The interface speed of the transmission line 9a is 150 Mb / s which is an international standard. On the other hand, A
The interface speed of the TM switch 30 is 600 Mb /
The transmission line 9b can be directly accommodated, but the transmission line 9a cannot be directly accommodated. However, as the capacity, it is possible to accommodate four transmission lines 9a. Therefore, the cell multiplexing circuit 40 multiplexes four 150 Mb / s input ports 60 in cell units, and one 600 Mb / s input port 60 is multiplexed.
It is output to the incoming line 11 of the ATM switch 30 as an interface. The cell multiplexing circuit 40 is composed of switch modules (not shown) corresponding to the number of input ports. Cell multiplexing is performed by temporarily storing the cells in a buffer in the switch module and coordinating with other switch modules while reading the cells from the buffer at high speed so as to avoid collision of cells on the incoming line 11. Perform multiplexing.

FIG. 36 and FIG. 37 are inner views of a conventional cell switching apparatus when accommodating interfaces of different speeds. In both cases of FIG. 36 and FIG. 37, the ATM switch has a 600 Mb / s interface. The address queue 19 ₁ corresponds to the outgoing line 12 ₁ . Also, the output line 12 ₂ address queue 19 ₂ is compatible with respect to the output line 12 ₂ is divided by the cell demultiplexer 50 to output lines of the four 150 Mb / s. These four 15
The address queue 19 ₂ has four address queues # 0 to # 3 internally corresponding to the output line of 0 Mb / s.
When calling an address from the address queue 19 ₂ , the ATM switch cyclically accesses # 0 to # 3. Thus, cells output to the outgoing line 12 ₂ will be cell designated by # 3 from the address queue # 0 is output cyclically. Cell separation circuit 50
Divides these data into four outgoing lines in order to output a cell to the intended outgoing line.

On the other hand, in the case of FIG. 37, four incoming lines and four outgoing lines are multiplexed or demultiplexed by the cell multiplexing circuit 40 and the cell demultiplexing circuit 50 so as to conform to the 2.4 Gb / s interface. Therefore, 60 ATM switches
Even if only the interface of 0 Mb / s is provided, the interface of 2.4 Gb / s can be provided.

[0018]

Since the conventional data queuing device is constructed as described above, for example, when the memory 14 has a write capacity of P packets,
In order to prevent loss due to overflow of addresses in the first-in first-out memory 19, a capacity capable of holding P addresses is required for each, so that the conventional data queuing device 18 as a whole requires a capacity of P × m addresses. As a result, there is a problem that the scale of the device becomes large.

Further, the address queue must be constructed in consideration of the hierarchical use of lines in order to accommodate interfaces of different speeds. For example, as shown in FIG. 36, it is necessary to prepare a plurality of address queues by knowing in advance that the line will be separated by the cell separation circuit. Preparing a plurality of address queues corresponding to a plurality of outgoing lines separated by the cell separation circuit has a problem of increasing the size of the data queuing device and consequently the size of the device. It was

The present invention has been made to solve the above problems, and it is not necessary to prepare a plurality of memories for holding a data queue, and a memory for holding a data queue can be provided. By being shared by all output lines, the memory capacity can be reduced and the scale of the entire device can be reduced, and the efficiency of memory usage can be improved. Even with the same memory capacity, the rate of data discard caused by exceeding the memory capacity The purpose is to obtain a data queuing device capable of lowering.

It is another object of the present invention to provide a data queuing device capable of accommodating interfaces of different speeds even when a memory holding a data queue is shared by all output lines. And

[0022]

A data queuing device according to the present invention has the following elements. (A) a plurality of output lines for outputting data, (b) an input unit for inputting data that holds at least one output line of the plurality of output lines as a destination, (c) for the plurality of output lines Storage unit that is commonly provided for storing data input from the input unit, and (d) holds the output line from the data stored in the storage unit as a destination for each output line. The selected data as the data to be output to the output line, and (e) the search selection unit searches the output line for data. Search instructing means for instructing the timing to the search selecting means.

The storage section has a plurality of shift memories for sequentially shifting and storing data, and an output line correspondence memory provided corresponding to the output lines for each shift memory, and stored in the shift memory. The data destination is held by using the output line corresponding memory corresponding to the output line indicated by the data destination, and the search instructing means instructs the data search at a predetermined frequency corresponding to each output line. To do.

The search instruction means instructs the search selection means on the basis of the frequency table in which the data output frequencies are registered corresponding to the output lines, and the search timing for each output line based on the output frequency of the frequency table. It is characterized by comprising a search instruction unit for

The output line has an output line having a reference output frequency and an output line having an output frequency smaller than the reference output frequency, and the output line correspondence memory stores a plurality of destinations. One destination display bit is assigned to each output line having a destination output bit and a reference output frequency, and one destination display bit is assigned to each output line having an output frequency smaller than the reference output frequency. It is characterized by allocating bits.

The output line has an output line having a reference output frequency and an output line having an output frequency higher than the reference output frequency, and the output line corresponds to the output line correspondence memory and a plurality of destinations holding destinations. One destination display bit is assigned to an output line that has a display bit and has a reference output frequency, and has a reference output frequency for an output line that has an output frequency greater than the reference output frequency. The feature is that the destination display bits to be assigned to the output line are grouped and assigned.

The storage unit uses the destination display bit corresponding to one output line of the grouped destination display bits to store the destination of the data output to the output line having the output frequency higher than the reference output frequency. When the search instruction means instructs the search selection means to search for data on an output line having an output frequency higher than the reference output frequency, the search instruction means controls the output line having the reference output frequency. It is characterized in that the search is instructed at a frequency higher than that of searching the data.

The storage unit manages the destination of the data output to the output line having the output frequency higher than the reference output frequency by using the grouped destination display bits in order,
When the search instructing means instructs the search selecting means to search for data on an output line having an output frequency higher than a reference output frequency, it sequentially searches a plurality of grouped destination display bits. It is characterized by

[0029]

In the data queuing device according to the present invention, the storage unit having the buffer memory can be shared by all output lines. Then, by instructing the search timing of the data stored in the storage unit by the search instruction means,
It is possible to output data at a speed adapted to the outgoing line of different speed.

Further, since the search instructing means instructs the search at a predetermined frequency corresponding to the output lines, it is possible to instruct the data output speed for each output line.

Further, the search instruction means has a frequency table, and the output frequency of data can be changed by registering the output frequency for each output line in the frequency table.

The output line corresponding memory has a plurality of destination display bits, and the destination display bits are assigned to the output lines having the reference output frequency, and the output frequency smaller than the reference output frequency is assigned. Since the destination display bit is assigned to each output line having, output data having a reference output frequency and output lines having an output frequency smaller than the reference output frequency are searched for data with a frequency of search. The same search operation can be performed although it is different.

On the other hand, for output lines having a higher output frequency than the output line having the reference output frequency, the destination display bits assigned to the output lines having the reference output frequency are grouped and one of them is grouped. Assigning destination indicator bits provides an interface for output lines that have a high output frequency.

Further, when the data of the output line having a high output frequency is searched, the data can be searched correctly by operating at high speed even when only one destination display bit is used. Even when the data of the output line having a high output frequency is searched, the data is output by the same search operation as the search operation for the output line having the reference output frequency except that the high speed search is performed.

By assigning a plurality of destination display bits to the output line having a high output frequency in order,
It is possible to search for data by using the same search operation as the output line having the reference output frequency without operating at high speed.

[0036]

【Example】

Example 1. FIG. 1 is a diagram showing a system to be achieved in this embodiment. In this embodiment, the case where the outgoing line from the ATM switch has a 600 Mb / s interface will be described. Out line 1
The case where 2 ₁ is separated into four outgoing lines 150 ₁ to 150 ₄ by the cell separating circuit 50 will be described. Figure 2
FIG. 3 is a diagram showing an example of a common buffer type ATM switch. A feature of this common buffer type ATM switch is that the data queuing device 180 as described above is used in the control circuit 16. FIG. 3 is a diagram showing an embodiment of the data queuing device 180 according to the present invention. In the figure, the same reference numerals as those in the conventional example indicate the same or corresponding parts as the respective parts in the same figure.

In FIG. 3, 1 is an input line for inputting data of finite length, 2 ₁ to 2 _m are plural output lines for outputting data, and 3 _{1 to} 3 _m are corresponding to output lines 2 ₁ to 2 _m. destination instruction indicated by the bits of the destination output lines of the data to be input is provided Te input, 4 ₁ to 4 _k is shift memory, 5 ₁₁ to 5 _miles destination indicating bits corresponding to the shift memory where data is stored, For example, the destination display bit 5 ₁₂ is the shift memory 4
_1- bit information indicates whether or not the data stored in ₁ is destined for the output line 2 ₂ . In another example, the destination display bit 5 _km indicates whether or not the data stored in the shift memory 4 _k is destined for the output line 2 _m . 6 _{1 to} 6 _m are search circuits provided corresponding to the output lines 2 ₁ to 2 _m . For example, the search circuit 6 ₁ has the destination display bits 5 ₁₁ , ₅₂₁ . ． ． It is connected to 5 _k1 .
7 _{1 to} 7 _m are selectors provided corresponding to the output lines 2 ₁ to 2 _m . For example, the selector 7 ₁ corresponds to the output line 2 ₁ , selects the corresponding data from the shift memories 4 ₁ to 4 _k according to the instruction of the search circuit 6 ₁ and outputs the selected data to the output line 2 ₁ . Further, reference numeral 100 is a search control unit for instructing the search circuit of search timing.

FIG. 4 is a block diagram of the search control unit 100. The search control unit 100 has a frequency table 101 in which search timings are registered. Search instruction unit 102
Outputs the timing of the search registered in the frequency table 101 to the search circuit as a search instruction.

FIG. 5 is a diagram showing an example of the frequency table. The frequency table is provided for each outgoing line. Each output line corresponds to four output lines. For example, the output line 2 ₁ to 2 ₄ correspond to the output line 12 ₁ . Similarly, for the output line 12 _2, the output line 2 ₅ ~
2 ₈ correspond. Output lines are provided for the slowest speed interface. For example, there are 8 outgoing lines in the ATM switch, and each outgoing line is 600M.
When the cell separation circuit is provided with a b / s interface and all the output lines are divided into 150 Mb / s output lines, 8 × 4 = 32 output lines are provided. The frequency table thus predefines 32 output lines and at what speed the output line should provide the interface. In other words, the frequency table is a table that indicates at what output frequency data should be searched for each output line. For example, it indicates that data is output to the output lines 2 ₁ to 2 _{4 at} a speed of 150 Mb / s. It also indicates that data is output to the output line ₂₅ at a speed of 600 Mb / s. Other blanks indicate that data is not searched.

FIG. 6 is a diagram showing a timing chart of a search instruction output by the search instruction unit 102 based on the frequency table shown in FIG. In this example, it is considered that data is retrieved every four time slots. The search instruction 33 ₁ is sent from the search instruction unit 102 to the search circuit 6 _{1 in the} time slot 4 and the time slot 20.
Is output to. Therefore, the search circuit 6 ₁ searches for data to be output to the output line 2 ₁ in the time slot 4 and the time slot 20. Further, the search instruction unit 102 outputs the search instruction to the search circuit 6 _{2 in the} time slot 8 and the time slot 24. The search circuit 6 ₂ searches for data in the time slot 8 and the time slot 24 and outputs the data to the output line 2 ₂ . In this way, when the frequency table 101 specifies 150 Mb / s, data is searched for every 16 time slots.

On the other hand, the search instruction unit 102 outputs the search instruction 33 ₅ to the search circuit 6 ₅ in the time slots 4, 8, 12, ... Therefore, the search circuit 6 ₅ searches for data every four time slots and outputs the data to the output line 2 ₅ . The search instruction unit 102 uses the output line 2 of the frequency table.
_Since the columns corresponding to ₆ , 2 ₇ and 2 ₈ are blank, the search instruction is not output to the output lines 2 ₆ , 2 ₇ and 2 ₈ . Thus, the data output from the output lines 2 ₁ to 2 ₄ are multiplexed in the ATM switch and output to the output line 12 ₁ . FIG. 7 is a diagram showing the relationship between the output lines 2 ₁ to 2 ₄ and the output line 12 ₁ . The data output to the output lines 2 _{1 to} 2 ₄ are input to the cross point switch. A selector exists in the crosspoint switch, and the selector cyclically accesses the data to be taken out from the buffer memory through the output lines 2 ₁ to 2 ₄ .
Come out. That is, the selector has output lines 2 ₁ to 2
By switching ₄ in order, the data read from the buffer memory is output. As shown in FIG. 6, as a result, the search instruction is output every four time slots, and the data searched by these search instructions are multiplexed on the output line 12 _1. The output to ₁ is outputting data at a speed of 600 Mb / s. On the other hand, data is output to the output line 2 ₅ every four time slots, and the output lines 2 ₆ , 2 ₇ ,
Not output data for 2 _8. By outputting the data output from the output line 2 ₅ to the output line 12 ₂ as it is, the data is output at a speed of 600 Mb / s.

Next, the operation will be described. Here, FIG.
~ Fig. 9 is a time chart showing the timing of signals of each part, where the number of input lines 1 is 1 and the number of output lines 2 ₁ to 2 _m is m.
There with four shows a change of each part of the state when the number k of the shift memories 4 ₁ to 4 _k is six. Further, here, a case will be described in which the four output lines 2 ₁ to 2 ₄ correspond to _one output line 12 ₁ and are divided into _four output lines by the cell separation circuit 50. The speed of outgoing line 12 ₁ is 60
It is 0 Mb / s. The speed of the _four outgoing lines 15 ₁ to 15 4 divided by the cell separation circuit is 150 Mb / s.

In FIGS. 8 to 9, (a) shows the flow of time in the horizontal axis direction in units of time slots. (B) shows an example of data input to the input line 1, and (c) shows destination instruction inputs 3 ₄ , 3 ₃ , 3 ₂ , 3 ₁ indicating the destination of the input data in this order. (D) to (o) show an example of the state of each time slot of the shift memories 4 ₁ to 4 ₆ and the destination designating bits 5 _{11 to} 5 ₆₄ . Also, (p) to (s)
Indicates the data output to the output lines 2 ₁ to 2 ₄ .

The data input to the input line 1 is information of a finite length, such as frame structure information having fixed breaks with respect to a predetermined fixed time, fixed length address information, or fixed length packet. is there. 8 to 9, a fixed length time is defined, and for the sake of explanation, numbers are sequentially assigned from time slot 1 to define the time. In the figure, it is assumed that one piece of data arrives in the unit time slot.

Before time slot 1, data has not arrived, or sufficient time has elapsed since the data arrived and was output, and there is data in the internal shift memories 4 ₁ to 4 _6. No example is given. Further, it is assumed that the data has arrived at each of the time slots 1, 2, 3, 4, 6, 7, and 8.

Further, FIGS. 8 to 9 show the case where the reading of the output lines 2 ₁ to 2 ₄ is collectively performed for every 4 time slots, and in reality, the data is read in the time slot 4 and the time slot 8. Is being read.

At the same time that data is input from the input line 1,
Destination information is input from the destination instruction inputs 3 _{1 to} 3 ₄ . For example, if the input data is destined for the output line 2 ₄ ,
Destination instruction input 3 ₄ is a significant condition. In the figure, since the significant bit is set to "1", at this time, the input destination instruction input {3 ₄ , 3 ₃ , 3 ₂ , 3 ₁ } is {1,
0,0,0}.

In time slot 1, data a destined for output line 2 ₄ is input, and in time slot 2, data b destined for output line 2 ₁ is input. Now, since the shift memory 4 ₆ in the time slot 1 is empty, the input data a is shifted immediately. At this time, destination instruction input 3 _{1 to} 3 ₄
Are taken into the destination indication bits 5 _{64 to} 5 ₆₁ .

Similarly, in time slot 2, since the shift memory 4 ₅ is empty, the data a is stored in the shift memory 4 ₆
To the shift memory 4 ₅ , and the input data b is shifted to the vacant shift memory 4 ₆ . Data a
Shifts from the shift memory 4 ₆ to the shift memory 4 ₅ , and at the same time, the original destination display bits 5 _{64 to} 5 ₆₁ shift to the destination display bits 5 _{54 to} 5 ₅₁ corresponding to the next shift memory 4 ₅ .

Next, the reading of data from the output lines 2 ₁ to 2 ₄ will be described. FIG. 8 shows an example of collectively outputting data in the time slot 4. In order to output the data in the time slot 4, at the beginning of the time slot 4, the search circuit 6 ₁ searches for the data to be output. If there is a significant bit in each of the corresponding destination indication bits 5 _{11 to} 5 ₆₁ , it is notified to the corresponding selector 7 ₁ . The selector 7 ₁ selects _one from the notified shift memories 4 ₁ and outputs the data to the output line 2 ₁ . Since the search instruction from the search instruction unit 102 does not come to the search circuits 6 _{2 to} 6 ₄ in the time slot 4 as shown in FIG. 6, the output lines 2 ₁ to 2 2
Do not search the data output to ₄ .

The search circuit 6 ₁ searches for the data to be output to the output line 2 ₁ , and the destination designating bits 5 ₁₁ , 5 ₂₁ ,
5 ₃₁ , 5 ₄₁ , 5 ₅₁ , 5 ₆₁ are read in this order, and the significant bit "1" is searched from among these. If there is a significant bit in this, the selector 7 ₁ is notified of this. The selector 7 ₁ is a selector for selecting one from the six in the figure, and selects one from the six shift memories 4 ₁ to 4 ₆ according to the instruction of the search circuit 6 ₁ and outputs the corresponding data to the output line. Output to 2 ₁ .

Since the operation for outputting data to the output line 2 ₁ is independent of the output operation of the other output lines 2 ₂ to 2 ₄ , it is possible to operate simultaneously and separately.

The destination display bits 5 _{11 to} 5 ₆₁ searched by the search circuit 6 ₁ have their significant bits erased when selected as a result of the search. Further, the shift memory 4 ₁ to 4 ₆ data is read, the data is erased. If there is data in the subsequent stage of the shift memory 4 ₁ to 4 _6, data from behind is shifted to the shift memory where the data is read.

Next, a specific operation will be described with reference to FIGS. In time slot 1 to time slot 4 in FIG. 8, data a, b, c, d are respectively input, and the input data a, b, c, d are stored in the shift memory in the order of input, To be done. In the time slot 4, data is read to the output line 2 ₁ as described above.

Data output to the output line 2 ₁ in the time slot 4 will be specifically described below with reference to the example of FIG. In time slot 4, the search circuit 6 ₁
The address indication bits 5 ₁₁ , 5 ₂₁ , 5 ₃₁ , 5 ₄₁ , 5 ₅₁ , 5 ₆₁ are read in this order. This value is 0, 0, 0,
It is 0, 1, 1. When the significant bit "1" is searched from this in this order, the destination indication bit 5 ₅₁ corresponds to it, and this is notified to the selector 7 ₁ . The selector 7 ₁ selects the six shift memories 4 ₁ to 4 ₆ to 4 ₅ according to the instruction of the search circuit 6 ₁ and outputs the data b to the output line 2 ₁ .

When the data b is output to the output line 2 ₁ , the shift memory 4 ₅ in which the data b existed in the time slot 4 becomes empty, and the data c in the subsequent stage is shifted in the time slot 5 shown in FIG. It shifts to memory 4 ₅ . Also, accompanying the data c, destination indication bits 5 ₆₄ , 5 ₆₃ ,
The information of 5 ₆₂ , 5 ₆₁ also includes the destination indication bits 5 ₅₄ , 5 ₅₃ ,
It shifts to 5 ₅₂ , 5 ₅₁ .

In the time slot 5, since no data is input from the input line 1, the data in the time slot 5 are sequentially shifted while remaining empty. Furthermore, in time slot 6 to time slot 8, data e,
f and g are sequentially input. The input data is stored and shifted in the shift memory. In the time slot 8, data is read to the output line 2 ₂ . The output circuit 2 ₂ outputs the data e by the search circuit 6 _2.
To search. These retrieved data e are output line 2 ₂
Is output to With respect to the output lines 2 ₁ , 2 ₃ and 2 ₄ , since the search instructions 33 ₁ , 33 ₃ and 33 ₄ do not occur, the search circuits 6 ₂ , 6 ₃ and 6 ₄ do not search the data. Therefore, no data is output to the output lines 2 ₁ , 2 ₃ and 2 ₄ .

In the above example, all the input data could be written to the shift memory 4 _6. However, if there is data in all the shift memories 4 ₁ to 4 ₆ , the data cannot be written, so This data is discarded. The number k of the shift memories 4 ₁ to 4 _k in order to reduce the probability that the data is discarded better is large.

Next, the flow of the above-mentioned operation will be described with reference to FIG. In S1, the data and the destination instruction are input from the input line 1 and the destination instruction inputs 3 _{1 to} 3 _m . Next, in S2, it is checked whether or not data already exists in the last-stage shift memory that first stores the input data. If the data already exists in the last shift memory, the data and the destination instruction input in S1 are discarded in S3. If it is determined in S2 that the shift memory is empty, the data and the destination instruction input in S1 are stored in the last shift memory in S5. Next, in S6, it is checked whether it is the fourth input.
If it is not the fourth input, the operations of S1 to S5 are repeated again. While the operations of S1 to S6 are repeated, the shift memory shifts the input data forward.
By this front-justification work, the shift memory at the final stage for inputting data is in an empty state unless the entire shift memory is full. If it is determined in S6 that the input is the fourth time, the search circuits 6 _{1 to} 6 _{4 in} S7.
Searches the destination instruction for each outgoing line based on the search instruction, and searches for output for each outgoing line. In S8, it is determined whether or not the data corresponding to the search result output line is found. If not found, the process returns to the input step of S1. If output data is found on the outgoing line in S8, the selector selects the corresponding data from the shift memory in S9. In S10, the data selected by the selector is output to the corresponding output line. In S11, the data output in S10 is no longer needed, so the corresponding destination instruction is cleared and the data is deleted from the shift memory. After deleting this data, S again
Return to 1 data and destination instruction input. Further, by deleting this data, the shift memory in the subsequent stage is prompted to perform the data forward packing operation, and the address instruction cleared is overwritten by the contents in the shift memory in the subsequent stage.

FIG. 11 is a diagram showing the data thus output to the outgoing line 12 ₁ . Data b, data e, data g, and data a are output to the output line 12 ₁ in this order.
This data is separated by the cell separation circuit 50 and
The data is divided in the order in which the data arrives at the four 0 Mb / s outgoing lines.

Next, referring to FIG. 12, FIG. 13 and FIG.
Outgoing lines 00Mb / s are present present 4, a case will be described in which the output line _{21 to 24} corresponds to that the four outgoing lines. In this example, the number of input lines 1 is the one, described the case where the shift memory ₄₁ to ₆ are present. The difference between FIG. 12 and FIG. 7 is the operation in time slot 4. When four output lines correspond to four output lines operating at a speed of 600 Mb / s, the search instructions 33 _{1 to} 33 ₄ are output to the search circuits 6 _{1 to} 6 _{4 in the} time slot 4. To be done. Search circuit 6 ₁ ~
6 ₄ searches for data to be output, and the selectors 7 ₁ ...
7 ₄ outputs the data to the output lines 2 ₁ to 2 ₄ , respectively.
In the case shown in FIG. 12, the data b is output to the output line 2 ₁ and the data a is output to the output line 2 ₄ . Similarly,
In the case shown in FIG. 13, the data c is outputted to the output line 2 _1, the data e is outputted to the output line 2 _2.
Further, in the case shown in FIG. 14, the data d is output to the output line 2 _{1 and the} data g is output to the output line 2 ₃ . As described above, in the case of having the interface of 600 Mb / s, the search circuit independently searches the plurality of output lines for data. The timing of this search is based on the definition of the frequency table 101. On the other hand, in the case of 150 Mb / s described above, data is output every 16 time slots. The timing of this search is based on the definition of the frequency table 101.

As described above, according to this embodiment, the finite length data inputted to the input line 1 is written into the shift memory 4 which can be sequentially shifted between the adjacent lines irrespective of the destination, and the data is shifted. A destination display bit 5 indicating the destination of the data is provided corresponding to the memory, and a search circuit 6 for searching a significant bit in the destination display bit corresponding to the destination output line finds the output data corresponding to the output line in the order of arrival and arrival. The data is extracted by the selector 7, and after the extraction, the latter stage of the shift memory is shifted so that the selector outputs the data to the desired output line 2.

Further, this embodiment shows a case in which an ATM switch having a 600M interface corresponds to a 150M interface. The destination display bit and the output line are provided in the number corresponding to the 150M interface, the destination display bit is associated with the output line having the 150M interface one bit at a time, and the output line having the 600M interface is provided with By making only 1 bit of 4 bits of the destination indication bit correspond, it is possible to accommodate interfaces of different speeds. When the 600M interface is supported, data is retrieved and output once every four cell slots for each outgoing line. On the other hand, in the case of the 150M interface, 4 bits of the destination indication bit are used, and the 4 bits are sequentially circulated and searched to output data once every 16 cell slots from one output line. As a result, data output is achieved once every four cell slots.

According to this embodiment, the data inputted from the input line is written in the shift memory, the destination thereof is stored in the destination display bit, the destination display bit is searched for the output line, and the previously inputted data is stored. Since the data is read first, it is possible to guide the input data to a predetermined destination output line in the order of arrival, and since the shift memory is shared by all output lines, the number of data writes exceeds the capacity of the buffer memory. Therefore, there is an effect that a data queuing device capable of reducing the discard rate of the data generated thereby can be obtained.

Further, according to this embodiment, even when the shift memory is shared by all the output lines, the destination display bit is provided corresponding to the slowest interface, so that the hierarchized interfaces of different speeds are provided. Can be accommodated.

Example 2. In the first embodiment described above,
The case of supporting the 150 Mb / s interface has been described, but in this embodiment, 2.4 Gb / s
The case of supporting the s interface will be described. FIG. 15 shows a case where four output lines of 600 Mb / s are put together and the cell multiplexing circuit 40 supports the 2.4 Gb / s interface. FIG. 16 is a diagram showing the relationship between the output line 2 ₁ and the output lines 12 ₁ , 12 ₂ , 12 ₃ , 12 ₄ . The data output from the output line 2 ₁ is input to the cross point switch. A selector exists in the crosspoint switch, and the selector cyclically outputs the data fetched from the buffer memory to the output line 12
It outputs to ₁ , 12 ₂ , 12 ₃ , and 12 ₄ . That is, the selector sequentially outputs the data designated by the output line 2 ₁ to each output line by sequentially switching the points P10, P11, P12, and P13. FIG. 17
FIG. 6 is a diagram showing an example of a frequency table in this embodiment. Also in the frequency table in this embodiment, the number of output lines is prepared according to the interface of 150 Mb / s, which is the slowest speed, as described above. In this embodiment, a 150 Mb / s interface is not used, but a 600 Mb / s interface may be divided by a cell separation circuit to support a 150 Mb / s interface. Therefore, one output line and one destination display bit are used. Provide four each for the output line of
The frequency table allows the speed to be specified for each output line. In this example, the outgoing line 12
Only output line 2 ₁ is assigned to ₁ to 12 ₄ ,
Output lines 2 ₂ to 2 ₁₆ are not used. Further, as to the output line 12 _{5 and} thereafter, only one output line is assigned from the four output lines as in the above-described embodiment.

FIG. 18 is a diagram showing a timing chart of a search instruction in this embodiment. The search instruction unit 102 issues a search instruction as shown in FIG. 18 by referring to the frequency table 101. The search instruction 33 ₁ instructs a search for each time slot. Therefore, the search circuit 6 ₁
Retrieves the data to be output to the output line 2 ₁ for each time slot. With respect to the output lines 2 ₂ to 2 ₁₆ , no data is output because the search instructions 33 ₂ to 33 ₁₆ are not output. The search instruction unit 102 instructs the search of the data so as to correspond to the frequency of similarly 600 Mb / s as in the embodiment described above using a search instruction 33 _17.

As shown in FIG. 18, the retrieval instruction 33 ₁ instructs the output line 2 ₁ to retrieve data for each time slot. Therefore, data is output to the output line 2 ₁ at a frequency four times that of the other output lines. The data output to the output line 2 ₁ is used to retrieve the data from the buffer memory via the selector shown in FIG.

FIG. 19 is a diagram showing a specific example of this embodiment. Data a, data b, data c are stored in the shift memory.
Is remembered. The destination indication bit holds the destination corresponding to these data. According to the time chart shown in FIG. 18, the data a in the first to fourth time slots, data c, the data d, 4 pieces of data of the data f is output to the output line 2 _1. Further, the data b is output to the output line 2 ₁₇ in the fourth time slot in which the data f is output. At the same time, the data e is output to the output line 2 ₂₁ .

FIG. 20 is a diagram showing the data thus output. The data output to output line 2 ₁ is A
4 outgoing lines 12 ₁ , 12 ₂ , 12 by TM switch
_It is divided into ₃ and 12 ₄ and output. For example, the data a output in the time slot 1 is output to the output line 12 ₁ . The data c output in time slot 2 is output line 12
Output to ₂ . Further, the data d output in the time slot 3 is output to the output line 12 ₃ . In this way, the data output in each time slot is cyclically divided into four output lines 12 ₁ , 12 ₂ , 12 ₃ , 12 by the selector.
It is output to ₄ in order. The cell multiplexing circuit 40 has these four
1. Input the data from the output line of the book and multiplex in order.
Data is transferred at a speed of 4 Gb / s.

In the above-mentioned example, as shown in FIG. 18, it is necessary to retrieve the data to be output to the output line 2 _{1 at} a speed four times faster than usual. Therefore, a configuration in which the search may be performed at the same speed as usual will be described below. Figure 21
FIG. 6 is a diagram showing a destination distribution unit 200 that distributes destination instruction input. When the data output to the 2.4 Gb / s interface is input, the destination distribution unit 200 distributes and stores the data into a plurality of destination display bits. FIG. 19
In the case shown in (1), since the destination distribution unit does not exist, only the destination display bit corresponding to the output line 2 ₁ is used, and the destination instruction is input to the same column of the destination display bits.

On the other hand, as shown in FIG. 21, the destination distribution unit 20
When 0 is present, as shown in FIG. 22, when the destination distribution unit outputs data to the 2.4 Gb / s interface, the destination indication bit is cyclically circulated and used. When the input data is output to the output line of the 2.4 Gb / s interface, the destination distribution unit switches the destination display bits in order and stores the destination. For example, in the state of FIG. 22, the data m is recorded for the 2.4 Gb / s interface, and the switch SW of the destination distribution unit 200 connects P1. In this state, when the next data r output to the output line of the 2.4 Gb / s interface is input, the switch SW switches to P2. Therefore, the destination indication bit of the data r is shown in FIG.
It is recorded at the position indicated by a circle in 8.

FIG. 23 shows the frequency table 1 in this example.
It is a figure which shows the example of 01. The destination distribution unit 200 outputs the output line 2
It shows that four output lines ₁ , 2, ₅ , 2 ₉ , and 2 ₁₃ are used. Therefore, the search instruction unit 102 outputs the output line 2
_The search circuit is operated to cyclically output data to ₁ , 2 ₅ , 2 ₉ , and 2 ₁₃ in sequence.

FIG. 24 is a timing chart of a search instruction output by the search instruction section. The destination distribution unit stores the destinations in four distributed locations, so 2.4 Gb /
In both cases of s and 600 Mb / s,
A search instruction is output every fourth slot. In this way, the output similar to that of FIG. 20 can be obtained.
In this example, the search circuit does not operate at high speed, and it becomes possible to retrieve the data of the 2.4 Gb / s interface using the same search speed as the conventional search speed for 600 Mb / s.

Example 3. In the embodiment described above, the destination indicator bit was prepared to correspond to the 150 Mb / s interface providing the slowest interface. For example, there are eight 600 Mb / s outgoing lines,
If all eight outgoing lines each have a 150 Mb / s interface, the number of output lines and destination indication bits is eight.
× 4 = 32 was required. These 32 output lines and 32
It is possible to flexibly cope with a change in the system configuration by preparing the bit destination display bit, preparing the frequency table as described above, and rewriting the frequency table. However, since there are unused output lines and unused destination indication bits, such waste can be eliminated. Figure 2
5 shows an example of a frequency table when the system shown in FIGS. 1 and 15 is used fixedly. If the system shown in FIG. 1 is a fixed system, a total of 11 destination indication bits are required. Therefore, it is about 1/3 of the 32 bits described above.
The number of outgoing lines and the number of destination display bits will be enough. When the number of output lines is 11 and the destination display bit is 11 bits, by describing the frequency table as shown in FIG. 25A, the same effect as that of the first embodiment can be obtained. be able to. Further, if the system shown in FIG. 15 is a fixed system, a total of 5 destination indication bits are required. Therefore, the number of outgoing lines and the number of destination display bits are about 1/6 of 32 bits described above. When the number of output lines is 5 and the destination display bit is 5 bits, by describing the frequency table as shown in FIG. 25B, the same effect as that of the second embodiment can be obtained. be able to.

Example 4. Further, in the first and second embodiments, the case where the selector exists corresponding to each output line is shown. However, as shown in FIG. 26, one selector exists for two output lines. It does not matter even if it is. In the case as shown in FIG. 26, the selector operates twice as fast as in the first and second embodiments,
The same effects can be obtained with the above-described embodiment.

Example 5. In the fourth embodiment described above, the case where the number of search circuits and selectors can be reduced by operating at high speed has been described. However, the case where the number is reduced even when the search circuits and selectors do not operate at high speed will be described below. Explained. FIG. 27 is a diagram for explaining the operation of the configuration shown in FIG. In the first and second embodiments described above, output is performed every four time slots, but in this example, output is performed every time slot. As shown in FIG. 27, the search circuit 6 ₁ outputs the output line 2 _{1 for} each time slot.
And 2 ₂ alternately detect whether or not there is data to be output. Similarly, selector 7 ₁
If data is present on the output lines 2 ₁ and 2 ₂ , these are output. Thus, the search circuit and the selector do not have to operate at high speed by performing the search and output for each time slot. In the case shown in FIG. 27, the data is output to each output line for each time slot even when operating at the same speed as in the above-described first and second embodiments, and more efficient output is performed.

Example 6. FIG. 28 shows a case where the number of search circuits is one and the number of selectors is one. In this case, the search circuit 6 operates 4 times faster than in the first and second embodiments, and the selector 7 operates 4 times faster than the first and second embodiments. The same effect as that of the embodiment can be obtained.

Example 7. FIG. 29 is a diagram for explaining the operation when the search circuit and the selector are operated at the same speed as in the first and second embodiments in the configuration of FIG. Figure 2
In the case shown in FIG. 9, the search circuit and the selector search and output the data of each output line for each time slot. In this way, by searching and outputting data to each output line for each time slot, it is possible to achieve the same effects as those of the above-described first and second embodiments. In this case, only one search circuit 6 and selector 7 are required, and high speed is not required, so that the circuit configuration becomes simple.

Example 8. In the above embodiment, 150
The case of accommodating the interfaces of Mb / s, 600 Mb / s and 2.4 Gb / s has been described, but the case of accommodating interfaces of other different speeds can be accommodated by the same method as the above-mentioned embodiment. Is.

[0081]

As described above, according to the present invention, since the memory holding the data queue can be shared by all the output lines, it is possible to obtain the data queuing device with a reduced memory capacity. Also, by the search instruction means,
By instructing the timing when the search means operates,
When this data queuing device is used in a cell switching device, it can accommodate interfaces of different speeds.

Further, even when data is stored in the common storage unit, by searching the output line corresponding memory, it becomes possible to search and output the output line corresponding data at a predetermined frequency.

Further, since it has a frequency table in which the output frequencies are registered, by changing the contents of the frequency table, it is possible to flexibly deal with the case where the system configuration is changed.

Further, the output line corresponding memory has a plurality of destination display bits, and by assigning the destination display bits to the interfaces having different speeds, the data can be correctly output to the interfaces having different speeds. it can.

Particularly, for a high speed interface,
By grouping and assigning the destination indication bits, it is possible to deal with high-speed interfaces without inconsistency.

Further, in the case of being compatible with a high speed interface, the search selecting means can operate at high speed to correctly search the data.

Further, even with a high-speed interface, it is possible to deal with a high-speed interface without operating at a high speed by sequentially allocating a plurality of destination display bits.

[Brief description of drawings]

FIG. 1 is a diagram showing a system having interfaces of different speeds according to the present invention.

FIG. 2 is a block diagram of an ATM switch of the present invention.

FIG. 3 is a configuration diagram of a data queuing device of the present invention.

FIG. 4 is a configuration diagram of a search control unit of the present invention.

FIG. 5 is a diagram showing a frequency table of the present invention.

FIG. 6 is a timing chart of a search instruction according to the present invention.

FIG. 7 is a diagram showing a relationship between an output line and an output line according to the present invention.

FIG. 8 is a time chart showing the timing of signals in each part of the data queuing device of the present invention.

FIG. 9 is a time chart showing the timing of signals in each part of the data queuing device of the present invention.

FIG. 10 is an operation flowchart diagram according to an embodiment of the present invention.

FIG. 11 is a diagram showing an output result for the different speed interface of the present invention.

FIG. 12 is a time chart showing the timing of signals in each part of the data queuing device of the present invention.

FIG. 13 is a time chart showing the timing of signals in each part of the data queuing device of the present invention.

FIG. 14 is a time chart showing the timing of signals in each part of the data queuing device of the present invention.

FIG. 15 is a diagram showing a system having interfaces of different speeds according to the present invention.

FIG. 16 is a diagram showing a relationship between an output line and an output line of the present invention.

FIG. 17 is a diagram showing a frequency table of the present invention.

FIG. 18 is a timing chart of a search instruction according to the present invention.

FIG. 19 is a diagram showing a destination indication bit of the present invention.

FIG. 20 is a diagram showing an output result for the different speed interface of the present invention.

FIG. 21 is a diagram showing a destination distribution unit of the present invention.

FIG. 22 is a diagram showing a destination indication bit of the present invention.

FIG. 23 is a diagram showing a frequency table of the present invention.

FIG. 24 is a timing chart of a search instruction according to the present invention.

FIG. 25 is a diagram showing another example of the frequency table of the present invention.

FIG. 26 is a block diagram when the number of selectors according to another embodiment of the present invention is reduced.

FIG. 27 is a diagram for explaining an operation when the number of selectors according to another embodiment of the present invention is reduced.

FIG. 28 is a block diagram in the case where a search circuit and a selection circuit according to another embodiment of the present invention are integrated.

FIG. 29 is a diagram for explaining an operation when a search circuit and a selector according to another embodiment of the present invention are integrated.

FIG. 30 is a block diagram showing a high speed packet switch including a conventional data queuing device.

FIG. 31 is a block diagram showing a conventional data queuing device.

FIG. 32 is a diagram showing a configuration of a conventional common buffer type ATM switch.

FIG. 33 is a diagram showing address queuing using a conventional first-in first-out memory.

FIG. 34 is a diagram showing a cell switching system using a conventional cell switching device.

FIG. 35 is a diagram showing a conventional cell exchange device.

FIG. 36 is a conceptual diagram of accommodating a conventional different speed interface.

FIG. 37 is a conceptual diagram of accommodating a conventional different speed interface.

[Explanation of symbols]

1 input line, 2 _{1 to} 2 _m output line, 3 _{1 to} 3 _m destination instruction input, 4 ₁ to 4 _k shift memory, 5 _{11 to} 5 _km destination display bit, 6 _{1 to} 6 _m search circuit, 7 _{1 to} 7 _m selector, 11 _{1 to} 11 _n incoming line, 12 _{1 to} 12 _m outgoing line, 1
3 packet multiplex circuit, 14 memory, 15 packet separation circuit, 16 control circuit, 17 header conversion circuit, 1
8 conventional data queuing device, 19 _{1 to} 19 _m first-in first-out memory, 40 cell multiplexing circuit, 50 cell separating circuit, 100 search control unit, 101 frequency table, 1
02 search instruction section, 33 _{1 to} 33 _m search instruction.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhito Sasaki 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corp. Communication Systems Research Institute (72) Hirotoshi Yamada 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corporation (72) Inventor Kazuno Oshima 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Co., Ltd.

Claims (7)

[Claims] 1. A data queuing device having the following elements: (a) a plurality of output lines for outputting data; (b) inputting data held at least one output line of the plurality of output lines as a destination. An input unit for: (c) a storage unit that is provided in common for the plurality of output lines and stores data input from the input unit; (d) stores for each of the output lines in the storage unit (E) the above-mentioned search, in which the data holding the output line as a destination is searched from the retrieved data, and the retrieved data is selected as the data to be output to the output line. Retrieval instructing means for instructing the retrieval and selection means when the selection means retrieves data for each of the output lines. 2. The storage unit has a plurality of shift memories for sequentially shifting and storing data, and an output line corresponding memory provided corresponding to the output lines for each shift memory,
While holding the data destination using the output line corresponding memory corresponding to the output line indicated by the data destination stored in the shift memory, the search instruction means searches the data at a predetermined frequency corresponding to each output line. The data queuing device according to claim 1, characterized by: 3. The search instruction means is a frequency table in which data output frequencies are registered corresponding to the output lines, and a search timing for each output line to the search selection means based on the output frequency of the frequency table. 3. The data queuing device according to claim 2, further comprising a search instructing unit for instructing. 4. The output line has an output line having a reference output frequency and an output line having an output frequency smaller than the reference output frequency, and the output line correspondence memory holds a destination. One destination display bit is assigned to each output line having a plurality of destination display bits and having a standard output frequency, and one destination display bit is assigned to each output line having an output frequency smaller than the standard output frequency. 4. A data queuing device as claimed in claim 3, characterized in that it assigns destination indication bits. 5. An output line having an output frequency serving as a reference and an output line having an output frequency greater than the reference output frequency, wherein the output line is a plurality of memory units each of which holds a destination. Output destination bits are assigned to the output line having the reference output frequency, and one output destination bit is assigned to the output line having the reference output frequency. 4. The data queuing device according to claim 3, wherein the destination indicating bits to be assigned to the output line having the are grouped and assigned. 6. The storage unit stores data output to an output line having an output frequency greater than a reference output frequency by using a destination display bit corresponding to one output line of the grouped destination display bits. When the destination is managed and the search instructing means instructs the search selecting means to search for data in an output line having an output frequency higher than the reference output frequency, the output line having the reference output frequency 6. The data queuing device according to claim 5, wherein the data queuing device is instructed to perform a search at a frequency higher than that at which the data is searched. 7. The storage unit manages the destination of data output to an output line having an output frequency higher than a reference output frequency by using the grouped destination display bits in order, and the search instruction means When instructing the search / selection means to search for data on an output line having an output frequency higher than a reference output frequency, a plurality of grouped destination display bits are sequentially searched. The data queuing device according to claim 5.