JPH0877704A - Address controller - Google Patents

Abstract

PURPOSE: To interpolate address data to address data having higher reliability in accordance with the results of a parity check of the address data by storing the data of an address data file decided to be effective by a means for determining addresses by majority as a representative address. CONSTITUTION: A register 1 for commonly using the addresses writes the header address HD1 of tracks TA0 to TA2 by a write enable signal en2 into the address data file 7. The register 1 selects the HD1 address from the file 7 with a selection circuit 5 and reads out the addresses of the tracks TA0 to TA2 in time sharing. The processing means 2 for deciding the addresses by majority decides the data to be effective and writes the data as the representative into the address data file 7 when the majority or oven of the address of the address data in the register 1 is the same. Thereafter, the addresses of the file 7 of the tracks of the ineffective parity results are rewritten with the address value obtd. by adding one (+1) to the representative address data of the previous block and are kept read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides an address control device for reproducing a highly reliable address from a tape format recorded in a plurality of tracks in the longitudinal direction of a magnetic tape.

[0002]

2. Description of the Related Art A digital reproducing apparatus for reproducing audio PCM data recorded on a tape has a PCM in a predetermined RAM address area based on address data in the reproduced data.
Data is stored once, error correction is performed, and then PCM data is read to perform voice reproduction. The address data is only protected by simple parity in terms of format, and even if the address data is lost due to a random error during tape reproduction, it is necessary to interpolate to the correct address to rescue the PCM data.

Therefore, the reproduction address is required to have high reliability. The conventional digital reproduction control device will be described below.

Before describing the conventional example, FIGS. 5 and 6 will be described. FIG. 6 is a diagram showing a data format of one tape block in one track.

A header of 3 words of a sync signal S indicating the beginning of a block and address data HD1 and HD2 (HD1 data and HD2 data are the same data) indicating a frame address and a block address of the block with 1 word as 10 bits. A total of data and PCM data of D0 to D47 {51 words × 10 bits} is configured as one tape block.

Word data representing one word as 10 bits is converted to 8-bit data after header data by 10-8 conversion after synchronization with a synchronization signal.

In the signal processing, PCM data is reproduced based on the converted address data. FIG. 5 shows a recording format on the magnetic tape when the number of tracks is limited to 3 for simplification of description.

When reproduction is performed in the direction of the arrow, one tape track comprises one block (51 words) × 32 blocks in one tape frame, and the block address value of the header address is from the first block address 0 to the last block. The address 31 and the leading block address 0 of the next tape frame with an inter frame gap (hereinafter referred to as IFG) interposed therebetween are set to 0.

The IFG has a variable length for adapting the tape recording process when there is jitter in the audio input sampling frequency due to digital input or the like.

A conventional address control device will be described below. FIG. 7 is a block diagram of an address control device in a conventional example.

Reference numeral 13 is an address register for storing the address data HD1 described in the data format of one tape block in FIG. 6, and 14 is a parity check with the output of the address register 13 and the address data HD2 from the reproduction address data a as inputs. Parity result generating means,
Reference numeral 15 is an increment register for adding the block address of the lower 5 bits of the address register 13 by the increment enable signal k when the parity result of the parity result generating means 14 is invalid, and 16 is the output of the increment register and the address register. It is a selection circuit for selecting an address by a selection signal from 14.

The operation of the conventional example configured as described above will be described below. The address register 13 stores the address data HD1 from the reproduction data a, and the parity result generating means 14 performs a parity check by inputting the address data HD1 and the address data HD2 from the reproduction data a to check whether the parity result is valid or invalid. judge.

When the parity result is valid, the output of 13 is stored in the increment register, and the block address selection signal 1 selects the output of the address register 13 and R
Output to AM block address e.

When the parity result is invalid, the block address of the previous block stored in the increment register is incremented by the increment enable signal k, the increment register output is selected by the block address selection signal l, and the RAM block address e is selected. Output.

The above is the address generation unit which is a component of one track, and in this case, there are as many address generation units as the number of tracks.

[0016]

However, in the above conventional configuration, in order to improve the reliability of the address data,
Even if the parity result is invalid, the parity result stored in the increment register before that increments the valid address data, so the reliability of the block address can be improved, but since it is a track-independent process, the number of tracks is the same. It was necessary to have an address generator, and the hardware scale was increased.

The present invention solves the above-mentioned conventional problems, in which the reproduction address of the current track is stored in the address data file, and at the time of the parity check, the representative address of the previous block remains the same even if the parity result is invalid. When it is valid, the address common register selects and temporarily stores the added representative address of the previous block, and then stores it again in the address data file.

After that, the purpose is to use the address read from the address data file into the address sharing register every time as the RAM address.

Even if the parity check result is invalid at the head address of the tape frame, if the representative address of the last address of the preceding tape frame is determined to be valid, the addition output of the representative address data is initialized to the head address. The purpose is to

Further, after performing a parity check using the parity check circuit common to the tracks, the parity result is stored in the address data file at the time of the parity check, and thereafter, the parity result read every time from the address data file is processed by majority. It is intended to be used as a means for evaluating the evaluation conditions of the means and a selection control means for inputting the address common register.

[0021]

In order to achieve this object, an address control device of the present invention has an address data file for storing a reproduction address of a current block of serial type digital data in track units, and an address data file for each time. Address sharing register for reading and temporarily storing, parity generating means for outputting the parity result of the current block, and when the same address in the address data file is more than half, it is determined that the address data for the current block of all tracks is valid. Address majority decision processing means, representative address generation means for storing the data in the address data file determined to be valid by the address majority decision processing means as a representative address, an adder circuit for adding the representative address data to (+1), and an addition Circuit output and address data file When the parity result of the current track is valid, the address data file output is selected and stored in the address shared register every time, and the parity result is invalid at the time of the parity check and the previous block is selected. If the representative address of is valid,
A control means is provided for selecting the address data of the adder circuit, temporarily storing it in the address common register, and storing it again in the address data file.

Further, the address control device of the present invention includes an adder circuit for initializing the representative address data to the start address when it is determined that the representative address data is valid at the final address of the tape frame.

In the address control device of the present invention, the parity check circuit common to the tracks determines the parity result of each track at the time of the parity check and stores it in the address data file, and thereafter the parity result from the address data file is parity-checked. The common register is provided with a parity generating means for reading each time.

[0024]

According to the present invention, even if the parity result of the address data of the current track stored in the address data file is invalid, if the representative address of the previous block is valid, the addition output of the representative address is temporarily added to the temporary address. After storing in the shared register, it is written again in the address data file, and every time after that, it is read out from the address data file to the address shared register, so the address read and address protection in track units are controlled by the track shared address shared register. It will be possible.

Even if the parity check result is invalid at the head address of the tape frame, if the representative address value of the last address of the previous tape frame is valid, the addition output of the representative address is initialized to the head address and the tape frame It is possible to interpolate address data at the joints.

Further, the parity generating means uses the parity check circuit common to the tracks to store the parity result in the address data file in track units at the time of the parity check, and then read it from the address data file to the parity common register every time. Therefore, the parity check circuit can be shared.

[0027]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an address control device in the first embodiment of the present invention, and FIG. 2 shows a timing diagram in the first embodiment.

In FIG. 1, 1 is an address common register, and 7 is address data in track units (TA0, TA
1, TA2) is an address data file to be written to and read from, and 2 is a majority processing means for determining that the address data file 7 is valid when the same data is majority.
3 is a representative address generating means for storing the address of the track determined to be valid by the majority processing means 2 by the representative address latch enable c, 4 is an adder circuit for adding the representative address d to (+1), and 5 is an address data file 7. A selection circuit for selecting the output and the output of the adder circuit 4 by the selection signal h,
Reference numeral 8 is a selection circuit for selecting the output of the address sharing register 1 and the reproduction address data by the selection signal b, and 9 is a parity result generating means for outputting the parity result f with the reproduction address data a and the output of the address sharing register 1 as inputs. .

The operation of the address controller of the first embodiment of the present invention constructed as above will be described below with reference to the block diagram 1 and the timing diagram 2.

As described with reference to FIGS. 5 and 6, for example TA0
After synchronizing the reproduction data of the track with the synchronization signal, the header address 1 (HD1) is converted into 10-8, and the write enable signal en2 is written from the reproduction address a to the TA0 area of the address data file 7. At this time, the selection circuit 8 selects the reproduction address data a side by the temporary address selection signal b.

Similarly, the header addresses 1 (HD1) of the TA1 and TA2 tracks are sequentially stored in the address data file 7 from the reproduction address a.

The address sharing register 1 selects the HD1 address once written in the address data file 7 by the selection circuit 5 and sequentially reads the addresses of the TA0, TA1 and TA2 tracks in a time division manner, and outputs the lower 5 bits of the output e. PCM data after the header address (HD1, HD2) is stored in a predetermined RAM address area as a block address.

Next, the parity result generating means 9 inputs the header address 2 (HD2) from the reproduction address a and the header address 1 (HD1) of TA0 read from the address data file 7 to the address sharing register 1 to input the parity. The parity result f is output independently of the track at the timing of the check enable signal g.

The majority decision processing means 2 stores the address data stored in the address common register 1 in a track-independent manner, and determines that the same data is more than a majority by using the track in which the parity result f is valid as the evaluation reference of the majority decision processing. In this case, the representative address latch enable signal c is generated.
In response to the representative address latch enable signal c, the representative address generating means 3 stores the address value of the track for which the parity result f is valid and outputs the representative address d.

If the parity result f is valid at the timing of the selection control signal h, it is continuously read from the address data file 7 to the address common register 1 each time.

If the parity result f is invalid at the timing of the selection control signal h and the representative address of the previous block is valid, the output of the adder circuit 4 is selected at the timing of the reproduction address D0 to select the address of the selection control signal h. It is taken into the shared register 1, the selection circuit 8 is switched to the output of the address shared register 1, and is written in the address data file by the write enable signal en2.

After that, the address of the address data file 7 of the track whose parity result is invalid is rewritten to the address value obtained by adding the representative address data of the previous block to (+1), and can be continuously read to the address common register. Is.

As described above, according to the first embodiment of the present invention, even if the parity result of the address data of the current track stored in the address data file is invalid, the representative address of the previous block is valid, After storing the addition output of the representative address in the temporary address shared register, it is written again in the address data file, and thereafter, the address shared file is read from the address data file every time. It is possible to control with a common address shared register, and it is possible to reduce the hardware scale of the RAM address generation unit.

Even if the parity check result is invalid at the head address of the tape frame, the adder circuit initializes the addition output of the representative address to the head address when the representative address value of the last address of the previous tape frame is valid. It is possible to interpolate the address at the joint of tape frames.

The parity result generating means of the address control device according to the second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of the parity result generating means of the address controller in the second embodiment of the present invention.

In FIG. 3, 1 is an address common register, 7 is an address data file for writing and reading address data and a parity result in track units (TA0, TA1, TA2), 12 is a parity result read from the address data file and temporarily A parity common register 5 for storing is a selection circuit for selecting the output of the address data file 7 and the output of the adder circuit 4 by the selection control signal h, 8
Is a selection circuit for selecting the output of the address sharing register 1 and the reproduction address data by the selection signal b, and 10a is a parity result generating means for receiving the output of the address sharing register 1 and the address reproduction data a and outputting a parity result,
Reference numeral 11 is a selection circuit for selecting the output of the parity sharing register 12 and the output of the parity result generating means 10.

The operation of the address control device of the second embodiment of the present invention constructed as above will be described below.

As described in the first embodiment of the present invention,
TA0, TA1, TA2 track header address 1
(HD1) is written to the address data file 7 by the write enable signal en2. At this time, the selection circuit 8 selects the reproduction address data a side by the temporary address selection signal b.

The address sharing register 1 selects the HD1 address once written in the address data file 7 by the selection circuit 5 and sequentially reads out the addresses of the TA0, TA1 and TA2 tracks by track time division.

Next, the parity result generating means 10 inputs the header address 2 (HD2) of the reproduction address a and the header address 1 (HD1) of TA0 read from the address data file 7 into the address sharing register 1 to perform a parity check. The parity result is obtained at the timing of the enable signal g, and the output result is written to the address data file 7 via the selection circuit 11.

After writing the parity result, the address data and the parity result are read from the address data file 7 to the address sharing register 1 and the parity sharing register 12, respectively.

The output of the parity sharing register 12 is used as the parity result i of each track for the switching condition of the selection control signal h and the evaluation comparison of the majority decision process.

Hereinafter, the same address control as in the first embodiment of the present invention is performed. As described above, according to the second embodiment of the present invention, the parity result generating means uses the parity check circuit common to the tracks and the parity sharing register to generate the parity and read from the parity area in the address data file. Therefore, it is not necessary to have the compare circuit in the parity check circuit of FIG. 4 independently for each track.

[0051]

As described above, according to the present invention, the address data of the track currently being reproduced is stored in the address data file, and at the time of the parity check, the representative address of the previous block remains the same even if the parity result is invalid. When it is valid, the address sharing register selects the representative address of the added previous block and temporarily stores it, then stores it again in the address data file and reads it from the address data file to the address sharing register every time after that. It is possible to prevent the address data of the current track from being interpolated from the erroneous address data whose parity result is invalid to the highly reliable representative address data to write the pcm data of the current track to the erroneous RAM address.
Since the address common register and the selection circuit are configured by a circuit common to the tracks, the hardware scale can be reduced.

Even if the parity check result is invalid at the head address of the tape frame, the addition output of the representative address is initialized to the head address when the representative address value of the last address of the previous tape frame is valid. Therefore, it is possible to prevent the pcm data from being written in the wrong RAM address at the joint of the tape frame.

Further, the parity check circuit common to the tracks is used to store the parity result in the address data file in track units at the time of the parity check, and thereafter, the parity result is read from the address data file every time. It is not necessary to have a parity check circuit in and the hardware scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an address control device according to a first embodiment of the present invention.

FIG. 2 is a timing chart in the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a parity circuit of an address control device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a parity check circuit of an address control device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a recording format on a magnetic tape.

FIG. 6 is a diagram showing a data format of one tape block.

FIG. 7 is a block diagram showing a configuration of an address control device in a conventional example.

[Explanation of symbols]

 1 address common register 2 address majority decision processing means 4 adder circuit 3 representative address generation means 5 selection circuit 10 parity result generation means

Claims (3)

[Claims] 1. A P that follows a sync signal and address data.
In a digital reproducing apparatus constituted by a plurality of tracks, wherein serial type digital data to which CM data is added in block units is defined as one track, an address data file for storing reproducing address data of the current block of the serial type digital data in track units. , Address sharing register that reads from the address data file each time and temporarily stores it, parity result generating means that outputs the parity result of the current block, and when the same address of the address data file is more than half, for the current block of all tracks Address majority decision processing means for judging the address data as valid; representative address generation means for storing the data of the address data file judged to be valid by the address majority decision processing means as a representative address; Is added to (+1), and a selection circuit for selecting the output of the addition circuit and the output of the address data file. When the parity result of the current track is valid, the address data file output is selected to select the address. Stored in the shared register every time, when the parity result is invalid at the time of parity check and the representative address of the previous block is valid,
An address control device that selects the address data of the adder circuit, temporarily stores it in the address common register, and then stores it again in the address data file. 2. The address control device according to claim 1, wherein the adder circuit initializes the representative address to the head address when it is determined that the representative address is valid at the final address of the tape frame. 3. The parity generation means performs checking on a track-by-track basis by a parity check circuit common to tracks.
The address control device according to claim 1, wherein the parity result of the current track is stored in the address data file at the time of the parity check, and thereafter, the parity result is read from the address data file every time.