JPH0877097A - Memory system - Google Patents

Abstract

PURPOSE: To lower minimum constitution units and enable fast access by making the data width of data of a synchronous DRAM(SDRAM) narrower than the bus width of data of a CPU. CONSTITUTION: A CPU 101 has a cache memory for data inside and performs external access in single read/write mode and burst read/write mode. The SDRAM 102 is an interface with modules 105 to 108 and controlled by a control ASIC 103. The control ASIC 103 performs control at an external access request from the CPU 101. A low-speed I/O 104 is a low-speed I/O of a ROM and passes data to the CPU 101. The SDRAM modules 105 to 108 are of the same constitution and consists of an SDRAM control circuit, a crystal oscillator, and an SDRAM. Then the SDRAM is used as a storage means and the CPU 101 is used as its read/write controller; and the bus width of data of the SDRAM is made narrower than the bus width of data of the CPU 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reads and writes a relatively large amount of data from and to a DRAM at a relatively high speed.
The present invention relates to a data processing system mainly composed of a CPU, that is, a memory system. This type of system is used, for example, in an image data processing apparatus, and the image data processing apparatus is, for example, an image pickup apparatus, an image scanner, an image display, a printer, or image data generated by one of the former two. Is used for an image processing apparatus for converting the latter two into one display information or recording image information.

[0002]

2. Description of the Related Art The processing speed of a CPU is improved, and the ratio of memory access time to the total processing time is large.
This improvement method has been considered. Recently, it has become possible to obtain a synchronous DRAM that accesses a data access command and read / write access data itself in a form synchronized with a clock signal.

This has a structure similar to that of a conventional DRAM, but the interface portion is clock-synchronized, and the address order during burst access is set in an internal register of the synchronous DRAM. it can. Therefore, at the burst read, if the address is given first, the time (CAS Latency)
After the set time), the first data can be sampled, and from there, every clock, the continuously set data can be sampled in the register set length (the Burst Length set length) and the register set order. . The same applies to burst write,
If an address is given first and write data is given for each clock, continuous writing is performed in the length and order set by the register. Unlike the conventional DRAM, it is not necessary to always give an address or change the strobe signal at the time of burst access, so that high speed data access is possible.

Since the synchronous DRAM is a completely synchronous type, the input signal is set up with respect to the clock, and the
It can be configured to satisfy the clock time, and is defined as the time from the clock even for the output signal.
Relatively easy to realize the control circuit.

Synchronous DRAM is disclosed in, for example, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent Publication No.-120114, this describes the structure of a synchronous DRAM and the operation of control signals and DRAM constituent elements in the DRAM. The synchronous DRAM operates in synchronization with the CPU clock.

[0006]

SUMMARY OF THE INVENTION Synchronous DRAM
All operate in synchronization with the clock signal, and since the access order after that is determined by the mode setting value only by inputting the first address, it can be realized with a relatively simple control circuit and high-speed access is possible. realizable.

However, since a synchronous DRAM has not existed in the past, it is difficult to obtain a small capacity one. On the other hand, the CPU tends to expand the data bus width in order to improve its access speed. Even under the present circumstances, a data bus having a 64-bit data bus width has become easy to use. Therefore, synchronous DRAM
When using as a storage means, there is a problem that the minimum constitutional unit becomes too large when it is matched with the CPU bus. For example, when the bus width of the CPU is 64 bits, even if the synchronous DRAM is composed of 16 megabits of 16 bits, four synchronous DRAMs must be used, so the minimum constitutional unit is 64 megabits = 8 megabytes.

Further, when trying to further increase the access speed, there are problems in setting up the control signal with respect to the clock signal and ensuring the hold time. In particular, a large number of synchronous DRAMs such as image memory systems
When using, the number of clock signals is required, and problems such as deterioration of waveform quality and mismatch of delay times are likely to occur. This causes malfunction and further failure.

It is a first object of the present invention to provide a system and system which make use of the characteristics of a synchronous DRAM and enable a high speed access while lowering the minimum constitutional unit. A second object is to further reduce the penalty caused by the difference in data bus width between the CPU and the synchronous DRAM. A third object is to be able to supply an appropriate clock to the synchronous DRAM even when the clock of the CPU is too fast and cannot be used as the clock of the synchronous DRAM.

A fourth object of the present invention is to reduce malfunctions and failures due to deterioration of clock waveform quality, skew, etc., and to flexibly respond to changes in the operating frequency of the CPU and make full use of the performance of the synchronous DRAM. A fifth object is to transmit the lower address at the time of continuous access with a small number of bits. A sixth object is to transmit the request address with a small number of bits. A seventh object is to perform high-speed continuous access with a small amount of read buffer memory. A simple control circuit can read a sufficient amount of unprocessed data.
An eighth object is to perform other processing while being stored in the de-buffer memory. A ninth object is to reduce the waiting time for read access. Lee
A tenth object is to prevent a contradiction due to the exchange of the execution order of the write and the write.

[0011]

[Means for Solving the Problems]

(1) In a memory system in which a synchronous DRAM is used as a storage means and a CPU is used as a read / write controller thereof, the bus width of the data of the synchronous DRAM is narrower than the bus width of the data of the CPU.

(2) In the above (1), a clock having a frequency higher than the clock of the CPU is synchronized DR.
It is characterized by supplying to AM.

(3) In the above (1), a clock having a frequency lower than that of the CPU is synchronized DR.
It is characterized by supplying to AM.

(4) In a memory system in which a synchronous DRAM is used as a storage means and a CPU is used as its read / write controller, a clock from a supply source different from the clock of the CPU is supplied to the synchronous DRAM. To do.

(5) In the above (4), a code system in which only one bit changes at a time is used as an address expression method at the time of continuous access.

(6) In the above (4), the request address is multiplexed and the synchronous DR
It is characterized in that it is transmitted to the AM control circuit.

(7) In the above (4), by having a means for monitoring the usage of the read buffer memory and controlling the signal of the CKE terminal of the synchronous DRAM,
It is characterized in that it corresponds to a read request that is less than the capacity of the read buffer memory.

(8) In the above (4), a means for monitoring the amount of use of the read buffer memory is provided, and if the amount of use of the read buffer memory does not fall below a certain amount, the next read It is characterized by not starting the de access.

(9) In the above (4), when a read instruction is recognized in a state where the write instruction can be interrupted, the read instruction is preceded.

(10) In the above (4), when the read instruction and the write instruction include the same address, the read instruction is not preceded.

(11) In the above (4), when the read instruction and the write instruction include the same address, it is possible to supply the data from the write buffer memory to the read buffer memory. Characterize.

[0022]

[Action]

(1) Since the data width of the synchronous DRAM is configured to be narrower than the data width of the CPU, the minimum configuration unit can be reduced and continuous access can be realized at high speed. Due to the characteristics, the penalties due to the different bus widths are small.

(2) Since the clock having a higher frequency than the clock of the CPU is supplied to the synchronous DRAM, the penalty due to the different bus width of the CPU synchronous DRAM can be further reduced.

(3) Since the clock having a frequency lower than the clock of the CPU is supplied to the synchronous DRAM, even if the clock of the CPU is too fast and cannot be used as the clock of the synchronous DRAM, A suitable clock can be supplied.

(4) Since the clock from the supply source different from the clock of the CPU is supplied to the synchronous DRAM, the clocks can be separated, whereby deterioration of clock waveform quality, malfunction due to skew, etc., and failure. , And it is possible to flexibly respond to changes in the operating frequency of the CPU.
It is possible to set the frequency that makes the best use of the performance of M. The distance over which the clock supplied to the synchronous DRAM is transmitted can be shortened, and high-speed access becomes possible.

(5) Since a code system in which only one bit changes at the same time is used as an address renewal method at the time of continuous access, all bits are encoded without requiring the same delay special treatment. Since it can be transmitted in a form, the number of transmission bits can be reduced.

(6) Since the request access is multiplexed and transmitted to the synchronous DRAM control circuit, the number of transmission bits can be reduced.

(7) A means for monitoring the amount of use of the read buffer memory, and a CK of the synchronous DRAM
By controlling the signal at the E terminal, the read buffer memory capacity is greater than that of the read buffer memory so that the read buffer memory capacity can be reduced.
High-speed continuous access is possible.

(8) A means for monitoring the amount of use of the read buffer memory is provided, and the next read access is not started unless the amount of use of the read buffer memory falls below a certain amount. Since it is configured like this, Synchronous DR
The control circuit of the AM can be simplified, and other processing can be performed while a sufficient amount of unprocessed data is stored in the read back-up memory.

(9) When a read command is recognized in a state in which the write command can be interrupted, the read command is preceded, so that the read speed has a great influence on the reduction of the processing speed of the CPU or the like. -Access waiting time is reduced.

(10) When the read instruction and the write instruction include the same address, the read instruction is not preceded, so that there is a contradiction caused by reading the old data before being written. Does not occur.

(11) When the read instruction and the write instruction include the same address, it is possible to supply the data from the write buffer memory to the read buffer memory. There is no inconsistency due to reading the old data before being written, and since the data can be supplied without accessing the main memory, the access time can be shortened.

[0033]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a CPU, which has an internal cache memory for instructions and data, and external access is performed by single read or write, burst read or write. 102
Is an interface with a synchronous DRAM (hereinafter sometimes referred to as SDRAM) module, and is controlled by the control ASIC 103. Control ASIC 1
Reference numeral 03 is an ASIC that controls an external access request from the CPU 101. Reference numeral 104 denotes a low-speed I / O such as ROM, which is a C via the control ASIC 103.
Pass data to PU 101. SD from 105 to 108
RAM modules (sometimes referred to as SDRAMM hereinafter), which have the same configuration.

FIG. 2 shows one of the SDRAM modules 10
5 shows the configuration. SDRAM module 105 is SD
RAM control circuit 201, crystal oscillator 202, SDRAM
It is composed of 203 to 206.

The SDRAM control circuit 201 controls the entire module 105, and the I / F ASI of FIG.
ADDR, DATA, R_ADD with C 102
R, W_ADDR, CMD, START, HIGH, N
It is interfaced using the EXT_OK signal.

ADDR indicates an address of an access request, DATA receives write data through this bus at the time of writing, and read data is sent through this bus at the time of reading. R_ADDR indicates what is written to the DATA bus at the time of reading. W_ADDR indicates which number of write data is transferred to the DATA bus at the time of writing,
MD indicates the type of access request, read / write,
Indicates single / burst (4 words, 8 words), etc.,
START is a signal indicating that a request has been issued, and is asserted for a certain period. HIGH is currently ADDR.
NEXT_OK is a signal indicating whether the content shown in is on the upper bit side or the lower bit side.
This signal is used when reading more data than the capacity of the buffer memory and indicates that new read data may be overwritten in the read buffer memory.

The SDRAM control circuit 201 also uses the SDR
It interfaces with AM 203 to 206 via RA, MD, and CONT signals.

RA is a bus of an address given to SDRAMs 203 to 206, and MD is SDRAMs 203 to 206.
Data bus between CONT, RAS, CAS,
SDRAM2 including WE, CKE, CS, DQM, etc.
This is a bus for control signals 03 to 206.

The crystal oscillator 202 is the SDRAM M 10
It supplies the clock signal used only within
The DRAMs 203 to 206 also operate on this clock signal.

FIG. 3 shows the configuration of the SDRAM control circuit 201. The SDRAM control circuit 201 includes a sequencer 30.
Write registers 302 to 305 for 1 or 4 words, selector 1 306 for selecting write data for half word to be supplied to the SDRAM in these registers 302 to 305, read from the SDRAM. Selector 23 which selects one of the data or write registers 302 to 305 and supplies it to the read register 308
07, a read register 308 for receiving read data for half a word, producing read data of a word from two times of read data if necessary, and determining the sending timing of the read data, And buffers 309 to 312. The selector 2307 is configured to be able to supply the read data from the SDRAMs 203 to 206 or one of the write registers 302 to 305 to the read register 308. Write register 302-
The data stored in 305 is stored in the SDRAM 203-
It can be supplied as read data without accessing 206.

FIG. 4 shows the I / F ASIC 1 shown in FIG.
The configuration of No. 02 is shown. The interface 102 includes a sequencer 401 and a read register 402 for four words.
~ 405, CP of these registers 402-405
Selector 40 for selecting read data to be supplied to U
6, a write register 407 that temporarily stores write data from the CPU 101, and a buffer 408 to
411. Figure 5 shows a 4-word burst
7 is a timing chart when writing is performed, and a signal indicated as SYSCLK in FIGS. 5 and 6 is SDRAMM 105-
Clocks other than 108 (101 to 104) are used, and the CPU 101 operates in synchronization with this clock. The signal labeled RAMCLK is SDRAMM 105-1.
08 is a clock used by the SDRAMM 105
~ 108 internal oscillators 20 (eg 105) each
2 is a clock generated.

In FIG. 5, from the first clock of SYSCLK, ADDR is driven to High Address, and CMD is driven to a status indicating 4-word write. And
Set HIGH to “H” level and add high to ADDR
Indicates that you are driving ss.

Start from the 3rd clock of SYSCLK
This indicates that the request is issued at the L "level. At this time, HIGH is set at the" L "level to indicate that the low address is driven to ADDR within the specified time.

From the 4th clock of SYSCLK, write data of 4 words is continuously driven to DATA every clock, and W_ADDR [1] and W_ADDR [0] are used to drive the write data. It shows what you are doing.

In this embodiment, since W_ADDR [1] and [0] do not change at the same time, a code system is used. It can be expressed whether it is write data. This decoding result is W_Reg_W
This is shown in e3 to W_Reg_We0, and the result of using this result to capture the data on the DATA bus is shown in W_Reg3 to W_Reg0.

RAMCLK is the SDRAMM 105-108
This is the clock signal of the
"L" level of T is detected, and after synchronization processing, RAMCLK of 6
Assert CS from the clock, drive a row address to RA, and assert RAS. And RAMC
A column address is driven to RA from the 7th clock of LK, CAS is asserted, data from W_Reg0 is driven to MD, and 4-word burst write is performed.

FIG. 6 is a timing chart when performing 8-word burst read. In FIG. 6, two SYSCLKs are shown in order to make it easy to see the timing of signal changes.

High to ADDR from the first clock of SYSCLK
Address is driven and CMD is driven with a status indicating 8-word read. And HIGH
It is set to H "level to indicate that the high address is being driven to ADDR.

Start from the 3rd clock of SYSCLK
It indicates that a request is issued by setting it to L ”. At this time, it indicates that HIGH is set to“ H ”level and that the low address is driven to ADDR within a specified time.

On the other hand, on the SDRAMM 105 to 108 side, the "L" level of START is detected at the fifth clock of RAMCLK, and CS is asserted from the sixth clock of RAMCLK.
Drive the row address to RA and assert RAS. And at the 7th clock of RAMCLK, C
Assert S and CAS and drive column address to RA. In this embodiment, since the cas latency is 2 clocks and the burst length is 4 words, the first read data is determined at RAMCLK 10 2 clocks after the CAS is asserted, and then 3 words. Minutes are fixed every clock. Here, burst read of 8 words is required, so RAMCLK 11, 12
CS, RA, RAS, and CAS are controlled so that the subsequent burst read for four words is executed by the clock. The data read from the SDRAMs 203 to 206 inside the SDRAMMs 105 to 108 (for example, 105) is driven onto the MD bus, temporarily stored in the read register 308 in the SDRAM control circuit 201, and then driven onto the DATA bus. To be done. And R_A
DAT using DDR [1] and R_ADDR [0]
It indicates the order of the data driven on the A bus. In this embodiment, R_ADDR
Since [1] and [0] use a code system that does not change at the same time, just like W_ADDR, decoding is performed by a simple combination circuit, and what number of read data does not generate [whisker]. Can be expressed. The result of this decoding is shown in R_Reg_We0 to R_Reg_We3, and the result of using this result to capture the data on the DATA bus is R_Reg0 to R_Reg.
3 is shown.

In the I / F ASIC 102, read / write
The fact that the data has been sent is R_AD at 10 of SYSCLK.
C, which is a data bus from the 11th clock of SYSCLK to the CPU 101, detected from the "L" level of DR [0]
Supply read data to _D from R_Reg. Then, at this time, by asserting RDY, the CPU 101 is notified that valid data is on the C_D bus. Also, from the 10th clock of SYSCLK, NEXT_OK
By asserting that R_Reg may be overwritten (that is, it can be guaranteed that the data in the register is completely used before the overwriting is executed). Notice.

[0052]

【The invention's effect】

(1) Since the data width of the synchronous DRAM is configured to be narrower than the data width of the CPU, the minimum configuration unit can be reduced and continuous access can be realized at high speed. Due to the characteristics, the penalties due to the different bus widths are small.

(2) Since the clock having a frequency higher than the clock of the CPU is supplied to the synchronous DRAM, the penalty due to the different bus width of the CPU synchronous DRAM can be further reduced.

(3) Since the clock having a frequency lower than the clock of the CPU is supplied to the synchronous DRAM, even if the clock of the CPU is too fast and cannot be used as the clock of the synchronous DRAM, A suitable clock can be supplied.

(4) Since the clock from the supply source different from the clock of the CPU is supplied to the synchronous DRAM, the clocks can be separated, whereby deterioration of clock waveform quality, malfunction due to skew, etc., and failure. , And it is possible to flexibly respond to changes in the operating frequency of the CPU.
It is possible to set the frequency that makes the best use of the performance of M. The distance over which the clock supplied to the synchronous DRAM is transmitted can be shortened, and high-speed access becomes possible.

(5) Since a code system in which only one bit changes at the same time is used as an address renewal method at the time of continuous access, all bits are encoded without requiring the same delay special treatment. Since it can be transmitted in a form, the number of transmission bits can be reduced.

(6) Since the request access is multiplexed and transmitted to the synchronous DRAM control circuit, the number of transmission bits can be reduced.

(7) A means for monitoring the usage of the read buffer memory is provided, and CK of the synchronous DRAM is provided.
By controlling the signal at the E terminal, the read buffer memory capacity is greater than that of the read buffer memory so that the read buffer memory capacity can be reduced.
High-speed continuous access is possible.

(8) A means for monitoring the amount of use of the read buffer memory is provided, and the next read access is not started unless the amount of use of the read buffer memory falls below a certain amount. Since it is configured like this, Synchronous DR
The control circuit of the AM can be simplified, and other processing can be performed while a sufficient amount of unprocessed data is stored in the read back-up memory.

(9) When the read command is recognized in a state where the write command can be interrupted, the read command is preceded, so that the read speed has a large influence on the reduction of the processing speed of the CPU or the like. -Access waiting time is reduced.

(10) When the read instruction and the write instruction include the same address, the read instruction is not preceded, so that there is a contradiction caused by reading the old data before being written. Does not occur.

(11) When the read instruction and the write instruction include the same address, since the data can be supplied from the write buffer memory to the read buffer memory, There is no inconsistency due to reading the old data before being written, and since the data can be supplied without accessing the main memory, the access time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of SDRAMM 105 shown in FIG.

3 is a block diagram showing a configuration of an SDRAM control circuit 201 shown in FIG.

FIG. 4 is a block diagram showing a configuration of an I / F ASIC 102 shown in FIG.

FIG. 5 is a timing chart showing a signal change in each part of the circuits shown in FIGS. 2 to 4 when performing a 4-word burst write.

FIG. 6 is a timing chart showing a signal change in each part of the circuits shown in FIGS. 2 to 4 when performing 8-word burst write.

[Explanation of symbols]

301: Sequencer 302-305: Write register 306: Selector 1 307: Selector 2 308: Read register 309-312: Buffer 401: Sequencer 402-405: Read register 406: Selector 1 407: Selector 2 408: Write register 409-412: Buffer

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Satoshi Ishii 1-3-6 Nakamagome, Ota-ku, Tokyo Ricoh Co., Ltd.

Claims (11)

[Claims] 1. A synchronous DRAM using C as a storage means.
A memory system that uses a PU as its read / write controller, characterized in that a bus width of data of a synchronous DRAM is narrower than a bus width of data of a CPU. 2. The memory system according to claim 1, wherein a clock having a frequency higher than that of the CPU is supplied to the synchronous DRAM. 3. The memory system according to claim 1, wherein a clock having a frequency lower than that of the CPU is supplied to the synchronous DRAM. 4. A synchronous DRAM is used as a storage means and C
A memory system that uses a PU as its read / write controller, wherein a clock from a supply source different from the clock of the CPU is supplied to the synchronous DRAM. 5. The memory system according to claim 4, wherein a code system in which only one bit changes at a time is used as an address expression method during continuous access. 6. The memory system according to claim 4, wherein the request address is multiplexed and transmitted to a synchronous DRAM control circuit. 7. The read buffer according to claim 4,
Synchronous D with means to monitor memory usage
By controlling the signal of the CKE terminal of RAM,
A memory system characterized in that it corresponds to a read request that is less than the capacity of the buffer memory. 8. The read buffer according to claim 4,
It has a means to monitor the memory usage, and if the usage of the read buffer memory does not drop below a certain level, the next read
A memory system characterized by not starting access to memory. 9. The memory system according to claim 4, wherein when a read instruction is recognized in a state where the write instruction can be interrupted, the read instruction is preceded. 10. The memory system according to claim 9, wherein when the read instruction and the write instruction include the same address, the read instruction is not preceded. 11. The write buffer according to claim 9, when the read instruction and the write instruction include the same address.
A memory system characterized in that data can be supplied from the memory to the read buffer memory.