JPH0876874A - Device and method for controlling clock of central processing unit - Google Patents

Abstract

PURPOSE: To control a clock of CPU so as to execute an operation with a low power consumption by automatically changing-over the clock into the absolute min. operation clock of CPU within a range where the requesting performance of a program to run is satisfied in the operation environment of a multi- task. CONSTITUTION: The clock controlling device is provided with a performance information of a central processing unit(CPU) 1, which is required at every task, and also provided with more than one performance information setting circuits 9 and 10 setting performance information of CPU 1 at every task, a selecting information generating circuit 7 deciding the clock frequency of CPU 1 so as to permit the operation to be executed with absolute min. performance which is required by the task in starting, an oscillation circuit 6 generating plural clock signals and a clock selecting circuit 5 selecting one of the clock signals and giving it to the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control device and a clock control method for a central processing unit, and is used for an information processing device represented by a personal computer (hereinafter simply referred to as "personal computer") and a small information terminal. Central processing unit (hereinafter, "CPU")
(Hereinafter abbreviated)), the clock control device and the clock control method of the central processing unit suitable for achieving the power saving.

[0002]

2. Description of the Related Art In recent years, due to an increase in power demand, power consumption has become a problem throughout society. On the other hand, under such circumstances, the small computer market has expanded rapidly, and the number of PCs installed in the world market has reached 30.
The number exceeds 0,000. In addition, the demand for portable information devices that use batteries is also increasing, and lowering the power consumption of such devices is becoming an important issue.

Therefore, in particular, the CPU which is the center of the information processing apparatus such as the personal computer and the portable information equipment.
Attention has been paid to the reduction of the power consumption, and many methods have been tried so far. One of the powerful methods of reducing the power consumption of the CPU is a method of controlling the clock of the CPU. This achieves the suppression of the power consumption of the CPU by operating the CPU with a low speed clock under a specific condition. Here, the specific condition is that the power supply voltage has dropped to an arbitrary level, an interrupt to the CPU has occurred, and the like.

Now, regarding such a method for reducing the power consumption of a CPU, as an invention to be applied to an information processing apparatus having a multitasking function which is strongly demanded for realizing a communication function such as an information terminal, there is disclosed in Japanese Patent Laid-Open No. Sho 62-62. There is a "transition method to a low power consumption state" described in Japanese Patent Publication No. 150416. The present invention, in a system equipped with an operating system (hereinafter, abbreviated as “OS”) that allows a plurality of tasks to operate in parallel, has means for detecting the presence / absence of a task to be executed and low power consumption for a computer system. This is a transition method in which a means for bringing the computer into a state is provided and the computer system is brought into a low power consumption state when there is no task to be executed.

[0005]

The above prior art describes a method for shifting a computer system to a low power consumption state. However, the above-mentioned conventional technique determines whether or not there is a task to be executed, and operates in the low power consumption state only when there is no task to be executed, and operates in the low power consumption state during task execution. Therefore, there is a problem that its application range is narrow.

Further, in recent years, multimedia (moving images, voices, etc.) which requires a great deal of computing performance has been often incorporated in the system. For example, a case where word processing or spreadsheet software and video conferencing software are operated by one personal computer can be considered. Here, the former word processor or spreadsheet software is a CPU
Tens of MIPS (Million instructions / second, Million Instruct
Ion Per Second) performance is enough to use, but
The latter video conferencing software requires communication functions in addition to video and audio compression / expansion processing.
S performance is required. On the other hand, the performance of CPUs is rapidly increasing at a rate of about 1.6 times per year, and it is only a few times in a few years.
It can be expected to reach the performance of 00 MIPS. However, the difference in power consumption between the operating states of several tens of MIPS and several hundreds of MIPS is very large, and therefore several hundred M
Operating tens of MIPS software on a CPU having IPS performance is a waste of power.

Therefore, there has been a demand for automatically switching the performance according to the software used, but in the prior art, there is no idea that the performance of the CPU is switched according to the operation speed of the program. was there.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and its object is to reduce the performance depending on the performance of the program operated by the information processing apparatus in a multitasking operating environment. When executing a processing program, the minimum required C that satisfies the required performance
(EN) Provided are a clock control device and a clock control method for a CPU capable of automatically switching to an operation clock of a PU to save power consumption and realizing operation with low power consumption even during task execution.

Another object of the present invention is to determine whether the information processing apparatus is operated by an AC power source or a battery, and only when the information processing apparatus is operated by a battery, a clock of a CPU which operates with low power consumption. A control device and a clock control method are provided.

[0010]

In order to achieve the above object, the configuration of the invention relating to the clock control device of the central processing unit of the present invention is a multitasking operating system capable of activating and switching a plurality of tasks and executing them. A memory that stores a program, and executes the program under the multitasking operating system environment,
Further, in a clock control device of a central processing unit of an information processing device including a central processing unit whose operation speed is determined based on a given clock frequency, it is necessary for each task activated under the multitasking operating system environment. By providing the performance information of the central processing unit to be set, one or more performance information setting circuit for setting the performance information of the central processing unit for each task, and one or more performance information set in the performance information setting circuit. A selection information generation circuit that generates selection information so as to determine the clock frequency of the central processing unit so as to operate with the minimum required performance required by the task being activated, and generates a plurality of clock signals. And a clock for selecting one of the plurality of clock signals according to the selection information and giving it to the central processing unit. It is obtained as provided 択回 path.

More specifically, in the clock controller of the central processing unit, the central processing unit, the one or more performance information setting circuits, the selection information generating circuit, and the clock selection circuit are integrated in one chip. It was done like this.

In order to achieve the above-mentioned object, the configuration of the invention relating to the clock control method of the central processing unit of the present invention has a memory for storing a multitasking operating system and a program capable of activating and switching a plurality of tasks. And a central processing unit which executes the program under the multitasking operating system environment and whose operation speed is determined based on a given clock frequency, the clock control method of the central processing unit of the information processing apparatus. In the above, the performance information of the central processing unit required for each task started under the multitasking operating system environment is provided, and one or more performance information setting circuits, a selection information generation circuit, and a plurality of clock signals are provided. An oscillator circuit for generating a clock signal and a clock selection circuit, The performance information setting circuit sets performance information of the central processing unit for each task, and the selection information generation circuit uses one or more performance information set in the performance information setting circuit to determine whether the task being started up. The selection information is generated so as to determine the clock frequency of the central processing unit so as to operate with the minimum necessary performance required, and the clock selection circuit generates the selection information from the oscillator according to the selection information. One of the plurality of clock signals is selected and given to the central processing unit.

More specifically, in the clock control method for the central processing unit, the multitasking operating system manages the performance information required by each task for each task, and when the task is started, Having the step of setting the performance information of the task to be activated to the performance information setting circuit, and further, invalidating the performance information of the corresponding task set in the performance information setting circuit when the task is terminated. To have.

More specifically, in the clock control method for the central processing unit, when starting the task, a step of registering performance information of the task in a task management table and reading performance information of all the running tasks. A step of calculating the minimum required performance information of the central processing unit by using the performance information of all the tasks, and setting the performance information of the central processing unit in the selection information generation circuit, Further, when the task is terminated, the performance information of the task is deleted from the task management table, the performance information of all the running tasks is read, and the performance information of all the tasks is used to obtain the minimum required information. A step of calculating the performance information of the central processing unit and a step of setting the performance information of the central processing unit in the selection information generating circuit. It is that to have a flop.

In order to achieve the above-mentioned object, another configuration of the invention relating to the clock control device of the central processing unit of the present invention is the clock control device of the central processing device,
According to the program, the central processing unit generates clock selection information of the central processing unit from one or more performance information obtained from the performance information setting circuit.

In still another configuration, in the clock control device of the central processing unit, the information processing device can use either a battery or an AC power supply as a power supply means, and a discrimination means of the power supply means is provided. Then, when the battery is used and when the AC power source is used, the central processing unit is
The clock selection information of the central processing unit is generated from one or more pieces of performance information obtained from the performance information setting circuit.

[0017]

According to the present invention, the CPU has the performance information unique to each program, and the CPU required for the selection information generation circuit is selected by the performance information of the operating program at the time of starting and ending the task in multitasking. Determine performance,
Controls the CPU clock. Therefore, even when a plurality of programs are executed in parallel, the operation clock of the CPU is determined in consideration of the required performance of each program, so that the operation can be performed with the necessary and minimum power.

Further, the power supply detection circuit determines whether the power supply of the information processing apparatus is an AC power supply or a battery, and when the power supply is a battery, the selection information generation circuit operates the CPU clock in a low state. As a result, it operates with low power consumption only when it is operated with a battery.

[0019]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 12. [Embodiment 1] Hereinafter, a first embodiment according to the present invention will be described with reference to FIG.
It will be described with reference to FIGS. First, the circuit configuration of the CPU clock control device according to the present invention will be described with reference to FIG. FIG. 1 shows a CP according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a circuit configuration of a U clock control device.

In FIG. 1, the oscillator circuit 6 can generate clocks of eight kinds of frequencies. The selection information circuit 7 is a circuit for controlling the clock selection circuit 5. The performance information setting circuits 9 and 10 are circuits for holding task load information. The memory 1 has a CPU 1
Stores programs and data used by. And
As shown in the figure, the task management program 14 and the task management table 15 are stored in this memory 13.

MI to CPU 1 to 5 to 40 MIPS
Eight levels of operating states can be specified at PS intervals. The oscillator circuit 6 outputs clocks of eight types of frequencies corresponding to the above levels.

Further, the information processing apparatus according to the present invention is premised on that a multitasking OS (Operating System) is started and various programs are executed on the OS. The OS includes a task management program 14 that controls activation and termination of tasks. Further, the task management table 15 includes various information necessary for controlling the task management program 14. Specifically, for each task,
In addition to the task ID that uniquely identifies each task, the required memory capacity, etc., the performance information and the pending flag characteristic of the present invention are registered as items.

The performance information is the load capacity of the CPU designated according to the contents of the program executed by each task. The pending flag is a flag indicating that the performance information of a certain task is in a waiting state for setting in the performance information setting circuit.

The role of the pending flag will become clear later when the operation of the present invention is described using a flow, so the performance information will be described first. The performance information is specified according to the contents of the program executed by the task, as described above. For example, in the case of a program related to a word processor, the editing program is 10 MIPS,
It is assumed that the print program requires a CPU performance of 5 MIPS.

In such a situation, when the task management program 14 sets the performance information of 10 MIPS in the performance information setting circuit 9 when activating the task of the editing program, the selection information circuit 7 causes the CPU 1 corresponding to 10 MIPS. Generate selection information corresponding to the operating frequency of.
According to this selection information, the clock selection circuit 5 selects the corresponding clock and sends the CP via the clock line 4.
Supply to U1. As a result, the CPU1 has 10 MIPS
Works with. This is the basic mechanism of the present invention.

Subsequently, when printing the document edited by the word processor, the task management program 14 activates the task of the print program. At this time, performance information of 5 MIPS is set in the performance information setting circuit 10. The selection information circuit 7 is the 10 MIPS set in the performance information setting circuit 9.
The selection information corresponding to the operating frequency of the CPU 1 corresponding to 15 MIPS is generated from the performance information of 1 and the performance information set in the performance information setting circuit 10. According to this selection information, the clock selection circuit 5 selects a corresponding clock and supplies it to the CPU 1 via the clock line 4. As a result, CPU1 changes from 10 MIPS to 15 MIPS.
Switch to a faster operating mode.

It should be noted that the performance information is represented by the processing capability for each time, and therefore, when both tasks are executed in parallel, both tasks are added.

According to the present invention, even when printing is executed during editing by the word processor, the performance of the CPU 1 is improved so as to be commensurate with the load so that sufficient operation for editing can be performed while printing. You can get the environment.

Next, the detailed circuit configuration of the performance information setting circuit will be described with reference to FIG. FIG. 2 is a block diagram showing the circuit configuration of the performance information setting circuit according to the first embodiment of the present invention.

As described above, the performance information setting circuit 9
This is a circuit for holding performance information for each task activated by the task management program 14. When the task is started, the performance information is set in the performance information setting register 22, the task ID of the task is set in the task ID setting register 20, and the task ID setting register 20 is set.
And enable information indicating that the setting of the performance information setting register 22 is valid is set in the enable setting register 21. The enable setting register 21 indicates a valid state when the logical value is "1" and an invalid state when the logical value is "0". Therefore, the AND circuit 23 sets the information in the performance information setting register 22 to the performance information line 1 only when the AND circuit 23 is in the valid state.
Output to 1. Conversely, in the invalid state, the logical value “0” is output to the performance information line 11.

Here, the enable setting register 21 is
The valid state indicates that the value set in this performance information setting circuit is valid, while the opposite invalid state indicates that the value set in this performance information setting circuit is invalid, so to speak, the value is set. It has not been done.

Further, the task ID setting register 20, the enable setting register 21, and the performance information setting register 2
The setting information of No. 2 can be read by the CPU 1 via the address bus 2 and the data bus 3, and the task management program 14 can know the setting information of the performance information setting circuit 9.

Next, the detailed circuit configuration of the selection information generating circuit will be described with reference to FIG. FIG. 3 is a block diagram showing the circuit configuration of the selection information generation circuit according to the first embodiment of the present invention.

Recall that the present embodiment was able to specify eight levels of operating states to the CPU1. Therefore, the selection information generation circuit 7 handles 3-bit information.

In FIG. 3, the adder circuit 30 adds 3-bit information. Carry signal line 31 indicates a logical value "1" when the carry of the addition result is carried. Decoder circuit 3
5 is 3 bits.

The adder circuit 30 outputs the addition result of the performance information (0 to 7) of the performance information line 11 and the performance information (0 to 7) of the performance information line 12 to the logical sum circuit 32 to the logical sum circuit 34. . When the addition result is 7 or less, the carry signal line 31 becomes the logical value “0”, and the OR circuit 32 to the OR circuit 34.
Shows the addition result of the addition circuit 30 as it is to the decoder circuit 3
Output to 5.

On the other hand, when the addition result of the adding circuit 30 is 8 or more, the addition result 7 is output to the decoder circuit 35. In short, the carry signal line 31 has the logical value "1", and the OR circuits 32 to 34 all output the logical value "1" to the decoder circuit 35. Such case classification is necessary to keep the highest level of performance information at 7 because the number of clocks that the clock selection circuit 5 can select is limited to eight. For example, if the clock selection circuit 5 can select 16 kinds of clocks, the configuration of this selection information circuit also becomes different.

In this way, the OR circuit 32 to the OR circuit 3
The decoder circuit 35 receives the performance information output by
Information for selecting the corresponding clock signal is output to the selection information signal line 8.

As described above, the selection information circuit 7 is
The clock selection information generated from the information on the performance information lines 11 and 12 is output to the selection information signal line 8 to cause the clock selection circuit 5 to select an appropriate clock.

Next, details of the task management program 14 will be described with reference to FIGS. 4 and 5. FIG. 4 is a flow chart showing the operation of the task management program when the task is activated. FIG. 5 is a flowchart showing the operation of the task management program at the end of the task.

First, the operation when the task management program 14 activates a task will be described with reference to FIG. First, a predetermined task activation process performed by a normal multi-task OS is performed (S400).
Here, the contents of the task management table 15 are updated. That is, the task ID of the newly started task, the required memory capacity, the performance information, etc. are registered in the task management table 15.

Next, the enable information set in the performance information setting circuits 9 and 10 is read (S401), and it is checked whether the information is valid or invalid (S402). This is to check if there is an unused performance information setting circuit.

If either of the enable information is invalid, the task ID of the task to be activated, the enable valid information and the performance information are set in the corresponding performance information setting circuit (either 9 or 10) (S403). ). As a result, the CPU 1 operates at the optimum clock frequency under the environment in which the new task is activated, and the task activation process ends.

On the other hand, in step S402, if all the enables are valid, the performance information setting circuits are all used for other tasks. In this case, it is necessary to check whether or not the performance information of these performance information setting circuits 9 and 10 should be updated by the newly started task.

In this case, the performance information of these performance information setting circuits 9 and 10 is read (S404).

Next, the read performance information is compared with the performance information of the task to be started (S405). As a result, if the performance information of the task to be activated has the lowest value, the CP that has already been activated is sufficient for the CP.
The performance of U is increasing. Therefore, in this case, without updating the performance information setting circuits 9 and 10, the pending flag of the task to be activated in the task management table 15 is set to the valid state (S407), and the processing is ended. here,
The pending flag indicates that the task is activated, but that does not affect the performance information setting circuits 9 and 10. This pending flag is referred to when the subsequent task ends.

On the other hand, if the performance information of the task to be started is not the lowest value, the task corresponding to this started task is
CPU performance must be increased. Therefore, in this case, the task ID, enable valid information, and performance information of the task to be activated are set in the performance information setting circuit (either 9 or 10) having the lowest value (S406). . Then, the pending flag of the process corresponding to the process ID of the rewritten performance information setting circuit is validated, and the process ends. This is because the task that has already been activated is not reflected in the performance of the performance information setting circuit due to the rewriting, so that the task is restored later.

As a result, the CPU 1 operates at the optimum clock frequency under the environment in which the new task is activated, and the task activation process is terminated.

As described above, this embodiment is composed of two performance information setting circuits 9 and 10. However, it is possible to cope with the case where the number is increased, and the more the number, the finer the clock becomes. The control becomes possible, and the effect of power saving can be obtained.

First, the operation when the task management program 14 terminates a task will be described with reference to FIG. First, the performance information setting circuits 9 and 10
The task ID information set in is read (S50
1), the task ID of the task whose information is about to end
It is checked whether they match with (S502). This is to check whether the performance of the task to be finished is reflected in the performance information setting circuit.

If the task ID stored in one of the performance information setting circuits and the task ID information of the task to be ended match, the corresponding performance information setting circuit (either 9 or 10), Enable / disable information is set (S503). This corresponds to erasing the information in the performance information setting circuit.

Next, it is checked whether or not there is a task whose pending flag is valid in the task management table 15 (S504). When the pending flag is in the valid state, it can be considered that the task is activated and is in a waiting state for setting the performance in the performance information setting circuits 9 and 10.
Therefore, if there is a task with the pending flag in the valid state, the task I
D, enable validity information and performance information, step 50
The performance information setting circuit (either 9 or 10) corresponding to 3 is set (S505). Then, the pending flag of the set task is set to the invalid state (S50
6).

As a result, the CPU 1 operates at the optimum clock frequency under the environment where the task is completed.

Finally, predetermined task end processing performed by a normal multitask OS is performed (S507), such as deleting information about the task to be ended from the task management table 15 and the task end processing is ended.

On the other hand, in step S502, if either task ID information does not match, it means that the task to be finished has no influence on the determination of the operating frequency of the CPU 1. Therefore, steps S503 to S506 are skipped, step S507 is executed, and the task end processing is ended.

Similarly, in step S504, if there is no task with the pending flag in the valid state, it means that there is no task that should influence the determination of the operating frequency of the CPU 1. Therefore, steps S505 and S5
Step 06 is skipped over step 06, and the task end processing is ended.

Finally, an example of a specific operation of the embodiment described above with reference to FIG. 6 will be described in the order of time. Figure 6
FIG. 4 is a timing chart showing the relationship between the status of each task and performance information in chronological order.

More specifically, FIG. 6 shows events indicating the activation and termination of each task, the state of the activated task (transition between the execution state and the standby state), the performance information setting circuit 9 and the performance information setting circuit. Performance information set to 10 and CP
It shows the performance information corresponding to the actual operation of U1.
As the unit of the time axis in this figure, six time slots (0 to 5) starting from each event are used.

As shown in FIG. 6, task A, task B, and task C are activated. The performance information corresponding to each of these is set to "2", "4", "5". Try.

First, in time slot 0, only the OS is operating, and there is no task being executed. At this time, the enable is set to the invalid state in the performance information setting circuit 9 and the performance information setting circuit 10, and the CPU 1
Is operating at the minimum performance “0”.

Next, in the time slot 1 in which the task A is activated, the task management program 14 sets the enable valid information and the performance information "2" in the performance information setting circuit 9. As a result, the CPU 1 operates with the performance corresponding to the performance information “2”.

Next, in the time slot 2 in which the task B is activated, first, the task B becomes the execution state, and the task A
Transitions from the running state to the waiting state. Further, the task management program 14 sets enable valid information and performance information “4” in the performance information setting circuit 10. As a result, the performance information “2” set in the performance information setting circuit 9 and the performance information “4” set in the performance information setting circuit 10 are added in the selection information generation circuit 7, and the CPU 1 sets the performance information “6”. "
Operates with performance equivalent to. Under this operating environment, task A and task B make a transition between the execution state and the standby state.

Next, in the time slot 3 in which the task C is activated, first, the task C becomes the execution state and the task A
Transitions from the running state to the waiting state. Since the performance information of the started task C is “5”, the task management program 14 uses the performance information setting circuit 9 and the performance information setting circuit 1.
The performance information set to 0 is compared, and the performance information “5” is set to the performance information setting circuit 9 having the lower performance information. As a result, the performance information is originally "9".
However, in this embodiment, since the maximum level of performance information is "7", the CPU 1 operates with the performance corresponding to the performance information "7".

The task management program 14 also sets the pending flag of the task A in the task management table 15 to the valid state. Under such an operating environment, the task A, the task B, and the task C make a contradictory transition between the execution state and the standby state.

Next, in the time slot 4 in which the task B is finished, first, the task C becomes the execution state, and the task B
Ends. Further, the task management program 14 sets, in the performance information setting circuit 10, the performance information “2” of the task A whose pending flag is in the valid state, instead of the performance information “4” of the task B. That is, the performance information of the task A that has been ejected is restored. As a result, the CPU 1 operates with the performance corresponding to the performance information “7”. Under this operating environment, task A and task C
It makes a contradictory transition between the execution state and the standby state.

Finally, in the time slot 5 in which the task A is finished, first, the task C becomes the execution state and the task A is finished. Furthermore, the task management program 14
The enable / disable information is set in the performance information setting circuit 10 to disable the performance information “2” of the task A to be ended.
As a result, only the performance information setting circuit 9 becomes effective, and C
PU1 operates with the performance corresponding to the performance information “5”.

In the first embodiment described above, the performance information setting circuit has two structures. However, the number of performance information setting circuits is not limited to this. Furthermore, fine control is possible. Similarly,
The clock frequency of the CPU 1 is not limited to eight types, and more power saving control can be performed by increasing the selection of frequencies.

[Second Embodiment] A second embodiment according to the present invention will be described below with reference to FIG. FIG. 7 is a block diagram showing the circuit configuration of the clock control device for the CPU according to the second embodiment of the present invention.

The second embodiment has the same basic structure and operation and the same idea, but is characterized in that the circuit structure is integrated into one chip.

The oscillator 62 generates a clock signal, and the frequency dividing circuit 61 generates eight types of clock signals having different frequencies. Further, the low power CPU 60 is the CPU 1
, Performance information setting circuits 9 and 10, and selection information generation circuit 7
The clock selecting circuit 5 and the frequency dividing circuit 61 are integrated on one chip.

In this embodiment, since the circuit section such as the performance information setting circuit 9 is integrated in the low power CPU 60, there is an advantage that the number of parts of the entire circuit configuration can be reduced.

Further, the low-power CPU 60 uses the frequency dividing circuit 6
Since 1 is built in, only one clock signal line from the oscillator 62 is required. As described in the first embodiment, the circuit incorporated in the low-power CPU 60 can be configured with relatively simple hardware, so that the circuit scale is relatively small and the number of pins is much larger than that of the CPU 1. Since it does not occur, it can be sufficiently configured as an integrated circuit.

As an effect of the second embodiment, not only downsizing and power saving by integrating the circuit but also hardware mounting design can be facilitated. That is, by incorporating the clock selection circuit 5 inside the chip, technical problems in mounting such as reflection and interference of the clock signal, which become a problem with the speeding up of the CPU clock, are alleviated.

[Third Embodiment] A third embodiment of the present invention will be described below with reference to FIGS. 8 to 10. Figure 8
It is a block diagram which shows the circuit structure of the clock control device of CPU which concerns on the 3rd Example of this invention.

The feature of the third embodiment is that the selection information generated by the performance information setting circuits 9 and 10 and the selection information setting circuit 7 in the first embodiment is set in accordance with the task management program 71 shown in FIG. The selection information setting circuit 70 generates the information.

Here, the selection information setting circuit 70 is a circuit for setting selection information to be given to the clock selection circuit 5.
The task management program 71 is a program having a function of generating selection information.

Hereinafter, the function of the selection information setting circuit 70 will be described in detail with reference to FIG. FIG. 9 is a block diagram showing the circuit configuration of a selection information setting circuit according to the third embodiment of the present invention.

Also in this embodiment, the performance level that can be handled is 8
Phases are assumed, so register 80 is 3
Is a bit. In the selection information setting circuit 70, the CPU 1 can set the 3-bit performance information and read the set performance information via the address bus 2 and the data bus 3. The performance information to be set is the first embodiment.
Unlike, the performance information setting circuit does not generate
It is generated by the task management program 71. This performance information is stored in the decoder circuit 35 in the selection information setting circuit 70.
And the decoder circuit 35 generates clock selection information from the performance information and outputs it to the selection information signal line 8.
As a result, the operating frequency of the CPU 1 is finally determined.

Next, taking into consideration the difference from the first embodiment,
The details of the operation of setting the performance information of the task management program 71 will be described in order of FIG. FIG. 10 is a flowchart showing the operation of setting the performance information of the task management program.

First, the task management program 71 checks whether the processing to be performed from now on is task start processing or task end processing (S900).

If it is the starting process, step S400 in FIG.
Similarly, a predetermined task generation process is performed (S901).
Here, various information corresponding to the task to be activated is registered in the task management table 15.

On the contrary, if it is the end processing, step S in FIG.
Similar to 507, a predetermined task end process is performed (S90
2). Here, various information corresponding to the task to be ended is deleted from the task management table 15.

After steps S901 and S902, it is checked whether or not there is an active task (S9).
03). This check may be performed by checking whether the task management table 15 is registered.

If registered, the performance information of all registered tasks is read (S904). Next, the total sum of the read performance information is obtained, performance information of the CPU 1 is generated (S905), and it is checked whether the value of the performance information of the CPU 1 exceeds "8" (S906). If it does not exceed, the performance information of the CPU 1 is set in the register 80 (S907).

On the contrary, if the value of the performance information of the CPU 1 exceeds "8", the value of the performance information of the CPU 1 is "7".
As (maximum value of performance information in this embodiment) (S90
8) and set in the register 80 (S907).

If there is no task being started in step S903, the value of the performance information of the CPU 1 is set to "0" (minimum value of the performance information in this embodiment) (S909) and set in the register 80. (S907).

In this way, if the task management program 71 has a function of generating selection information to be given to the CPU 1 from performance information at the time of starting and ending a task,
This brain can be realized by software. Therefore, in the present embodiment, unlike the first embodiment, the performance information setting circuits 9 and 10 are unnecessary, and there is an advantage that the number of hardware parts can be reduced.

[Embodiment 4] A fourth embodiment of the present invention will be described below with reference to FIGS. 11 and 12. The feature of this embodiment is that the performance of the CPU 1 is controlled according to the power supply used.

Considering this, the circuit configuration of the clock control device of the CPU and the configuration of the power supply circuit according to the present embodiment will be described with reference to FIG. FIG. 11 is a block diagram showing the circuit configuration of the clock control device for the CPU and the configuration of the power supply circuit according to the fourth embodiment of the present invention.

The selection information generating circuit 100 can generate clock signal selection information from the performance information. The power supply detection circuit 110 is a circuit for identifying the power supply means. Further, the power supply control circuit 111 controls whether the power supply means is the AC battery 113 or the battery 114. The selection circuit 112 of the power supply means is a circuit for switching which power supply is actually used. Where AC
It is assumed that the power supply 113 is supplied with power from the outside of the information processing apparatus using this CPU, and the battery 114 is built in the information processing apparatus. One of the AC power supply 113 and the battery 114 is used as a power supply means, and which one is used is determined by the power supply control circuit 111. In response to an instruction from the power supply control circuit 111, the selection circuit 112 causes the AC power supply 113 and the battery 114 to operate.
One of the above is selected and power is supplied by the information processing apparatus.

Further, the power supply detection circuit 110 enables the information that the power supply control circuit 111 has instructed the selection circuit 112 to be read by the CPU 1, and can detect which power supply means the CPU 1 is currently using. .

The selection information generation circuit 100 selects the performance information of the CPU 1 depending on the data input via the address bus 2 and the data bus 3 for which the CPU 1 sets the information.

The configuration and operation of the selection information circuit 100 will be described in detail below with reference to FIG. 12
FIG. 8 is a block diagram showing a circuit configuration of a selection information circuit according to a fourth example of the present invention.

The 2-port RAM 101 is composed of an address of 4 bits, data of 3 bits, and the decoder circuit 102 of 3 bits. The performance level of this example is also
Eight levels from “0” to “7” are assumed. Information is set in the 2-port RAM 101 from the address bus 2 and the data bus 3. According to the set information, the 4-bit performance information of the performance information lines 11 and 12 becomes address information, and the 3-bit data read as a result is sent to the decoder circuit 102. From the transmitted data, the decoder circuit 102 outputs 8-bit clock selection information and selects one of the eight types of clock signals.

Here, using Table 1 and Table 2 below, this
An example of information set in the port RAM 101 and output will be described. Table 1 is a table contrasting the setting of the performance information in the normal operation mode using the AC power supply 113.

[0096]

[Table 1]

Table 2 is a table showing the setting comparison in the power saving operation mode using the battery 114.

[0098]

[Table 2]

The setting of the performance information shown in Table 1 is basically based on the same algorithm as that of the first embodiment and is an algorithm for adding the information on the performance information lines 11 and 12. Therefore, the sum of the performance information of the tasks being executed is used as the actual clock level of the CPU 1.

On the other hand, the setting of the performance information shown in Table 2 is
This is an algorithm used when it is used in a battery drive, and is an algorithm such that the CPU 1 does not operate at full power. This algorithm is devised to set the clock level 5 when the CPU 1 does not use the settings of the clock levels 6 and 7 which operate at high speed, that is, when the sum of the performance information lines 11 and 12 is 6 or more.

As described above, in the fourth embodiment, by controlling the clock frequency given to the CPU 1 according to the usage state of the power supply means, the processing performance is deteriorated when the battery 114 is used. , It has the effect of extending the operating time of the battery being used.

[0102]

According to the present invention, in a multitasking operating environment, when a processing program that requires low performance is executed in accordance with the performance of the program operated by the information processing apparatus, the required minimum required performance is satisfied. It is possible to provide a clock control device and a clock control method for a CPU that can automatically switch to a limited operating clock of a CPU to save power consumption and realize operation with low power consumption even during task execution.

Further, according to the present invention, it is determined whether the information processing apparatus is operated by an AC power source or a battery, and a CPU which operates with low power consumption only when operated by the battery.
The clock control device and the clock control method can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a clock control device for a CPU according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a performance information setting circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a circuit configuration of a selection information generation circuit according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of a task management program when a task is activated.

FIG. 5 is a flowchart showing the operation of a task management program at the end of a task.

FIG. 6 is a timing chart showing the relationship between the status of each task and performance information in chronological order.

FIG. 7 is a block diagram showing a circuit configuration of a clock control device for a CPU according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a circuit configuration of a clock control device for a CPU according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a circuit configuration of a selection information setting circuit according to a third embodiment of the present invention.

FIG. 10 is a flowchart showing an operation of setting performance information of a task management program.

FIG. 11 is a block diagram showing a circuit configuration of a clock control device for a CPU and a configuration of a power supply circuit according to a fourth example of the present invention.

FIG. 12 is a block diagram showing a circuit configuration of a selection information circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 ... CPU, 2 ... Address bus, 3 ... Data bus, 4 ...
CPU 1 clock line, 5 ... Clock selection circuit, 6 ... Oscillation circuit, 7 ... Selection information generation circuit, 8 ... Selection information signal line,
9, 10 ... Performance information setting circuit, 11, 12 ... Performance information line, 13 ... Memory, 14 ... Task management program, 15
… Task management table. 20 ... Task ID setting register, 21 ... Enable setting register, 22 ... Performance information setting register, 23 ... AND circuit. 30 ... Adder circuit, 31
... carry signal line, 32 to 34 ... OR circuit, 35 ... decoder circuit. 60 ... CPU, 61 ... Dividing circuit, 62 ... Oscillator. 70 ... Selection information setting circuit, 71 ... Task management program. 80 ... Register. 100 ... Selection information generation circuit,
110 ... Power supply detection circuit, 111 ... Power supply control circuit, 112
... Selection circuit, 113 ... AC power supply, 114 ... Battery. 101
... 2-port RAM, 102 ... Decoder circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinya Oba 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (7)

[Claims] 1. A memory for storing a multitasking operating system and a program capable of activating and switching between a plurality of tasks and executing the program, and a clock for executing the program and providing the program under the multitasking operating system environment. A clock control device for a central processing unit of an information processing apparatus, comprising: a central processing unit whose operating speed is determined based on a frequency; a central processing unit required for each task activated under the multitasking operating system environment. The performance information of the central processing unit for each task is set, and one or more performance information setting circuits that set the performance information of the central processing unit, and one or more performance information set in the performance information setting circuit are used to start Of the central processing unit to operate with the minimum performance required for the task of A selection information generation circuit that generates selection information so as to determine the lock frequency, an oscillation circuit that generates a plurality of clock signals, and one of the plurality of clock signals is selected according to the selection information. A clock control device for a central processing unit, comprising a clock selection circuit for supplying the central processing unit. 2. The central processing unit, the one or more performance information setting circuits, the selection information generation circuit, and the clock selection circuit are integrated in one chip.
A clock controller for the central processing unit described. 3. A memory for storing a multitasking operating system and a program capable of activating and switching a plurality of tasks and executing the program, and a clock for executing the program and being provided with the program under the multitasking operating system environment. A clock control method for a central processing unit of an information processing apparatus, comprising: a central processing unit whose operating speed is determined based on a frequency; and a central processing unit required for each task activated under the multitasking operating system environment. Performance information setting circuit, one or more performance information setting circuits, a selection information generation circuit, an oscillation circuit that generates a plurality of clock signals, and a clock selection circuit. A circuit sets performance information of the central processing unit for each task, The synthesis circuit uses the one or more performance information set in the performance information setting circuit to determine the clock frequency of the central processing unit so as to operate at the minimum necessary performance required by the task being activated. And selecting one of a plurality of clock signals generated from the oscillator according to the selection information, and supplying the selected selection information to the central processing unit. Central processing unit clock control method. 4. The multi-task operating system manages performance information required by each task on a task-by-task basis, and when the task is activated, the performance information of the task activated to the performance information setting circuit is displayed. 4. The method according to claim 3, further comprising the step of setting, and further comprising the step of invalidating the performance information of the corresponding task set in the performance information setting circuit when ending the task. Control method for CPU central processing unit. 5. When the task is started, the performance information of the task is registered in a task management table, the performance information of all the running tasks is read, and the performance information of the all tasks is used. A step of calculating the minimum necessary performance information of the central processing unit, and a step of setting the performance information of the central processing unit in the selection information generating circuit; A step of deleting the performance information from the task management table, a step of reading the performance information of all the running tasks, a step of calculating the minimum required performance information of the central processing unit using the performance information of the all tasks, 5. The central processing unit clock according to claim 4, further comprising the step of setting performance information of the central processing unit in the selection information generating circuit. Click control method. 6. The central processing unit, according to the program, generates clock selection information of the central processing unit from one or more pieces of performance information obtained from the performance information setting circuit. The clock control device of the central processing unit according to claim 2. 7. The information processing apparatus can use either a battery or an AC power supply as a power supply means, and by providing an identification means of the power supply means, when the battery is used and when the AC power supply is used. The central processing unit generates clock selection information of the central processing unit from one or more pieces of performance information obtained from the performance information setting circuit according to the identification result. 7. The clock controller of the central processing unit according to claim 6.