JPH0865540A - Method for transmitting synchronizing signal - Google Patents

Abstract

PURPOSE: To save the length of a wire for supplying horizontal and vertical synchronizing pulses to a picture signal digital processing circuit. CONSTITUTION: A horizontal synchronizing pulse with width (a) and a vertical synchronizing pulse with width 2a are multiplexed and supplied to a digital processing circuit through an AND gate 33 and a DFF 34. Since both synchronizing pulses can be supplied only by one wire and separator circuits for respectively separating horizontal and vertical synchronizing pulses which are arranged on the digital processing circuit side can be respectively constituted of simple logic circuits, the design of the circuit can easily be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission method for transmitting a sync signal required for signal processing in a television device.

[0002]

2. Description of the Related Art Generally, digital signal processing of an image signal in a television apparatus is usually performed at a timing synchronized with horizontal and vertical synchronizing signals, and therefore, the digital processing of the image signal is performed. It is common practice to externally supply timing pulses representing horizontal and vertical timing to such processing circuits. An example of such a signal processing circuit is an image compression recording type digital VT.
An explanation will be given below with reference to the case of R (hereinafter referred to as digital VTR).

FIG. 10 shows the configuration of image signal processing of the recording system in such a digital VTR, and FIG. 11 shows the configuration of image signal processing of the reproducing system. First, the circuit of FIG. 10 will be described. The luminance signal and the color difference signal separated by the YC separation circuit 1 are supplied to the AD conversion circuits 3 and 4, and here, based on the horizontal synchronization signal HS from the synchronization separation circuit 2. A sampling clock SCK of the generated timing signal generation circuit 5 and a clock 1 / 4S having a cycle four times that of the sampling clock SCK.
AD converted by CK.

The AD conversion outputs DY, DR, DB are supplied to blocking and shuffling circuits 7 and 8, where 1
The screen data is divided into blocks each having 8 samples in the horizontal direction and 8 lines in the vertical direction, and further shuffled according to a predetermined pattern. These blocking and shuffling are executed based on the horizontal and vertical timing pulses HP and VP from the timing signal generating circuit 5, the clocks SCK and 1/4 SCK, and the identification signal FLID indicating the odd / even of the field. For reference, H
FIG. 12 shows an example of signal waveforms of P, VP, and FLID.

A blocking / shuffling circuit 7
13 shows an example of a specific circuit configuration of the above. In this figure, the AD conversion output DY is alternately input to the field memories 30 and 51 for each one field, and the write address at this time is SCK and FLI in the write control circuit 31.
It is generated according to the shuffling pattern based on D, HP, and VP. Reading from the field memory is always performed from the field memory in which the writing operation is not performed, and the read reference clock MCK, the field identification signal FIM corresponding to the FLID, and the horizontal and vertical timing signals HM and VM are used. Based on the read control circuit 32, a read control signal is generated.

In the circuit of FIG. 10, the above MCK,
Illustration of the FIM, HM, and VM is omitted. Further, the blocking / shuffling circuit 8 is provided with two sets of circuits similar to those of FIG. 13 for DR and DB. However, in this case, 4 instead of SCK and MCK
A double cycle clock is used. In FIG. 10, the shuffling output is converted into a non-interlaced signal in the buffering memory 9, and then supplied to the image compression encoding circuit 10 in a predetermined order to be data-compressed, and subjected to recording modulation, and then recorded. It is recorded on the tape via the amplifier 12.

In the reproducing system shown in FIG. 11, the reproduced data from the tape is supplied to the image compression / decoding circuit 16 via the reproduction amplifier 13, the equalization circuit 14 and the channel decoder 15, and is returned to the uncompressed data. Be done. Next, in the buffering memory 17, the deshuffling / deblocking circuits 21 and 22 after being converted into the interlaced format
To shuffle and block. These deshuffling / deblocking circuits
The circuit is similar to that shown in FIG. 13, and inverse transformations for shuffling and blocking are executed.

Data D obtained by this inverse transformation operation
The Y, DR, and DB are supplied to the YC synthesizing circuit after being restored to the original luminance signal and the color difference signal in the DA converting circuits 23 and 24, and further, the synthesizing circuit 27 adds the complex synchronizing signal to the composite video signal. It is formed. It should be noted that the deshuffling / deblocking circuit and the composite synchronizing signal generating circuit are M
Timing signals such as CK, FIM, HM, and VM are supplied to perform the above-described inverse conversion and generation of a composite synchronizing signal.

[0009]

As described above, in the signal processing of the recording system and the reproducing system of the digital VTR, HP (HM) and V which are horizontal and vertical timing signals are used.
The use of P (VM) is indispensable. However, it is necessary to route two signal lines dedicated to the horizontal and vertical timing signals between the signal processing blocks in this way to increase the number of terminals between blocks and increase the board size. This is not desirable because it causes an increase in power consumption, an increase in power consumption, and an increase in manufacturing cost. The present invention intends to solve such a problem.

[0010]

The present invention is a synchronization signal transmission method for transmitting a synchronization signal having horizontal synchronization pulse timing information and vertical synchronization pulse timing information, wherein the synchronization signal is a horizontal synchronization pulse A horizontal timing pulse having timing information and a vertical timing pulse composed of a single pulse representing the timing of a vertical synchronizing pulse are provided, and the pulse width of the horizontal timing pulse and the pulse width of the vertical timing pulse are Characterized by being different. In this case, the pulse width of the vertical timing pulse may be, for example, twice or more the pulse width of the horizontal timing pulse.

[0011]

[Operation] When horizontal and vertical timing signals are multiplexed, 1
It is transmitted by a signal line of a book. The receiving circuit separates the horizontal timing pulse and the vertical timing pulse based on the difference in pulse width.

[0012]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 shows transmission waveforms of horizontal and vertical timing signals in the first embodiment of the present invention, in which a pulse of width 2a represents a vertical timing position and a pulse of width a represents a horizontal timing position. In this way, by generating one signal SY in which the horizontal and vertical timing signals are multiplexed, it is possible to transmit both timing signals with one signal line.

Such a multiplexed signal SY is shown in FIG.
It can be easily generated by using an AND gate and a D flip-flop as shown in [1]. For reference, a timing chart for generating SY in this circuit is shown in [2] of FIG. An example of the circuit configuration for separating the horizontal and vertical timing signals from SY on the receiving side is shown in [1] of FIG. 3, and the timing chart for separating and deriving the horizontal and vertical timing signals from this circuit is also the same. It is shown in [2] of the figure.

FIG. 4 shows the transmission waveforms of the horizontal and vertical timing signals in the second embodiment. The pulse of width 3a represents the vertical timing position and the pulse of width a represents the horizontal timing position. Such a multiplexed signal SY is, for example,
It can be generated using the circuit configuration shown in [1] of FIG. [2] in the figure shows S in this circuit.
7 is a chart showing the timing of Y generation. On the receiving side, a circuit configuration example for separating the horizontal and vertical timing signals from such SY is shown in [1] of FIG.
In addition, a timing chart in which horizontal and vertical timing signals are separated and derived in this circuit is shown in [2] of FIG.

FIG. 7 shows the transmission waveforms of the horizontal and vertical timing signals in the third embodiment. The pulse of width a represents the vertical timing position, and the pulse of width 2a represents the horizontal timing position. Such a multiplexed signal SY is, for example,
It can be generated using the circuit configuration shown in [1] of FIG. [2] in the figure shows S in this circuit.
7 is a chart showing the timing of Y generation. On the receiving side, a circuit configuration example for separating the horizontal and vertical timing signals from such SY is shown in [1] of FIG.
In addition, a timing chart in which horizontal and vertical timing signals are separated and derived in this circuit is shown in [2] of FIG.

Although the three embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and as will be apparent from the description of the claims, the vertical embodiment will be described. The timing signal is multiplexed with the horizontal timing signal as a pulse having a pulse width different from that of the horizontal timing signal and transmitted, and various configurations other than the above-described embodiment can be adopted. Further, although the digital VTR has been described as an example of the television device to which the present invention is applied, it is needless to say that the present invention can be applied to various other television devices.

[0017]

The number of signal lines for transmitting horizontal and vertical timing signals is only one, and wiring is easy. A circuit for multiplexing the horizontal and vertical timing signals and a circuit for separating the timing signals can be obtained with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a waveform of a multiplexed signal according to a first embodiment of the present invention.

FIG. 2 is a multiple signal generation circuit and its timing chart in the embodiment.

FIG. 3 is a horizontal and vertical timing signal separation circuit and its timing chart in the embodiment.

FIG. 4 is a waveform of a multiplexed signal according to the second embodiment of the present invention.

FIG. 5 is a multiple signal generation circuit and its timing chart in the embodiment.

FIG. 6 is a horizontal and vertical timing signal separation circuit and its timing chart in the embodiment.

FIG. 7 is a waveform of a multiplexed signal according to the third embodiment of the present invention.

FIG. 8 is a multiple signal generation circuit and its timing chart in the embodiment.

FIG. 9 is a horizontal and vertical timing signal separation circuit and its timing chart in the embodiment.

FIG. 10 is a circuit configuration of a recording system of an image compression recording type digital VTR.

FIG. 11 is a circuit configuration of a reproduction system of the digital VTR.

FIG. 12 is a diagram showing horizontal and vertical timing signals and field identification signals.

FIG. 13 is a configuration of a blocking / shuffling circuit.

[Explanation of symbols]

 5 ... Timing signal generation circuit 7, 8 ... Blocking / shuffling circuit 20 ... Reference timing signal generation circuit 21, 22 ... Deshuffling / deblocking circuit 26 ... Composite synchronization signal generation circuit

Claims (2)

[Claims] 1. A synchronization signal transmission method for transmitting a synchronization signal having horizontal synchronization pulse timing information and vertical synchronization pulse timing information, wherein the synchronization signal includes a horizontal timing pulse having horizontal synchronization pulse timing information and a vertical synchronization pulse having vertical synchronization pulse timing information. A vertical timing pulse composed of a single pulse indicating the timing of the synchronizing pulse, and a pulse width of the horizontal timing pulse and a pulse width of the vertical timing pulse are different from each other. Transmission method. 2. The synchronizing signal transmission method according to claim 1, wherein the vertical timing pulse has a pulse width that is at least twice the pulse width of the horizontal timing pulse.