JPH0865289A - Synchronizing system for binary serial data communication - Google Patents

Abstract

PURPOSE: To provide the synchronizing system for binary serial data communication with which transmission P and Q channels can be secured and proper decoding is enabled on reception side equipment even when step-out of frame synchronization occurs in the middle of data transmission because of radio wave hit or the like. CONSTITUTION: A system is composed of a serial/parallel converter 41, viterbi decoder 51 and frame synchronizing detection circuit 61 for processing binary serial data in order to transmit input data in the state of inserting a frame synchronizing pattern to respective frames as the binary serial data, in which the bit of the P channel and the bit of the Q channel alternately appear, by encoding those input data with the convolusion encoder of a 1/2 encoding ratio on the transmission side. In order to provide a proper data sequence by fixing the P and Q channels and detecting the frame synchronizing pattern on the reception side, a system is composed of a serial/parallel converter 42, Viterbi decoder 52 and frame synchronizing detecting circuit 62 for processing one-bit delayed data of binary serial data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization system in which an error correction system used in data communication is applied to binary serial data communication.

[0002]

2. Description of the Related Art Conventionally, in binary serial data communication, when an error correction method with a coding rate of 1/2 by a convolutional encoder having a coding rate of 1/2 is applied, before data transmission is started. The preamble signal is transmitted from the transmitting side device to the receiving side device, and two kinds of data strings (P-channel and Q-channel data strings) are generated due to the coding rate of 1/2.
After confirming, the data communication was performed from the transmission side device to the reception side device.

[0003]

However, in the method of determining the P-channel and Q-channel data strings only with the above-mentioned preamble signal, when the frame synchronization loss occurs during the data transmission due to the electric wave interruption or the like, P Since the channel and the Q channel become uncertain and correct decoding cannot be performed, an error occurs in the subsequent data.

An object of the present invention is to provide binary serial data in which the transmitting P channel and the Q channel can be determined and correct decoding can be performed in the receiving side device even if the frame synchronization is lost during the data transmission due to the electric wave interruption or the like. It is to provide a synchronization method in communication.

[0005]

According to the present invention, a transmission side device and a reception side device are provided, and the transmission side device receives input data having continuous frames and receives each of the frames of the input data. A frame sync insertion circuit for outputting output data with a frame sync pattern inserted therein, and a coding rate of 1/2. The output data is convolutionally coded,
A convolutional encoder for transmitting binary serial data in which bits of the P channel and bits of the Q channel appear alternately, and the receiving side device receives the binary serial data, and the binary serial data is received. A 1-bit delay circuit that outputs 1-bit delayed serial data obtained by delaying the data by 1-bit, and the binary serial data are received, and the binary serial data is alternated bit by bit into first virtual P channel data and First
Connected to the first serial-parallel conversion circuit and the 1-bit delay circuit, which are distributed as the virtual Q-channel data of the second virtual P-channel data and the second virtual P-channel data and the second virtual P-channel data. The first serial-parallel conversion circuit and the second serial-parallel conversion circuit that distributes as virtual Q-channel data are connected to the first virtual P-channel data and the first virtual Q-channel data. A first Viterbi decoder for performing Viterbi decoding on the decoded data and a second serial-parallel conversion circuit are connected, and the second virtual P-channel data and the second virtual Q-channel data are converted into second decoded data. Is connected to the second Viterbi decoder for performing Viterbi decoding and the first Viterbi decoder. Detecting the frame synchronization pattern,
A first frame synchronization detection circuit that outputs a first detection signal and outputs the first decoded data as a first reception output signal when the frame synchronization pattern is detected, and the second Viterbi decoding. Connected to a receiver, detects the frame synchronization pattern from the second decoded data, outputs a second detection signal when the frame synchronization pattern is detected, and secondly receives the second decoded data. A second frame synchronization detection circuit that outputs an output signal, and is connected to the first and second frame synchronization detection circuits,
A selector that selectively outputs one of the first and second received output signals as receiving-side device output data, and the first and second frame synchronization detection circuits are connected, and the first detection is performed. When receiving the signal, the signal selector is caused to output the first reception output signal as the reception side device output data, and when the second detection signal is received, the signal selector is caused to output the second signal. And a control circuit for outputting the reception output signal of (1) as the output data of the receiving side device, a synchronization system in binary serial data communication is obtained.

[0006]

According to the present invention, the transmitting side device sends a frame synchronization pattern for each frame, and the receiving side device catches the frame synchronization so that the P channel and the Q channel are finally determined. . That is, in the present invention, the synchronization pattern transmitted by the transmission side device is divided into two systems, that is, the data sequence delayed by one bit at the reception side device and the one not, and each is decoded by the Viterbi decoder. Immediately after that, if frame synchronization is established and either one is synchronized, the data string of the synchronized system is determined to be a correct data string and data communication is performed.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a synchronous transmission side device in binary serial data communication according to an embodiment of the present invention includes a frame synchronization insertion circuit 1 and a convolutional encoder 2. The frame synchronization insertion circuit 1 receives input data having continuous frames and an input clock synchronized with the input data, and outputs output data in a state in which a frame synchronization pattern having a large autocorrelation is inserted into each frame of the input data and the output data. Output an output clock synchronized with data. The convolutional encoder 2 has a coding rate of 1/2, and performs convolutional coding on the output data of the frame synchronization insertion circuit 1, and a binary value in which P channel bits and Q channel bits appear alternately as described later. The serial data is transmitted as the transmission data and the transmission clock synchronized with the transmission data is transmitted.

Referring to FIG. 2, the receiving device of the synchronous system in the binary serial data communication according to the above embodiment of the present invention includes a 1-bit delay circuit 3 and first and second serial circuits.
Parallel conversion circuits 41 and 42, first and second Viterbi decoders 51 and 52, first and second frame synchronization detection circuits 61 and 62, and determination circuit (that is, control circuit)
7 and a signal selector 8. 1-bit delay circuit 3
Receives binary serial data (that is, received data) and outputs 1-bit delayed serial data obtained by delaying the binary serial data by 1 bit.

First serial-parallel conversion circuit 41
Receives the binary serial data (that is, the received data) and the reception clock that is synchronized with the binary serial data (that is, the received data), and as described later, the binary serial data is alternated bit by bit. The first virtual P channel (Pch) data and the first virtual Q channel (Qch) data are distributed, and a clock synchronized with the first virtual P channel data and a clock synchronized with the first virtual Q channel data are output. To do. The second serial-parallel conversion circuit 42 is connected to the 1-bit delay circuit 3 and receives the 1-bit delayed serial data and the aforementioned received clock synchronized with the aforementioned received data (that is, 1-bit delayed serial data), As will be described later, the 1-bit delayed serial data is alternately distributed bit by bit as the second virtual P channel (Pch) data and the second virtual Q channel (Qch) data, and at the same time, as the second virtual P channel data. The synchronized clock and the clock synchronized with the second virtual Q channel data are output.

The first Viterbi decoder 51 is connected to the first serial-parallel conversion circuit 41, receives the first virtual P-channel data and the first virtual Q-channel data, and a clock synchronized with them, The first virtual P-channel data and the first virtual Q-channel data are Viterbi-decoded, and the first decoded data and a clock synchronized with it are output. Similarly, the second Viterbi decoder 52
Of the second virtual P-channel data and the second virtual Q-channel data and a clock synchronized with them, and receives the second virtual P-channel data and the second virtual Q-channel. The data is Viterbi-decoded, and the second decoded data and the clock synchronized therewith are output.

The first frame sync detection circuit 61 has a first
Connected to the Viterbi decoder 51, receives the first decoded data and the clock synchronized with the first decoded data, detects the frame synchronization pattern from the first decoded data, and when the frame synchronization pattern is detected, outputs the first detection signal 611. A clock 613 that outputs the first decoded data as a first received output signal 612 and that is synchronized with the first decoded data.
Is output. Similarly, the second frame synchronization detection circuit 62
Is connected to the second Viterbi decoder 52, receives the second decoded data and the clock synchronized therewith, detects the frame synchronization pattern from the second decoded data, and when the frame synchronization pattern is detected, the second The detection signal 621 is output, the second decoded data is output as the second reception output signal 622, and the clock 623 synchronized with the second decoded data is output.

The signal selector 8 is connected to the first and second frame synchronization detection circuits 61 and 62 and selectively uses one of the first and second reception output signals 612 and 622 as the reception side device output data. Output. At the same time, the signal selector 8
When the first reception output signal 612 is selectively output, the clock 613 is selectively output as the device output clock on the reception side, and when the second reception output signal 622 is selectively output, the clock is output. 623 is selectively output as a receiving side device output clock.

The determination circuit (that is, the control circuit) 7 is connected to the first and second frame synchronization detection circuits 61 and 62, and when receiving the first detection signal 611, the signal selector 8
When the second detection signal 621 is received, the first reception output signal 612 and the clock 613 are selectively output as the reception side device output data and the reception side device output clock.
A control signal is applied to the signal selector 8 so that the signal selector 8 selectively outputs the second reception output signal 622 and the clock 623 as the reception-side device output data and the reception-side device output clock. In other words, the determination circuit (that is, the control circuit) 7 determines which of the first and second frame synchronization detection circuits 61 and 62 is the frame synchronization detection circuit that has detected the synchronization pattern, and the signal selector 8 Are controlled as described above.

Next, the operation of the transmission side apparatus of FIG. 1 and the reception side apparatus of FIG. 2 will be described. First, in the transmission side apparatus of FIG. 1, the frame synchronization insertion circuit 1 inserts a synchronization pattern for each frame. After that, the convolutional encoder 2 encodes the output data of the frame synchronization insertion circuit 1 at a coding rate of 1/2 as shown in FIG. 3, and outputs an in-phase component, that is, a P channel (Pch) component and a quadrature component. , That is, Q channel (Q
ch) component, and binary serial data in which the separated G channel bit G1 and Q channel bit G2 appear alternately is transmitted as transmission data. In FIG. 3, reference numeral 21 is an adder.

In the receiving side apparatus of FIG. 2, the received data received is first serial-parallel conversion circuit 41 as it is.
Input to the second serial-parallel conversion circuit 42 after being delayed by 1 bit by the 1-bit delay circuit 3.
It is divided into two systems that are input to. The input data of the first and second serial-parallel conversion circuits 41 and 42 are shown in FIG. Since bit G1 and bit G2 are alternately arranged in the transmission data as shown in FIG. 3, even if a bit in the data string is taken out, the bit is G1 and G2.
I don't know which one. When the received data is assumed to be a data string of bit a and bit b as shown in FIG. 4, it cannot be determined which of a and b corresponds to G1 and G2. Therefore, the 1-bit delay circuit 3 creates data in which the received data is delayed by 1 bit, and the received data and the 1-bit delayed data create two systems of a data string in which G1 is the head and a data string in which G2 is the head. .

These two series of data are respectively converted by the first and second serial-parallel conversion circuits 41 and 42 into a data string of a and a data string of b (shown in the upper column of FIG. 5), as shown in FIG. ) And a data string of b and a data string of a (shown in the lower column of FIG. 5) are converted in parallel. Then, the data sequence of a and the data sequence of b shown in the upper column of FIG. 5 are input to the first Viterbi decoder 51 as virtual P channel data and virtual Q channel data, respectively, and the first Viterbi decoder 51 is input. To decrypt. In addition, the data string of b and the data string of a shown in the lower column of FIG. 5 are input to the second Viterbi decoder 52 as virtual P channel data and virtual Q channel data, respectively, and the second Viterbi decoder 52 is input. To decrypt. In this way, the original data can be surely decoded by either of the first and second Viterbi decoders 51 and 52. This is detected by one of the first and second frame synchronization detection circuits 61 and 62 for the synchronization pattern inserted in the transmission side device, and the determination circuit 7 determines which of the first and second frame synchronization detection circuits 61 and 62 is used. It is possible to determine whether the synchronization pattern has been detected, control the signal selector 8 to take out the original data, and perform data communication.

[0018]

As described above, according to the present invention, even if the frame synchronism is lost in the middle of data transmission due to the electric wave interruption or the like, the transmitting side device can determine the transmitting P channel and the Q channel, which is correct. Can be decrypted.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitting side device of a synchronous system in binary serial data communication according to an embodiment of the present invention.

FIG. 2 is a block diagram of a receiving device of a synchronous system in binary serial data communication according to the above embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of the transmission side device of FIG.

FIG. 4 is a diagram for explaining the operation of the receiving-side apparatus in FIG.

FIG. 5 is a diagram for explaining another operation of the receiving side apparatus of FIG.

[Explanation of symbols]

 1 Frame Synchronization Insertion Circuit 2 Convolutional Encoder 3 1-bit Delay Circuit 41 First Serial-Parallel Conversion Circuit 42 Second Serial-Parallel Conversion Circuit 51 First Viterbi Decoder 52 Second Viterbi Decoder 61 First Frame synchronization detection circuit 62 Second frame synchronization detection circuit 7 Judgment circuit (that is, control circuit) 8 Signal selector 21 Adder

Claims (1)

[Claims] 1. A transmission side device and a reception side device, wherein the transmission side device receives input data having continuous frames, and outputs a state in which a frame synchronization pattern is inserted into each frame of the input data. A frame sync insertion circuit for outputting data, and a convolution having a coding rate of 1/2, convolutionally coding the output data, and transmitting binary serial data in which bits of P channel and bits of Q channel appear alternately. An encoder, the receiving-side device receives the binary serial data, and outputs the binary serial data as 1
Output 1-bit delayed serial data with bit delay 1
A bit delay circuit and the binary serial data are received, and the binary serial data is set to 1
A first serial-parallel conversion circuit that alternately distributes each bit as first virtual P channel data and first virtual Q channel data, and is connected to the 1-bit delay circuit, and the 1-bit delayed serial data is 1 bit. A second serial-parallel conversion circuit that alternately distributes the second virtual P-channel data and the second virtual Q-channel data every time, and the first virtual P-channel conversion circuit connected to the first serial-parallel conversion circuit. Channel data and the first virtual Q
A first Viterbi decoder that Viterbi-decodes channel data into first decoded data, and the second virtual-P channel data and the second virtual Q that are connected to the second serial-parallel conversion circuit.
A second Viterbi decoder that Viterbi-decodes channel data into second decoded data, and is connected to the first Viterbi decoder, detects the frame synchronization pattern from the first decoded data, and detects the frame synchronization pattern. Is connected to the second Viterbi decoder and a first frame synchronization detection circuit that outputs a first detection signal and outputs the first decoded data as a first reception output signal. , Detecting the frame synchronization pattern from the second decoded data, outputting a second detection signal when detecting the frame synchronization pattern, and outputting the second decoded data as a second reception output signal And a second frame synchronization detection circuit, which is connected to the first and second frame synchronization detection circuits and selectively receives one of the first and second reception output signals. A selector for outputting as device output data, and the first and second frame synchronization detection circuits, and when receiving the first detection signal, the signal selector selects the first reception output signal. A control circuit for causing the signal selector to output the second reception output signal as the reception-side device output data when receiving the second detection signal as the reception-side device output data. A synchronization method in binary serial data communication characterized by having.