JPH0864846A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0864846A JPH0864846A JP6198360A JP19836094A JPH0864846A JP H0864846 A JPH0864846 A JP H0864846A JP 6198360 A JP6198360 A JP 6198360A JP 19836094 A JP19836094 A JP 19836094A JP H0864846 A JPH0864846 A JP H0864846A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- metal film
- optical
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、光通信等に用いる光送
信機あるいは光受信機を形成する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device forming an optical transmitter or an optical receiver used for optical communication or the like.
【０００２】[0002]
【従来の技術】従来の光送信機あるいは光受信機は電気
的、磁気的雑音から回避するためにそれらを金属ケース
に封入することによって確保していた。一方、電子機器
の大規模化、高速化と共に小型化が求められている。特
に、光受信機は微弱な光信号を電気信号に変換した後、
増幅する構成をとるためその要求は厳しく、種々のシー
ルド対策が開発されている。2. Description of the Related Art Conventional optical transmitters or optical receivers have been secured by enclosing them in a metal case in order to avoid electrical and magnetic noise. On the other hand, electronic devices are required to be large-scale, high-speed and small in size. In particular, optical receivers convert weak optical signals into electrical signals,
The requirements are strict because of the amplification configuration, and various shield measures have been developed.
【０００３】例えば、図４はシールドパッケージされた
従来例の構成を示す斜視図であり、図示していない光フ
ァイバからの信号は入力端子１４からフォトダイオード
１６に入射され、これを増幅するための集積回路（Ｉ
Ｃ）１７、コンデンサ１８からなる光受光回路がケース
基台１１の中に搭載されている。このケース基台１１は
シール用樹脂膜１３を介して金属製のキャップ１２に固
着され、光受光回路はシールドパッケージされている
（特願平５−３０２２号）。For example, FIG. 4 is a perspective view showing the structure of a shield packaged prior art example, in which a signal from an optical fiber (not shown) is made incident on a photodiode 16 from an input terminal 14 and is amplified. Integrated circuit (I
C) A light receiving circuit including a capacitor 17 and a capacitor 18 is mounted in the case base 11. The case base 11 is fixed to a metal cap 12 via a sealing resin film 13, and the light receiving circuit is shielded (Japanese Patent Application No. 5-3022).
【０００４】[0004]
【発明が解決しようとする課題】このような方式を用い
た場合は、一枚の基板上に受光素子と複数の増幅回路を
形成する場合、あるいは受光素子と増幅回路及び発光素
子とその駆動回路を混載する場合には、個々の回路間を
シールドするための間隔が必要となり、さらに全体をシ
ールドパッケージを施すために装置の小型化には限界が
あった。そこで本発明は、かかるシールドパッケージを
施さなくても問題点を解決した半導体装置を提供するこ
とを目的とする。When such a method is used, a light receiving element and a plurality of amplifying circuits are formed on one substrate, or a light receiving element, an amplifying circuit, a light emitting element and a driving circuit thereof. In the case of mixed mounting, it is necessary to provide an interval for shielding between individual circuits, and further there is a limit to downsizing the device because the entire package is provided. Therefore, it is an object of the present invention to provide a semiconductor device which solves the problem without providing such a shield package.
【０００５】[0005]
【課題を解決するための手段】本発明に係わる半導体装
置は、基板の表面に形成された導体パターンと光デバイ
ス又は表面に電子回路が形成された半導体ＩＣチップと
がバンプを介して電気的に接続され、前記光デバイスの
光透過窓部を除く面、前記半導体ＩＣチップの裏面及び
前記基板の裏面には金属膜が施され、該金属膜は接地さ
れていることを特徴とする。In a semiconductor device according to the present invention, a conductor pattern formed on the surface of a substrate and an optical device or a semiconductor IC chip having an electronic circuit formed on the surface are electrically connected via bumps. A metal film is formed on the surface of the optical device other than the light transmitting window portion, the back surface of the semiconductor IC chip and the back surface of the substrate that are connected, and the metal film is grounded.
【０００６】前記光デバイスは発光ダイオード、レーザ
ダイオードあるいは受光ダイオードであること、また、
前記電子回路は発光ダイオード又はレーザダイオードの
駆動回路あるいは受光ダイオードの増幅回路であること
特徴とする。The optical device is a light emitting diode, a laser diode or a light receiving diode, and
The electronic circuit is a drive circuit for a light emitting diode or a laser diode or an amplifier circuit for a light receiving diode.
【０００７】[0007]
【作用】上記の構成によれば、本発明に係わる半導体装
置の電子回路（増幅回路、駆動回路、導体パターン）は
接地された金属膜と基板裏面に形成された接地用金属膜
との間に挟まれた構成をとっているので、周囲からのノ
イズの影響が受け難くなる。発光装置の場合は、周辺回
路への影響が軽減される。また、光透過窓部を除く光デ
バイス面についても金属膜を施し接地しているので、同
様のシールド効果が得られる。According to the above construction, the electronic circuit (amplifier circuit, drive circuit, conductor pattern) of the semiconductor device according to the present invention is provided between the grounded metal film and the grounding metal film formed on the back surface of the substrate. Since it is sandwiched, it is less susceptible to noise from the surroundings. In the case of a light emitting device, the influence on peripheral circuits is reduced. Further, since a metal film is also applied to the optical device surface excluding the light transmitting window portion to be grounded, the same shielding effect can be obtained.
【０００８】[0008]
【実施例】以下、添付図面を参照して本発明の実施例を
説明する。図１は本発明の半導体装置に係わる一実施例
の構成を示す断面図である。図において、信号光を受光
して電流に変換する受光素子１−１、この電流を増幅す
る回路を有する半導体ＩＣチップ２−１及び信号光を発
光する発光ダイオード又はレーザダイオード等の発光素
子１−２、この発光素子１−２を駆動するための回路を
有する半導体ＩＣチップ２−２とは表面に導電パターン
５を形成した基板４とバンプ９・・・を介して電気的に
接続された装置である。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view showing the structure of an embodiment of the semiconductor device of the present invention. In the figure, a light receiving element 1-1 that receives signal light and converts it into a current, a semiconductor IC chip 2-1 having a circuit that amplifies this current, and a light emitting element 1 such as a light emitting diode or a laser diode that emits signal light 1- 2. A device in which a semiconductor IC chip 2-2 having a circuit for driving the light emitting element 1-2 is electrically connected to a substrate 4 having a conductive pattern 5 formed on its surface via bumps 9 ... Is.
【０００９】半導体ＩＣチップ２−１、半導体ＩＣチッ
プ２−２の表面には夫々増幅回路３−１、駆動回路３−
２が形成され、それらの裏面にはＡｕ等からなる薄膜６
−１が蒸着されている。一方、アルミナを主成分とする
基板４の表面にはＡｇＰｄ等の導体からなるパターン５
が形成され、パターン５と前記電子回路３−１、３−２
あるいはこれらの回路と光素子１−１、１−２とはＳｎ
Ｐｄ等からなる球状のバンプ９を介して接続される。こ
れにより従来使われていたＡｕワイヤ等による接続に比
べてインダクタンスが小さくなり、高周波信号の損失が
小さくなると共に、空中への電磁波の放出あるいは外界
からの電磁界の影響を受け難くなる。基板４の裏面には
全面に接地用金属膜６−３が形成されている。接地はＡ
ｕ等の金属リボン８、スルーホール７の経路を通して行
なわれる。接地をより確実にするために、Ａｕリボンは
インダクタンスを下げられるように複数本接続してい
る。また、スルーホールも基板強度に影響しない程度に
多数設けている。On the surfaces of the semiconductor IC chip 2-1 and the semiconductor IC chip 2-2, an amplifier circuit 3-1 and a drive circuit 3- are respectively provided.
2 are formed, and a thin film 6 made of Au or the like is formed on their back surfaces.
-1 is vapor-deposited. On the other hand, a pattern 5 made of a conductor such as AgPd is formed on the surface of the substrate 4 containing alumina as a main component.
Are formed, and the pattern 5 and the electronic circuits 3-1 and 3-2 are formed.
Alternatively, these circuits and the optical elements 1-1 and 1-2 are Sn.
Connection is made via a spherical bump 9 made of Pd or the like. As a result, the inductance is reduced, the loss of high-frequency signals is reduced, and the electromagnetic wave is not emitted into the air or is not easily affected by the electromagnetic field from the outside as compared with the connection using an Au wire or the like which has been conventionally used. A grounding metal film 6-3 is formed on the entire back surface of the substrate 4. Grounding is A
It is carried out through the path of the metal ribbon 8 such as u and the through hole 7. In order to secure grounding, a plurality of Au ribbons are connected so that the inductance can be reduced. Also, a large number of through holes are provided so as not to affect the strength of the substrate.
【００１０】導体パターン５は前記電子回路３−１、３
−２に電源を供給し、あるいは信号電流を取出し、又は
それらの部材の間を接続するためにパターンが形成され
る。従って、増幅回路３−１、駆動回路３−２及び導体
パターン５は接地された金属膜６−１と基板裏面に形成
された接地用金属膜６−３との間に挟まれた構成をとっ
ているので、周囲からのノイズの影響は受け難くなり、
あるいは周辺回路への影響が軽減される。光素子１−
１、１−２の場合は光が透過する窓部１−１Ａ、１−２
Ｂを除く面には金属膜６−２を施して接地されているの
で、前記と同様の遮蔽効果を持っている。The conductor pattern 5 is composed of the electronic circuits 3-1 and 3 described above.
-2 to provide power, extract signal current, or form a pattern to connect between these members. Therefore, the amplifier circuit 3-1, the drive circuit 3-2 and the conductor pattern 5 are sandwiched between the grounded metal film 6-1 and the grounding metal film 6-3 formed on the back surface of the substrate. Therefore, it is less likely to be affected by noise from the surroundings,
Alternatively, the influence on the peripheral circuits is reduced. Optical element 1-
In the case of 1 and 1-2, window portions 1-1A and 1-2 through which light is transmitted
Since the surface except B is provided with the metal film 6-2 and is grounded, it has the same shielding effect as described above.
【００１１】図２は、図１に示した実施例に適用される
発光ダイオード１−２と駆動回路３−２のブロック図で
あり、図３は受光ダイオード１−１と増幅器３−１のブ
ロック図である。接地端子Ｇｎｄは図１における金属膜
６と接続され、データ入出力端子ＤＡＴＡ等、信号検出
出力端子ＳＩＧＮＡＬ ＤＥＴＥＣＴ等及び電源供給端
子Ｖｃｃは導体パターン５と接続される。FIG. 2 is a block diagram of a light emitting diode 1-2 and a drive circuit 3-2 applied to the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of a light receiving diode 1-1 and an amplifier 3-1. It is a figure. The ground terminal Gnd is connected to the metal film 6 in FIG. 1, and the data input / output terminal DATA and the like, the signal detection output terminal SIGNAL DETECT and the like and the power supply terminal Vcc are connected to the conductor pattern 5.
【発明の効果】以上説明したように、本発明に係わる半
導体装置の電子回路は、接地された金属膜と基板裏面に
形成された接地用金属膜との間に挟まれた構成をとって
いるので、周囲からのノイズの影響が受け難くなる。発
光装置の場合は、周辺回路への影響が軽減される。ま
た、光透過窓部を除く光デバイス面についても金属膜を
施し接地しているので、同様のシールド効果が得られ
る。As described above, the electronic circuit of the semiconductor device according to the present invention has a structure in which it is sandwiched between the grounded metal film and the grounding metal film formed on the back surface of the substrate. Therefore, it is less likely to be affected by noise from the surroundings. In the case of a light emitting device, the influence on peripheral circuits is reduced. Further, since a metal film is also applied to the optical device surface excluding the light transmitting window portion to be grounded, the same shielding effect can be obtained.
【図１】本発明の半導体装置に係わる一実施例の構成を
示す断面図である。FIG. 1 is a cross-sectional view showing the configuration of an example of a semiconductor device according to the present invention.
【図２】本実施例に適用される発光ダイオードと駆動回
路のブロック図である。FIG. 2 is a block diagram of a light emitting diode and a drive circuit applied to this embodiment.
【図３】本実施例に適用される受光ダイオードと増幅器
のブロック図である。FIG. 3 is a block diagram of a light receiving diode and an amplifier applied to this embodiment.
【図４】シールドパッケージされた従来例の構成を示す
斜視図である。FIG. 4 is a perspective view showing a configuration of a shield packaged conventional example.
１：光デバイス １−１：受光素子 １−２：発光素子 ２：半導体ＩＣチップ ３：電子回路 ３−１：増幅回路 ３−２：駆動回路 ４：基板 ５：導体パターン ６：金属膜 ７：スルーホール ８：金属リボン ９：バンプ １０：ピン １１：ケース基台 １２：キャップ １３：樹脂膜 １４：入力端子 １６：ＰＤ １７：ＩＣ １８：コンデンサ １９：ガラス板 1: Optical device 1-1: Light receiving element 1-2: Light emitting element 2: Semiconductor IC chip 3: Electronic circuit 3-1: Amplifying circuit 3-2: Driving circuit 4: Substrate 5: Conductor pattern 6: Metal film 7: Through hole 8: Metal ribbon 9: Bump 10: Pin 11: Case base 12: Cap 13: Resin film 14: Input terminal 16: PD 17: IC 18: Capacitor 19: Glass plate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｓ 3/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical indication H01S 3/18
Claims (3)
光デバイス又は表面に電子回路が形成された半導体ＩＣ
チップとがバンプを介して電気的に接続され、前記光デ
バイスの光透過窓部を除く面、前記半導体ＩＣチップの
裏面及び前記基板の裏面には金属膜が施され、該金属膜
は接地されていることを特徴とする半導体装置。1. A semiconductor IC having a conductor pattern formed on a surface of a substrate and an optical device or an electronic circuit formed on the surface.
The chip is electrically connected via a bump, and a metal film is applied to the surface of the optical device excluding the light transmitting window, the back surface of the semiconductor IC chip and the back surface of the substrate, and the metal film is grounded. A semiconductor device characterized in that.
イオードあるいは受光ダイオードであることを特徴とす
る請求項１の半導体装置。2. The semiconductor device according to claim 1, wherein the optical device is a light emitting diode, a laser diode or a light receiving diode.
イオードの駆動回路あるいは受光ダイオードの増幅回路
であることを特徴とする請求項１の半導体装置。3. The semiconductor device according to claim 1, wherein the electronic circuit is a drive circuit for a light emitting diode or a laser diode or an amplifier circuit for a light receiving diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6198360A JPH0864846A (en) | 1994-08-23 | 1994-08-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6198360A JPH0864846A (en) | 1994-08-23 | 1994-08-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864846A true JPH0864846A (en) | 1996-03-08 |
Family
ID=16389819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6198360A Pending JPH0864846A (en) | 1994-08-23 | 1994-08-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864846A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998034285A1 (en) * | 1997-01-31 | 1998-08-06 | Matsushita Electronics Corporation | Light emitting element, semiconductor light emitting device, and method for manufacturing them |
| JP2002544673A (en) * | 1999-05-12 | 2002-12-24 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | LED-device |
| JP2006041234A (en) * | 2004-07-28 | 2006-02-09 | Mitsubishi Electric Corp | Optical transmitting module and optical receiving module |
| JP2014165224A (en) * | 2013-02-21 | 2014-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Optical semiconductor device and optical semiconductor device manufacturing method |
-
1994
- 1994-08-23 JP JP6198360A patent/JPH0864846A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998034285A1 (en) * | 1997-01-31 | 1998-08-06 | Matsushita Electronics Corporation | Light emitting element, semiconductor light emitting device, and method for manufacturing them |
| US6333522B1 (en) | 1997-01-31 | 2001-12-25 | Matsushita Electric Industrial Co., Ltd. | Light-emitting element, semiconductor light-emitting device, and manufacturing methods therefor |
| US6597019B2 (en) | 1997-01-31 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd | Semiconductor light-emitting device comprising an electrostatic protection element |
| US6642072B2 (en) | 1997-01-31 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Light-emitting element, semiconductor light-emitting device, and manufacturing methods therefor |
| JP2002544673A (en) * | 1999-05-12 | 2002-12-24 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | LED-device |
| JP2006041234A (en) * | 2004-07-28 | 2006-02-09 | Mitsubishi Electric Corp | Optical transmitting module and optical receiving module |
| JP2014165224A (en) * | 2013-02-21 | 2014-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Optical semiconductor device and optical semiconductor device manufacturing method |
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