JPH0851162A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To inhibit punch-through between a source region and a drain region while realizing the high-speed operation of a short-channel MOSFET in the short-channel MOSFET. CONSTITUTION:In an N channel type MOSFET, an N-type junction capacitance reducing region 13 is formed in the lower section of an N<+> type semiconductor region 15 constituting parts of a source region and a drain region in the same concentration as an N pocket region 9 at a place in the same depth as the N pocket region 9 by impurities having a conductivity type reverse to the N pocket region 9. In a P channel type MOSFET, a P-type junction capacitance reducing region 14 is formed similarly to the lower section of a P<+> type semiconductor region 16 configuring parts of a source region and a drain region in the same concentration as a P pocket region 11 at a place in the same depth as the P pocket region 11 by impurities having a conductivity type reverse to the P pocket region 11, thus reducing junction capacitance between the source region and the pocket region or between the drain region and the pocket region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technology, and more particularly to a complementary MOSFET.
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having (CMOSFET).

[0002]

2. Description of the Related Art As the operating speed of a semiconductor integrated circuit device increases and the power consumption per chip increases remarkably as the integration density increases, a large-scale circuit can be mounted on one chip by using a conventional NMOS device or bipolar device. It's getting harder to configure. For this reason, not only the power consumption is small, but also the noise margin can be made large, and the circuit design is easy. Therefore, the demand for CMOS devices in VLSI is rapidly increasing.

CMOS devices are n-channel MOS
The FET and the p-channel MOSFET are arranged in series.

After forming channel regions by implanting channel ions into the p-type well and the n-type well formed on the main surface of the semiconductor substrate, a gate electrode is formed from a polycrystalline silicon film in which phosphorus is diffused. Next, in order to form low-concentration source and drain regions, ions are implanted using the gate electrode as a mask, and a low-concentration n-type semiconductor region (n ⁻ -type semiconductor region) made of n-type impurities is formed in the p-type well. , A low-concentration p-type semiconductor region (p ⁻ type semiconductor region) made of p-type impurities is formed in the n-type well.

Further, after forming a side wall spacer of a silicon oxide film on the side wall of the gate electrode, ions are implanted using the gate electrode and the side wall spacer as a mask in order to form a high concentration source region and drain region. A high-concentration n-type semiconductor region (n ⁺ -type semiconductor region) made of an n-type impurity in the p-type well and a high-concentration p-type semiconductor region (p ⁺ -type semiconductor region) made of a p-type impurity in the n-type well
To form LDD (Lightly Doped Drain)
Structure n-channel MOSFET and p-channel MOS
A CMOS device including an FET is completed.

However, as the miniaturization of the semiconductor integrated circuit device progresses, the short channel effect of the CMOS device becomes remarkable and the breakdown voltage between the source region and the drain region becomes a serious problem.

When the channel length of the gate electrode, that is, the gate length is shortened, the drain depletion layer approaches the source region,
The drain depletion layer and the source depletion layer are connected. In this state, the drain electric field influences the source region side and lowers the diffusion potential in the vicinity of the source region, so that a current flows between the source region and the drain region even if the channel is not formed. This is a phenomenon called punch through, and when this punch through begins,
The drain current sharply increases as the drain voltage increases, and the saturation current stops flowing.

Therefore, in a short-channel CMOS device, a semiconductor region (n-pocket region) made of p-type impurities is formed below an n ^-- type semiconductor region which constitutes part of a source region and a drain region of an n-channel MOSFET.
Under the p ⁻ type semiconductor region that constitutes a part of the source region and the drain region of the p channel type MOSFET.
A MOSFET having a pocket structure in which a semiconductor region (p-pocket region) made of a type impurity is formed and the depletion layer is suppressed from spreading and punch-through is suppressed is used.

Regarding the pocket structure MOSFET, International Elec
tron Device Meetings. "Halo Doping Effects in Subm
icron DI-LDD Device Design "PP. 230 ~ PP. 233, 19
85).

[0010]

However, in the above-mentioned pocket structure MOSFET, in particular, the junction capacitance parasitic between the high-concentration source region and the pocket region or between the high-concentration drain region and the pocket region is increased, and the MOSF is increased.
The present inventor has found that there is a problem that the high-speed operation of ET is hindered.

An object of the present invention is to provide a short channel field effect transistor (Metal Oxide Semiconductor Field Effect transistor).
Transistor (MOSFET) suppresses punch-through between the source and drain regions,
It is to provide a technique capable of realizing high-speed operation of FET.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows. That is, (1) In the semiconductor integrated circuit device of the present invention, under the low-concentration semiconductor region forming part of the source region and the drain region of the LDD structure, the gate electrode is used as a mask to conduct the opposite conductivity to the low-concentration semiconductor region. A pocket region is formed by ion-implanting a p-type impurity, and a gate electrode and a sidewall spacer are used as a mask under a high-concentration semiconductor region that constitutes another part of the source and drain regions of the LDD structure. And a MOSFET having a junction capacitance reduction region formed by ion-implanting an impurity having a conductivity type opposite to that of the pocket region.

(2) In the semiconductor integrated circuit device of the present invention, a low-concentration semiconductor region is formed under the low-concentration semiconductor region forming part of the source region and the drain region of the LDD structure by using the gate electrode as a mask. A pocket region is formed by ion-implanting impurities of opposite conductivity type, and further, a gate electrode and a sidewall spacer are formed below a high-concentration semiconductor region that constitutes another part of the source region and the drain region of the LDD structure. MOSFET in which a low dielectric constant region is formed by ion-implanting an element that forms a silicide having a lower dielectric constant than silicon by using
have.

(3) In the semiconductor integrated circuit device of the present invention, a low-concentration semiconductor region is formed under the low-concentration semiconductor region forming part of the source and drain regions of the LDD structure by using the gate electrode as a mask. A pocket region is formed by ion-implanting impurities of opposite conductivity type, and an element that reacts with silicon to form an insulator is ion-implanted under the pocket region under the pocket region. With an insulator region formed by
Have an ET.

[0016]

According to the above-mentioned means, since the pocket region made of the impurity of the conductivity type opposite to the source region and the drain region of the MOSFET is formed below the source region and the drain region, the punch between the source region and the drain region is formed. Through can be suppressed, and at the same time, the junction capacitance parasitic between the source region and the pocket region or between the drain region and the pocket region of the MOSFET can be reduced.
It is possible to realize high-speed operation.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) CM which is an embodiment of the present invention
A method of manufacturing an OS device will be described with reference to FIGS.

First, as shown in FIG. 1, a p-type well 2 and an n-type well 3 are formed by a self-alignment method on the main surface of a semiconductor substrate 1 made of an n-type silicon single crystal, and then the p-type well is formed. 2 and n-type well 3 have a thickness of about 400n for device isolation.
The m field insulating film 4 is formed.

Next, the p-type impurity (B) is ion-implanted into the channel regions of the p-type well 2 and the n-type well 3 to form the threshold voltage control layer 5. Next, after forming the gate insulating film 6 with a film thickness of about 6.5 nm, the semiconductor substrate 1
A polycrystalline silicon film added with phosphorus is deposited thereon by a CVD (Chemical Vapor Deposition) method, and the polycrystalline silicon film is etched to form a gate electrode 7.

Next, as shown in FIG. 2, n-type impurities (As) are ion-implanted into the p-type well 2 using the gate electrode 7 as a mask, and the low-concentration source region and drain region of the n-channel MOSFET are formed. To form the n ⁻ type semiconductor region 8. Then, p-type impurities (B) are ion-implanted into the p-type well 2 to form an n-pocket region 9 for punch-through control below the n ⁻ -type semiconductor region 8. The n ⁻ type semiconductor region 8 is formed with an impurity concentration of, for example, 10 ¹⁹ / cm ³ ,
The n pocket region 9 is formed with an impurity concentration of, for example, 10 ¹⁸ / cm ³ .

Similarly, p-type impurities (BF ₂ ) are ion-implanted into the n-type well 3 using the gate electrode 7 as a mask, and p
A p ⁻ type semiconductor region 10 forming a low concentration source region and a drain region of the channel MOSFET is formed. Then, an n-type impurity (P) is ion-implanted into the n-type well 3 and p ^- type for punch-through control is formed below the p ⁻ -type semiconductor region 10.
The pocket area 11 is formed.

Next, as shown in FIG. 3, the silicon oxide film deposited by the CVD method on the semiconductor substrate 1 is subjected to RIE (Reacti).
The sidewall spacers 12 are formed on the sidewalls of the gate electrode 7 by etching using the ve ion etching method.

Next, using the gate electrode 7 and the sidewall spacer 12 of the n-channel MOSFET as a mask,
An n-type impurity (P) is ion-implanted into the p-type well 2 so as to have the same depth and the same concentration as the n-pocket region 9.
The mold junction capacitance reduction region 13 is formed. The impurities in the n-type junction capacitance reducing region 13 cancel out the impurities in the n-pocket region 9 located below the n ⁺ -type semiconductor region 15 formed later.

Similarly, p-type impurity (B) is ion-implanted into the n-type well 3 using the gate electrode 7 and the sidewall spacer 12 of the p-channel MOSFET as a mask,
The p-type junction capacitance reducing region 14 is formed so as to have the same depth and the same concentration as the p pocket region 11. The impurities in the p-type junction capacitance reducing region 14 cancel out the impurities in the p-pocket region 11 located below the p ⁺ -type semiconductor region 16 formed later.

At this time, indium (In) is used instead of B as the element for ion implantation into the n-type well 3, and the p-type well 2 is used.
Instead of P as an element to be ion-implanted into
If heavy metal such as b) is used, p-channel type MOSFE
The source region and the drain region of each of the T and n channel type MOSFETs can be made amorphous, and the n ⁺ type semiconductor region 15 and the p ⁺ type semiconductor region 16 to be formed later are formed.
Can be formed shallowly.

Next, as shown in FIG. 4, n-type impurities (As) are ion-implanted into the p-type well 2 by using the gate electrode 7 and the sidewall spacers 12 as a mask, and the high concentration of the n-channel type MOSFET is obtained. An n ⁺ type semiconductor region 15 forming a source region and a drain region is formed.

Similarly, the p-type impurity (BF
₂ ) is ion-implanted to form ap ⁺ type semiconductor region 16 constituting a high concentration source region and a drain region of the p channel type MOSFET. n ⁺ type semiconductor region 15 and p ⁺
The type semiconductor region 16 is formed with an impurity concentration of, for example, 10 ²¹ / cm ³ .

After that, the interlayer insulating film 17 is formed on the semiconductor substrate 1.
Is deposited, the interlayer insulating film 17 is etched to open a contact hole 18, and then the metal film deposited on the interlayer insulating film 17 is etched to form a wiring 19, whereby the CMOS device of this embodiment is formed. Is completed.

As described above, according to this embodiment, the impurity concentrations of the high-concentration source region and the pocket region located under the drain region are canceled out, so that the source region and the pocket region are drained from each other and the drain region and the pocket region are drained from each other. The junction capacitance between them can be reduced.

(Embodiment 2) C which is another embodiment of the present invention
A method of manufacturing a MOS device will be described with reference to FIG. FIG. 5 is a cross-sectional view of essential parts showing the CMOS device of this embodiment.

Similar to the first embodiment, the n ^- type semiconductor region 8 of the n-channel MOSFET is masked with the gate electrode 7 as a mask.
And n-pocket region 9 and p-channel MOSFET
After the p ⁻ type semiconductor region 10 and the p pocket region 11 are formed, the sidewall spacer 1 is formed on the side wall of the gate electrode 7.
Form 2

Next, by using the gate electrode 7 and the sidewall spacers 12 as a mask, an element (for example, oxygen) whose dielectric constant of a silicide formed by reacting with silicon constituting the semiconductor substrate 1 is lower than that of silicon is used. Ions are implanted so as to have the same depth as the n pocket region 9 and the p pocket region 11, and the low dielectric constant region 20 having a dielectric constant lower than that of silicon is n-doped.
^It is formed below the ⁻ type semiconductor region 8 and below the p ⁻ type semiconductor region 10.

Next, ion implantation using the gate electrode 7 and the sidewall spacers 12 as a mask is performed to form an n-channel type M
N ⁺ forming the source and drain regions of the OSFET
The type semiconductor region 15 and the p ⁺ type semiconductor region 16 forming the source region and the drain region of the p-channel MOSFET are formed, respectively.

As described above, according to this embodiment, the dielectric constants of the high-concentration source and drain regions of the n-channel MOSFET and the p-channel MOSFET are made lower than that of silicon (semiconductor substrate 1). Therefore, the junction capacitance between the source region and the pocket region and between the drain region and the pocket region can be reduced.

(Embodiment 3) C which is another embodiment of the present invention
A method of manufacturing a MOS device will be described with reference to FIG. FIG. 6 is a cross-sectional view of essential parts showing the CMOS device of this embodiment.

Similar to the first embodiment, the n ^- type semiconductor region 8 of the n-channel MOSFET is masked with the gate electrode 7 as a mask.
And n-pocket region 9 and p-channel MOSFET
The p ⁻ type semiconductor region 10 and the p pocket region 11 are formed. Next, a silicide formed by reacting with silicon becomes an insulator, and an element (for example, oxygen) having a dielectric constant of this silicide lower than that of silicon is provided below the n pocket region 9 and the p pocket region 11. Ion implantation is performed so that the insulator region 21 is formed.

Next, an n-channel type M is formed by ion implantation using the gate electrode 7 and the sidewall spacers 12 as a mask.
N ⁺ forming the source and drain regions of the OSFET
The type semiconductor region 15 and the p ⁺ type semiconductor region 16 forming the source region and the drain region of the p-channel MOSFET are formed, respectively.

As described above, according to this embodiment, the dielectric constant of the lower portion of the source region and the drain region of each of the n-channel type MOSFET and the p-channel type MOSFET can be made lower than that of silicon constituting the semiconductor substrate 1. Therefore, the junction capacitance between the source region and the pocket region and between the drain region and the pocket region can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0042] For example, in Example 1, after forming the n-type junction capacitance reducing region or p-type junction capacitance reducing region has formed the n ⁺ -type semiconductor region or p ⁺ -type semiconductor region, n ⁺ -type semiconductor region Alternatively, after forming the p ⁺ -type semiconductor region, the n-type junction capacitance reducing region or the p-type junction capacitance reducing region may be formed.

In the second embodiment, the n ⁺ type semiconductor region or the p ⁺ type semiconductor region is formed after the low dielectric constant region is formed, but the n ⁺ type semiconductor region or the p ⁺ type semiconductor region is formed. After that, the low dielectric constant region may be formed.

Further, although the method of manufacturing the CMOS device has been described in the above-mentioned embodiment, the present invention can be applied to all devices including short channel MOSFETs and the manufacturing method thereof.

[0045]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the invention, a short channel MOSFET
Punch-through between the source region and the drain region of the MOSFET can be suppressed, and at the same time, the junction capacitance can be reduced to realize high-speed operation of the MOSFET.

Further, according to the present invention, the above effect can be obtained while maintaining the consistency with the conventional process.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a CMOS device that is an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a CMOS device that is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a CMOS device which is an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a CMOS device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a semiconductor substrate showing a CMOS device which is another embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor substrate showing a CMOS device which is another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 p-type well 3 n-type well 4 field insulating film 5 threshold voltage control layer 6 gate insulating film 7 gate electrode 8 n ⁻ type semiconductor region 9 n pocket region 10 p ⁻ type semiconductor region 11 p pocket region 12 Sidewall spacer 13 n-type junction capacitance reducing region 14 p-type junction capacitance reducing region 15 n ⁺ type semiconductor region 16 p ⁺ type semiconductor region 17 interlayer insulating film 18 contact hole 19 wiring 20 low dielectric constant region 21 insulator region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (10)

[Claims] 1. A semiconductor integrated circuit device having an LDD structure MOSFET, wherein the LDD structure MOSFE is provided.
A pocket region formed by introducing an impurity of a conductivity type opposite to that of the low-concentration semiconductor region is formed below the low-concentration semiconductor region forming part of the source and drain regions of T, and the source and drain regions are formed. 2. A semiconductor integrated circuit device, wherein a junction capacitance reducing region formed by introducing an impurity of a conductivity type opposite to that of the pocket region is formed below a high-concentration semiconductor region forming another part of the semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the junction capacitance reducing region is located at the same depth as the pocket region. 3. The impurity concentration of the junction capacitance reducing region is
2. The semiconductor integrated circuit device according to claim 1, wherein the impurity concentration of the pocket region is the same. 4. The semiconductor integrated circuit device according to claim 1, wherein the impurity forming the junction capacitance reducing region is a heavy metal. 5. A semiconductor integrated circuit device having an LDD structure MOSFET, wherein the LDD structure MOSFET is provided.
A pocket region formed by introducing an impurity of a conductivity type opposite to that of the low-concentration semiconductor region is formed below the low-concentration semiconductor region forming part of the source and drain regions of T, and the source and drain regions are formed. A low-dielectric constant region formed by introducing a silicide having a dielectric constant lower than that of silicon is formed under a high-concentration semiconductor region forming another part of the semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein the low dielectric constant region is located at the same depth as the pocket region. 7. A semiconductor integrated circuit device having an LDD structure MOSFET, wherein the LDD structure MOSFET is provided.
A pocket region formed by introducing an impurity of a conductivity type opposite to that of the low-concentration semiconductor region is formed below the low-concentration semiconductor region forming part of the source and drain regions of T, and the source and drain regions are formed. 2. A semiconductor integrated circuit device, comprising: a high-concentration semiconductor region that constitutes another part of the semiconductor device and an insulator region below the pocket region. 8. A method of manufacturing a semiconductor integrated circuit device having an LDD-structure MOSFET, wherein the low-concentration semiconductor region is formed below a low-concentration semiconductor region forming part of a source region and a drain region of the LDD-structure MOSFET. A step of forming a pocket region by introducing an impurity of a conductivity type opposite to that of the semiconductor region, and a process of forming a pocket region under the high-concentration semiconductor region forming the other part of the source region and the drain region, the conductivity opposite to the pocket region. A step of introducing a type impurity to form a junction capacitance reduction region, a method of manufacturing a semiconductor integrated circuit device. 9. A method of manufacturing a semiconductor integrated circuit device having an LDD-structured MOSFET, wherein the low-concentration semiconductor region is formed below a low-concentration semiconductor region forming part of a source region and a drain region of the LDD-structured MOSFET. A step of forming a pocket region formed by introducing an impurity of a conductivity type opposite to that of the semiconductor region, and a portion of the high-concentration semiconductor region forming the other part of the source region and the drain region is provided with a dielectric constant lower than that of silicon. And a step of forming a low dielectric constant region by introducing a low silicide, the method for manufacturing a semiconductor integrated circuit device. 10. A method of manufacturing a semiconductor integrated circuit device having an LDD-structure MOSFET, wherein the low-concentration semiconductor region is formed below a low-concentration semiconductor region forming part of a source region and a drain region of the LDD-structure MOSFET. Forming a pocket region by introducing an impurity of a conductivity type opposite to that of the semiconductor region, and reacting with silicon in the high-concentration semiconductor region forming the other part of the source region and the drain region and under the pocket region. And a step of forming an insulator region by introducing an element for forming an insulator, the method for manufacturing a semiconductor integrated circuit device.