JPH0846497A - Frequency phase comparator - Google Patents

Abstract

PURPOSE:To provide a frequency phase comparator eventually generating no insensitive zone in the I/O characteristic. CONSTITUTION:A signal FREF is inputted to a flip-flop 20 and a NAND circuit 11a. A signal FVCO is inputted to a flip-flop 21 and a NAND circuit 10a. The output of the flip-flops 20 and 21 are inputted to an AND circuit 23 and OR circuits 11a and 11b. The output of the NAND circuit 10a is delayed by a delay circuit consisting of a NOR circuit 10c, inverter 10b, resistor 10e, and capacitor 10d. They are inputted to the other terminal of the NOR circuit 10c. The output of the NOR circuit 10c is inputted to the OR circuits 11a and 11b and drives respective MOSFETs 26 and 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency phase comparator suitable for use in a phase locked loop circuit or a motor phase control circuit.

[0002]

2. Description of the Related Art In recent years, with the advent of digital audio such as satellite broadcasting, a digital-analog converter for processing audio signals sampled at different sampling frequencies has been popular in the market. Here, for example, the transfer rate of digital audio of satellite broadcasting is about 0.8 Mbit / sec in A mode stereo and about 1.5 Mbit / sec in B mode stereo. In order to cope with such different transfer rates, it is necessary to provide a phase locked loop circuit (hereinafter abbreviated as "PLL") that follows the transfer rate of the digital audio signal sent to the above apparatus. If a phase comparator having only a phase comparison function is used for such a PLL, it cannot be used because the pull-in range becomes narrow, and a frequency phase comparator having a frequency comparison function is necessary.

Conventionally, a circuit as shown in FIG. 5 has been generally used as such a frequency phase comparator. In FIG. 5, 20 and 21 are flip-flops and 2
2 is an inverter, 23 is an AND circuit, 26 is a P-type metal oxide semiconductor field effect transistor (hereinafter abbreviated as “MOSFET”), and 27 is an N-type MO.
It is an SFET. 28 is a power supply terminal, which is connected to the power supply V _DD .

The operation of the conventional frequency / phase comparator configured as described above will be described below. The D flip-flop 20 has one input D terminal suspended at the power supply voltage V _DD , and the clock terminal C receives the signal F _REF . The Q output terminal of the flip-flop 20 is the node A
It is input to the inverter 22 through and is connected to one input terminal of the AND circuit 23. The output of the inverter 22 is input to the gate of the P-type MOSFET.

On the other hand, the flip-flop 21 also has one input D terminal suspended from the power supply voltage V _DD , and the clock terminal C
A signal F _VCO is input to. The Q output terminal of the flip-flop 21 passes through the node B and the AND circuit 23.
Connected to the other input terminal of the N-type MOSFET 2
It is input to the gate of 7. The output of the AND circuit 23 is connected to the reset input terminals of the flip-flops 20 and 21. When both nodes A and B are high, the output of the AND circuit 23 becomes high and the flip-flop 20
And 21 are reset.

Now, FIG. 6 shows a signal waveform diagram of each portion of the circuit of FIG. Waveform F _REF is flip-flop 20
, And the waveform F _VCO is the input of the flip-flop 21. The lower three waveforms A to C correspond to the nodes A to C, respectively. In the figure, when the waveform F _VCO is delayed in phase in the section t ₁ with respect to the waveform F _REF , the section t ₂
Shows the case where the phases of both agree with each other, and the case where the phases are advanced in the section t ₃ .

The Q terminal outputs of flip-flops 20 and 21 are used to control MOSFETs 26 and 27. The output of this frequency phase comparator appearing at node C is
When only the MOSFET 26 is on, that is, the output of the power supply voltage V _DD appears in the section t ₁ , and when only the MOSFET 27 is on, that is, the output of the ground appears in the section t ₃ , both MOSFETs 26 and 27 are off. That is, when there is no input to the section t ₂ or any of the flip-flops 20 and 21, it is always in a high impedance state.

[0008]

However, in the above-mentioned conventional configuration, when the phase difference between F _REF and F _VCO is small, the output pulse widths of the nodes A and B are narrow, so that M
The output pulse may disappear depending on the frequency characteristics of the OSFETs 26 and 27.
There is a problem that a dead zone such as that shown in FIG.

Such a frequency / phase comparator can be implemented by, for example, P
When it is used for LL, it not only cannot follow the input frequency with high accuracy, but it also causes a symptom that the PLL apparently oscillates in the dead zone.
There is a problem that "mode" may occur.

The present invention solves the above problems.
It is an object of the present invention to provide a frequency phase comparator which is essentially free of dead zones in input / output characteristics.

[0011]

In order to achieve this object, a frequency phase comparator of the present invention comprises a first flip-flop with a reset terminal for receiving a first periodic signal at a clock terminal, and a second flip-flop with a reset terminal. A second flip-flop with a reset terminal that receives a periodic signal at its clock terminal, a logic circuit that performs a logical operation between the outputs of the second flip-flop and the first flip-flop, and the first cycle. Pulse signal generating means for receiving a dynamic signal and the second periodic signal, selecting a portion having the same logical value for both, and converting the pulse signal to a pulse signal having a predetermined width, and the pulse signal for the first pulse.
Of the first flip-flop and the second flip-flop, the pulse adding means for uniformly adding the outputs to the second flip-flop and the combining means for combining the outputs of the pulse adding means. The output of the logic circuit is connected to each reset terminal of the flip-flop.

A first flip-flop with a reset terminal for receiving a first periodic signal at a clock terminal;
First delay means for delaying the output of the first flip-flop by a predetermined time τ _{1, a} second flip-flop with a reset terminal for receiving a second periodic signal at its clock terminal, and this second flip-flop. a second delay means for delaying the output of the flop by a predetermined time tau _2, and a logic circuit for performing a logical operation between the output of the second delay means and said first delay means, the second delay means And a synthesizing means for synthesizing the output of the first delay means and the synthesizing means for synthesizing the output of the first delay means, and connecting the output of the logic circuit to the respective reset terminals of the first flip-flop and the second flip-flop. To do.

[0013]

According to this structure, the pulse generation means directly generates a pulse without passing through the first flip-flop and the second flip-flop, and each of the first flip-flop and the second flip-flop is generated. By adding the above-mentioned pulse to the output by the pulse adding means, the MOSFET constituting the synthesizing means can be surely made to respond.

According to the third aspect of the invention, the first delay means is provided at the output of the first flip-flop, and the second delay means is provided at the output of the second flip-flop. Of the pulse applied to the reset terminals of the first flip-flop and the second flip-flop is delayed
Of the pulses output from the second flip-flop and the second flip-flop, and forming a synthesizing means
The FET is surely made to respond.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a frequency phase comparator according to the first embodiment of the present invention. In the figure, flip-flops 20 and 21, an inverter 2
2. The AND circuit 23 and the MOSFETs 26 and 27 are the same as those in the conventional example, and detailed description of this part is omitted. Reference numeral 10 is a pulse generation circuit, which includes a NAND circuit 10a, an inverter 10b, a NOR circuit 10c, a capacitor 10d, and a resistor 10e. Reference numeral 11 is a pulse adding circuit, which is composed of OR circuits 11a and 11b.

With respect to the present embodiment configured as described above,
The operation will be described with reference to the signal waveform diagram of FIG.
The signal F _REF and the signal F _VCO are input to the NAND circuit 10a, and the output thereof is sent to one input terminal of the NOR circuit 10c and the inverter 10b. The output of the inverter 10b is a time constant τ ₀ composed of a resistor 10e and a capacitor 10d.
And is sent to the other input terminal of the NOR circuit 10c.

As a result, the pulse signal D having the pulse width τ ₀ is output to the output of the pulse generation circuit 10 at the moment when both the reference signal F _REF and the target signal F _VCO become high. The pulse signal D is input to one input terminal of each of the NOR circuits 11a and 11b. These NOR circuits 11a,
Nodes A and B are respectively connected to the other input terminal of 11b, and a pulse signal D having a time width τ ₀ is added to outputs E and F of the NOR circuits 11a and 11b, respectively. As a result, the MOSFETs 26 and 27 can be supplied with a signal having a pulse width that reliably operates regardless of how small the phase difference is.

As described above, according to the present embodiment, since the MOSFETs 26 and 27 forming the output stage can be supplied with the pulse for operating reliably, the dead zone does not occur in the input / output characteristics.

FIG. 3 is a circuit diagram of a frequency phase comparator according to the second embodiment of the present invention. In the figure, the flip-flops 20 and 21, the inverter 22, the AND circuit 23, and the MOSFETs 26 and 27 are the same as those in the conventional example, and detailed description thereof will be omitted. 1
Reference numeral 3 is a first delay circuit, and 14 is a second delay circuit.

With respect to the present embodiment configured as described above,
The operation will be described with reference to the signal waveform diagram of FIG.
The first delay circuit 12 delays the output of the flip-flop 20 for a time τ ₁ , and the second delay circuit 13 delays the output of the flip-flop 21 for a time τ ₂ . The reason for making the delay times different in this way is that the time from the output of the flip-flops 20 and 21 to the transmission to the MOSFETs 26 and 27 differs depending on the arrangement on the mask.
This is to correct this. Therefore, it may be considered that the delay times τ ₃ (= τ ₁ = τ ₂ ) are substantially the same.

As a result, the result of taking the logical product by the AND circuit 23 is delayed by the time τ _3, so that the reset timing of the flip-flops 20 and 21 is delayed by τ ₃ . As a result, the width of the pulse output from each of the flip-flops 20 and 21 is extended by the time τ ₃ . Therefore, by providing the first delay circuit 13 and the second delay circuit 13 as described above, the first delay circuit 13 and the second delay circuit 13 are substantially
It is possible to obtain the same effect as that of providing the pulse generating circuit 10 and the pulse adding circuit 11 in this embodiment.

In the above embodiment, the logic circuit is composed of the AND circuit 23, and the synthesizing means is the inverter 22 and M.
It is composed of OSFETs 26 and 27.

Although the reset terminals of the flip-flops 20 and 21 are made high active in the above embodiments, the AND circuit may be made low active and the NAND circuit may be replaced with a NAND circuit. Further, the first delay circuit 12 and the second delay circuit 13 in the second embodiment may be realized by a gate delay, or may be realized by providing a capacitive load for the output impedance of the flip-flops 20 and 21. You may. Besides, the present invention can be variously modified.

[0024]

As described above, in the frequency phase comparator having the structure according to the first aspect of the present invention, the pulse generating means directly generates a pulse without passing through the first flip-flop and the second flip-flop, and By adding the above-mentioned pulse to the respective outputs of the first flip-flop and the second flip-flop by the pulse adding means, it is possible to supply the pulse that the MOSFET constituting the combining means operates reliably, so that the input / output characteristics are in the dead zone. Will not occur.

According to the third aspect of the present invention, the first delay means is provided at the output of the first flip-flop, and the second delay means is provided at the output of the second flip-flop. The propagation of the pulse applied to the reset terminals of the flip-flop and the second flip-flop is delayed, and the width of the pulse output from the first flip-flop and the second flip-flop is widened.
Since the pulse for surely responding to ET can be supplied, the dead zone is not generated in the input / output characteristics.

Furthermore, since the delay time shift due to the difference in the arrangement on the mask can be corrected when integrated into an integrated circuit, the dead zone removal performance is further improved.

Therefore, when the frequency phase comparator of the present invention is used, for example, in a PLL, it can follow the input frequency accurately and there is no dead zone of the input / output characteristics.
A more stable PLL can be configured without generating a mode.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a frequency phase comparator according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of a main part of the frequency phase comparator in the example.

FIG. 3 is a circuit diagram of a frequency phase comparator according to a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram of a main part of the frequency phase comparator in the embodiment.

FIG. 5 is a circuit diagram of a frequency phase comparator in a conventional example of the present invention.

FIG. 6 is a signal waveform diagram of a main part of the frequency phase comparator in the conventional example.

FIG. 7 is an input / output characteristic diagram of the frequency phase comparator in the conventional example.

[Explanation of symbols]

 10 pulse generation circuit 11 pulse addition circuit 20, 21 flip-flop 22 inverter 23 AND circuit 26, 27 MOSFET

Claims (4)

[Claims] 1. A first flip-flop with a reset terminal for receiving a first periodic signal at a clock terminal, and a second flip-flop with a reset terminal for receiving a second periodic signal at a clock terminal. A logic circuit that performs a logical operation between the outputs of the second flip-flop and the first flip-flop, and the first periodic signal and the second periodic signal are received, and the logical values of these two are Pulse generating means for selecting the same portion and converting it into a pulse signal having a predetermined width; and pulse adding means for adding the pulse signal to the outputs of the first flip-flop and the second flip-flop, respectively. Synthesizing means for synthesizing the outputs of the pulse adding means, and the above-mentioned discussions are provided to the reset terminals of the first flip-flop and the second flip-flop, respectively. Frequency phase comparator, characterized in that connecting the output of the circuit. 2. The pulse generating means comprises: a logic circuit that performs a logical operation between the first periodic signal and the second periodic signal; and an integrating circuit that integrates the output of the logic circuit. The frequency phase comparator according to claim 1, which comprises: 3. A first flip-flop with a reset terminal for receiving a first periodic signal at a clock terminal, and first delay means for delaying the output of the first flip-flop by a predetermined time τ ₁ . A second flip-flop with a reset terminal for receiving a second periodic signal at its clock terminal, a second delay means for delaying the output of this second flip-flop by a predetermined time τ ₂ , and this second delay Means and a logic circuit for performing a logical operation between the outputs of the first delay means, and a combining means for combining the output of the second delay means and the output of the first delay means. A frequency phase comparator, wherein the output of the logic circuit is connected to the respective reset terminals of the first flip-flop and the second flip-flop. 4. The predetermined time τ ₁ and the predetermined time τ ₂ are
The frequency phase comparator according to claim 3, which is different from each other.